Different between TTL, ECL and CMOS select the suitable logic Gate Family for following application

1. INTEGRATED CIRCUIT

2. INTRODUCTIONTO LOGIC FAMILIES
• What is a logic Family
It is the way to describe the internal circuitry of the I.C.
• Types of logic Families
We have 7 Basic Logic Families
1) RTL – Resistor Transistor Logic
2) DTL – Diode Transistor Logic
3) IIL – Integrated injection Logic
4) TTL – Transistor – Transistor Logic (Ex 7400 & 5400 Series)
5) ECL – Emitter Coupled Logic (Ex 10000 series)
6) MOS – Metal Oxide Semiconductor
7) CMOS – Complementary Metal Oxide Semiconductor
(Ex. 4000 Series)

3. • Fan out - fan-out of a gate is the ability of its output to drive
several other gates. The more gates it can drive, the higher is its
fan-out
• Gate Delay - Gate delay is the delay offered by a gate for the
signal appearing at its input, before it reaches the gate output
• Noise Margin - Undesirable voltage variations that are
superimposed on normal operating voltage levels are called
noise. All gates are designed to tolerate a certain amount of
noise on their input and output ports. The maximum noise
voltage level that is tolerated by a gate is called noise margin
• Propagation Delay - The time between the logic transition on
an input and the corresponding logic transition on the output of
the logic gate
Basic Concepts

4. TTL
• The full form ofTTL isTransistorTransistor Logic.This is a logic family which
is mainly build up of NPN transistors, PN junction diodes and diffused
resistors.
• The basic building block of this logic family is NAND gate and there are
various subfamilies of this logic gate those are standardTTL .

5. 74xx

6. TTL subfamilies

7. TTL Chips
1 2 3 4 5 6 7
891011121314
1 2 3 4 5 6 7
891011121314
1 2 3 4 5 6 7
891011121314
7404 Hex Inverters
7408 Quad 2-Input AND Gates
7432 Quad 2-Input OR Gates

8. TTL NAND, NOR, XOR
1 2 3 4 5 6 7
891011121314
1 2 3 4 5 6 7
891011121314
1 2 3 4 5 6 7
891011121314
7400 Quad 2-Input NAND Gates
7402 Quad 2-Input NOR Gates
7486 Quad 2-Input EXCLUSIVE-OR Gates

9. TTL Multiple-input Gates
1 2 3 4 5 6 7
891011121314
1 2 3 4 5 6 7
891011121314
7421 Dual 4-Input AND Gates
7430 8-Input NAND Gate

10. TTL NOR and OR Gates
• .If input A is left floating (or connected toVcc), current will go
through the base of transistor Q3, saturating it

11. • If input A is left floating (or connected toVcc), current will go through the base of
transistorQ3, saturating it. If input A is grounded, that current is diverted away from
Q3‘s base through the left steering diode of “Q1,” thus forcing Q3 into cutoff.The same
can be said for input B and transistor Q4: the logic level of input B determines Q4‘s
conduction: either saturated or cutoff.
• Notice how transistors Q3 and Q4 are paralleled at their collector and emitter
terminals. In essence, these two transistors are acting as paralleled switches, allowing
current through resistors R3 and R4 according to the logic levels of inputs A and B.
If any input is at a “high” (1) level, then at least one of the two transistors (Q3 and/or
Q4) will be saturated, allowing current through resistors R3 and R4, and turning on the
final output transistorQ5 for a “low” (0) logic level output.The only way the output of
this circuit can ever assume a “high” (1) state is if both Q3 and Q4 are cutoff, which
means both inputs would have to be grounded, or “low” (0).
Explaining

12. Standard Characteristics forTTL
oVoltage levels.
oNoise Immunity.
oPropagation delays.
oFan-out.

13. Fan-out
oThe fan-out of a gate is the max number of inputs device
that can connected to the output without any problem
oDC fan-out:The number of inputs that an output can drive
with the output in a constant state (high or low).
ofan-out = min(IOH/IIH, IOL/IIL)

14. Propagation Delay forTTL
• The propagation delay is the amount of time that it takes for a change
in the input signal to produce a change in the output signal.
• Propagation delays are 10 nS when driving a 15 pF/400 ohm load.
o tPHL : high-to-low propogation time
o tPLH : low-to-high propogation time
o tPD : propogation delay; tPD= max (tPHL, tPLH)
o tPD determines the gate speed

15. Advantages ofTTL
oFast switching speed
oNo damage is done toTTL devices if inputs are left unconnected
oTTL components are relatively cheaper than the equivalent CMOS
components

16. TTL Input & output voltage
Voltage levels
range from 0 toVcc
whereVcc is typically
4.75V-5.25V.
Voltage range 0V - 0.8V
creates logic level 0
.Voltage range 2V -Vcc
creates logic level 1.

17. Logic Family Characteristics
Complementary metal oxide semiconductor (CMOS)
o most widely used family for large-scale devices
o combines high speed with low power consumption
o usually operates from a single supply of 5 – 15V
o excellent noise immunity of about 30% of supply voltage
o can be connected to a large number of gates (about 50)
o power consumption depends on speed (perhaps 1 Mw)

18. Inverter
pMOS
nMOS
Vi Vo
A A’
pMOS
nMOS
1
10
VGSp
VGSn
VDD = +5V
VGSn = Vi – 0V = 0V – 0V = 0V
VGSp = Vi – (+5V) = 0V – 5V = -5V
When Vi = 0V= 5
VGSn = Vi – 0V = 5V – 0V = 5V
VGSp = Vi – (+5V) = 5V – 5V = 0V
When Vi = +5V
pMOS = “ON” nMOS = “OFF”
pMOS = “OFF” nMOS = “ON”
= 5
= 0
= 0
= 0
= -5
01

19. Logic Design (NOR Gate)
Pull-up
network
Pull-down
network
Inputs
Inputs
NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
A
B
B
VDD
Y
0 0
1
pMOS (1)
nMOS (0)

20. Advantages of CMOS
• High fan out:
o ForTTL logic family the maximum fan out is found to be around 10 .Whereas
for CMOS logic family fan out rating rating may exceed 50.
oHence a larger no of gates can be driven by the output of a single gate.
• .
•

21. Disadvantages of CMOS
o Slow switching speed .
o CMOS devices can easily be destroyed by static electricity .
o No bipolar.
o Some circuits are not practicable.
o Difficult to implement.

23. COST
TTL CMOS

24. ECL
oAlso called as current mode logic
oObtained through bipolar transistor that compute logical functions.
oCHARACTERISTICS/ advantages
oChange state rapidly thus operate at high speed.
oFastest of logic family since propagation time is less than nano seconds.
oDoes not depend on state of the circuit.
oLittle power noise is generated.

25. Configuration :-

26. Explaining
o The basic circuit configuration consists of.
o a pair of NPN transistors with their emitters connected together and fed by a
current source as show in Fig. 1.
o In the steady state, either Q1 or Q2 is on but not both, and the output logic state is
determined by the voltage.
o Difference between the bases of Q1 and Q2 :
o -If Vb1 –Vb2 > 200 mV, Q1 will be turned on and Q2 turned off, and vice versa.

28. ADVANTAGES DISADVANTAGES OF ECL
oAdvantages of ECL
ofastest logic family available
oDisadvantages of ECL
onegative supply
ohigh static power dissipation
olimited choice of manufacturers and devices
olow noise margin

29. Application
oHigh – speed Line Receivers.
oPeak Detectors.
oHigh speedTriggers.
oUsed in the supercomputer .

30. Following table mentions difference betweenTTL, ECL
and CMOS logic families.
CMOSECLTTL
Specification
NAND/NOROR/NORNANDBasic gate
>502510Fan-out
1 MHZ4-551-22Power per
gate(mWatt)
ExcellentGoodVery GoodNoise
Immunity
1-2001-41.5-33tPD (ns)