A NOVEL APPROACH TO MINIMIZE SPARE CELL LEAKAGE POWER CONSUMPTION DURING PHYS...VLSICS Design
In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
FPGA IMPLEMENTATION OF RECOVERY BOOSTING TECHNIQUE TO ENHANCE NBTI RECOVERY I...Editor IJMTER
Negative Bias Temperature Instability is an important lifetime reliability problem in
microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI
since one of the PMOS devices in the memory cell always has an input of ‘0’. Previously proposed
recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by
attempting to keep their inputs at a logic ‘0’ exactly 50% of the time. However, one of the devices is
always in the negative bias condition at any given time. In this paper, we propose a technique called
Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery
mode by slightly modifying the design of conventional SRAM cells to verify its functionality and
quantity area and power consumption.
A NOVEL APPROACH TO MINIMIZE SPARE CELL LEAKAGE POWER CONSUMPTION DURING PHYS...VLSICS Design
In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
FPGA IMPLEMENTATION OF RECOVERY BOOSTING TECHNIQUE TO ENHANCE NBTI RECOVERY I...Editor IJMTER
Negative Bias Temperature Instability is an important lifetime reliability problem in
microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI
since one of the PMOS devices in the memory cell always has an input of ‘0’. Previously proposed
recovery techniques for SRAM cells aim to balance the degradation of the two PMOS devices by
attempting to keep their inputs at a logic ‘0’ exactly 50% of the time. However, one of the devices is
always in the negative bias condition at any given time. In this paper, we propose a technique called
Recovery Boosting that allows both PMOS devices in the memory cell to be put into the recovery
mode by slightly modifying the design of conventional SRAM cells to verify its functionality and
quantity area and power consumption.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)VLSI SYSTEM Design
Learning becomes Fun..
When tedious & difficult topics like Chip Design are explained in simple n creative videos....https://www.udemy.com/vlsi-academy
https://www.udemy.com/vlsi-academy
http://vlsisystemdesign.com/place_decap.php
Once the critical cells are placed on the chip, it becomes necessary to surround the critical cells by decoupling capacitors. The placement of de-coupling capacitors surrounding the pre-placed cells improves the reliability and efficiency of the chip.
A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Phys...VLSICS Design
In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Digital standard cell library Design flowijsrd.com
Commercial library cells are companies 'proprietary information and understandably companies usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. To address the problem the goal of this paper is to discuss the development of standard cell library. This involves in creating new standard cells, layout design, simulation and verification of each standard cell and finally characterization of all cells for timing and functional properties.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running
different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI Physical Design Flow(http://www.vlsisystemdesign.com)VLSI SYSTEM Design
Learning becomes Fun..
When tedious & difficult topics like Chip Design are explained in simple n creative videos....https://www.udemy.com/vlsi-academy
https://www.udemy.com/vlsi-academy
http://vlsisystemdesign.com/place_decap.php
Once the critical cells are placed on the chip, it becomes necessary to surround the critical cells by decoupling capacitors. The placement of de-coupling capacitors surrounding the pre-placed cells improves the reliability and efficiency of the chip.
A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Phys...VLSICS Design
In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Digital standard cell library Design flowijsrd.com
Commercial library cells are companies 'proprietary information and understandably companies usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. To address the problem the goal of this paper is to discuss the development of standard cell library. This involves in creating new standard cells, layout design, simulation and verification of each standard cell and finally characterization of all cells for timing and functional properties.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running
different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
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Optimal State Assignment to Spare Cell inputs for Leakage Recovery
1. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
Optimal State Assignment to Spare Cell inputs for
Leakage Recovery
Vasantha Kumar B.V.P N. S. Murthy Sharma K. Lal Kishore A. Rajakumari
Synopsys (India) Pvt. Ltd BVCE College, Odalarevu, JNT University, Ananthapur, B.V.R.I.T, Narsapure,
Hyderabad, India India, 533210. Hyderabad, India Hyderabad, India
Abstract— This work presents a novel models to minimize leakage power of spare
leakage recovery method based on optimal cells. The proposed method was tested on
state assignment to spare cells in the standard cell based LVDS layout created
layout during post placement stage of the using Synopsys SAED 32/28nm and other
physical design flow. As the technology available Synopsys Design Ware 65nm,
continues to shrinks, leakage power is 45nm, 40nm & 28nm standard cell libraries.
growing at exponential rate due to the With the proposed method we could
aggressive scaling trends of channel observe 48% to 30% reduction in spare cell
lengths, gate oxide thickness, and doping leakage power and 3.8% to 0.7% reduction
profiles combined with an increasing in overall design leakage power.
number of transistors packaged in a single
chip. For the high speed designs with multi Keywords-Spare Cells; State dependent
threshold libraries leakage recovery is the leakage power; Engineering Change Order
biggest challenge apart from meeting (ECO);Constant Insertion; Liberty
timing goals. There is a need for reducing Standard; Subthreshold Leackage Power;
leakage power where ever possible in Power Recovery.
various stages of the design flow. During
I. INTRODUCTION
the physical implementation stages VLSI
designs often needs be corrected due to Minimization of power is one of the most
the changes in specification or design rule important performance metrics in the design of
constraints violations. This correction portable systems and wireless communication
process is called Engineering Change devices. On the other hand the demand for
Order (ECO). Spare cells are redundant greater integration, higher performance, and
cells introduced in the layout during early lower dynamic power dissipation drives scaling
physical design stage whose inputs are of CMOS devices. In nanoscaled CMOS
traditionally tied to Power (VDD) or Ground devices leakage currents have increased
(VSS) and will be used during ECO dramatically leading to higher static power
changes. However these spare or ECO dissipation. There are many leakage sources.
cells in stand-by mode also contributes to a Among them the three major contributors are
significant sub-threshold leakage power in gate oxide tunneling based leakage (~54.79
lower technology nodes. In this paper we percent), subthreshold leakage (~44.5
are proposing a method which involves percent), and Band-To-Band-Tunneling (BTBT)
assigning optimal standby at every input of based leakage (~0.68 percent) for 45 nm Bulk-
spare cell gate based on state dependent CMOS [1]. Other components of leakage
leakage power tables available in library include Gate Induced Drain Leakage (GIDL),
Drain Induced Barrier Lowering (DIBL), etc.,
www.ijascse.in Page 1
2. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
implementations is to meet timing with the
lowest possible leakage. Various system and
architectural strategies are available to reduce
[2]. The magnitude of each leakage component overall power but there still remains the
depends on the process technology used. challenge of arriving at the optimal library cell
However use of high-K dielectric gate helps mix for at-speed lowest power.
reduce gate oxide leakage current. But, when
high-K dielectric is used, the channel mobility A. Multi-threshold libraries cells
degrades leading to reduced performance.
SiGe layer has been used to strain Si to Multi-threshold libraries are used to achieve
overcome reduced carrier mobility to improve the optimal library cell mix for at-speed lowest
performance. This, however, causes an power design. These libraries are released with
increase in subthreshold and BTBT leakage multiple versions typically called as high Vt
current [3]. For 65nm and below scaled CMOS (HVT), standard Vt (SVT) and low Vt(LVT) cells
devices the most important sources of leakage which are differentiated by gate length and/or
are: subthreshold leakage, gate leakage, and gate implant thus providing a variety of trade-
the reversed bias junction BTBT leakage. offs in performance versus leakage. SVT cells
Subthreshold current rises due to lowering of refers to the cell with standard threshold for the
threshold voltage which is scaled to maintain given process technology. The HVT cells refer
transistor ON current on the face of falling to cells with higher threshold voltage than the
power supply voltage. Gate leakage current standard for that process technology. Similarly,
density is increasing due to scaling of oxide the LVT cells are faster than SVT cells but the
thickness resulting in rising tunneling current. leakage is also correspondingly high. Typically
In fact, gate leakage is expected to increase at in high speed CPU design, the percentage of
least by 10 times for each of the future LVT cells from Synthesis netlist can be up to
generations [4]. 99% as the designs are first synthesized using
LVT cells to meet speed target. Even in
Reverse-biased tunneling band-to-band physical design stage since performance target
leakage is increasing due to reduction in is most critical requirement designers put more
junction depletion width that is necessary to effort on timing optimization from placement
contain transistor short channel effects (SCE). through post routing optimization. However
In previous CMOS technologies, dynamic power optimization during placement stages is
power easily wins over leakage power but as done optionally or incrementally if critical timing
shown in Figure. 1, ITRS road map predicted can be met with small total negative slack
that this trend is coming to an end [5]. As (TNS). Final stage leakage power recovery is
technologies scales down, percentage of only done at ECO stages by swapping LVT
leakage power to total power is gradually going cells with HVT cells on positive slack paths.
up with every node as shown in Figure.2.
Leakage is an unwanted byproduct and B. Spare (or) ECO Cells leakage
substantially reduces the operational time of
the devices thereby rendering such devices Design leakage is of particular importance
uncompetitive. It is, therefore, absolutely not only to data path combinational logics,
necessary to eliminate leakage, wherever it is memory blocks and sequential elements but
possible. As leakage becomes increasingly also to standby circuit connections of ECO or
significant in overall power consumption with spare cells. In this paper we are focusing on
feature size reduction, the goal of many standby leakage elimination in spare cells.
www.ijascse.in Page 2
3. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
Spare cells are redundant cells or extra cells
distributed in the design as backup cells to
implement any ECOs that may be required in
the design, at a later stage. Spare cells do not
play any active role in the IC operation. But
some of these cells can be selectively
connected to the normally functioning
electronic components, during revising or
rerouting process of IC. This process is often
referred to as an ECO, and the spare cells can
be alternatively referred to as ECO cells.
Figure 1. ITRS road map showing static power surpassing dynamic power
Based on the performance of the design and
switching activity involved different
combinations of HVT, SVT and LVT cells will 900
be sprinkled in the design core as spare cells. 800
Spare cell not only occupy more chip areas 700
causing substantial impact on the profit but are
Power Consumption[W]
600
also responsible for the more leakage power 500
[6]. The goal of the spare cell is to provide 400
sufficient resources for ECO at every possible 300
location so they are evenly distributed over the 200
whole layout. Spare cells contribute to 5-20% 100
of the total cell count in an IC [7]. As all the
0
spare cells are not used by the additional
2011
2012
2014
2015
2016
2018
2019
2020
2023
2024
2013
2017
2021
2022
2025
2026
design revisions, significant amount of power Switching Power, Logic Switching Power, Memory
leakage exists throughout the life time of the Leakage Power, Logic Leakage Power, Memory
Figure 2. SYSD11 SOC Consumer Stationary Power Consumption
chip due to cells which are not the part of the Trends(from ITRS)
logic. In traditional design flows unused spare
cells inputs are connected to VDD and VSS by foundry. To demonstrate the leakage
supply rails, which is called constant insertion recovery form ECO cells we have shown
technique and they will draw static or leakage experimental results on LVDS design using
current [8]. But this method of always tying Synopsys SAED 32/28nm library and other
inputs of spare cells to GND or VCC will not available Synopsys Design Ware 65nm, 45nm,
ensure less leakage. 40nm & 28nm standard cell libraries [9, 10].
This paper is organized in to six sections.
So, to address this issue we proposed an Section II talks about various ECO techniques
optimal state assignment technique to spare along with prior work to reduce leakage power
cell inputs to reduce their leakage power based in spare cells. Section III talks about state
on state dependent leakage table given dependent leakage power, Section IV talks
about proposed method for reducing spare
cells leakage, Section V talks about
experimental results and Section VI
conclusions.
www.ijascse.in Page 3
4. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
after the SoC is fabricated and issues are
caught during its post silicon validation (i.e very
late design change request). As, the mask
II. SPARE CELL BASED ECO’S AND MOTIVATION
generation cost for the base layers is multiple
Design changes are inevitable and are times the mask generation cost for the metal
increasing in complexity due to rapid growth in layers so addition/deletion or movement of any
Very Large Scale Integrated (VLSI) design standard cell requires the base layer change
size. When these changes occur towards the hence any of such activity is avoided and some
end of the design cycle, where the design has extra unused or redundant standard cells are
converged after significant efforts, it is added in the design for this purpose known as
infeasible to go through the top down design Spare Cells [12, 13, 14, 15, 16, 17, 18]. Spare
flow again. This demands a method called cells are the extra functional cells kept in the
Engineering Change Order (ECO) to keep design for ECO. The number of spare cells and
these changes local to avoid any need to do their type depends on the design complexity
re-synthesis of the whole design. Since the and functionality, but it is advisable to use
ECOs are done very close to tape out, these universal gates so that we can get most of the
are time critical missions and any inefficiency functionality or from the design functionality.
in implementation will directly impact the cost The most commonly useful type of spare cells
of the product. ECOs can be functional and are INV, BUF, NAND and NOR, while the
nonfunctional. Functional ECOs deal with complex gates like XOR are rarely used [19].
making logical changes to the design. The core
objective of a functional ECO is to B. Prior Work and motivation
accommodate RTL changes without major There are some techniques developed to
perturbation to the converged design. reduce leakage in the circuit level, like
Nonfunctional ECOs deal with changes that programmable spare cells which will separate
affect signal integrity, Design Rule Verification power rail from cell structure proposed by
(DRV) or routing. Anubhav Srivastava [6] and spare cell with two
power supply rails proposed by Yung-Chin Hou
A. Implementing ECOs [20]. This approach involves altering design
cells layout (or) creating new libraries which
There are two types of functional ECO requires significant changes to traditional flows.
flows during physical design flow. Also metal-configurable-gate-array spare cell
Unconstrained ECO (Non-Freeze Silicon ECO) ECO flows are becoming popular in recent
flow and Freeze silicon ECO flow [11]. technologies which needs gate array cells
Unconstrained ECO flow is used if the design library provided by library vendor separately
has not been taped out yet or before the mask [21]. During the re-spin these cells can be
preparations of the chip. In this flow there is programmed by metal mask changes for ECO
flexibility of addition/deletion of standard cells implementation, thus reducing mask cost.
while doing the change. These changes are These above mentioned methods are not
first implemented logically with any type or flexible for re-spin designs and methodologies
number of standard cells and then these cells like gate array eco requires new libraries with
are placed and routed incrementally as part of entirely different flows. Engineering change
physical implementation. This do not impact order (ECO) is a highly constrained design
the mask cost for the SoC as all the masks are optimization based on an existing design with
prepared after database is sent to Fab and no tight design schedules due to time to market
spare cells are required in the design. Freeze consideration [22]. Because of these reasons
silicon ECO flow is used if cell placement is designers do not tend to change their design
fixed or the changes are required to be done
www.ijascse.in Page 4
5. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
multiplied with its probability. (Here the
probability refers to the chances that the net
"A" and "B" would be in such a state that the
flows quickly to adopt these new flows which Boolean condition is satisfied). So the total
involves process changes. Also most of the re- leakage power would be the summation of all
spin designs with uses spare cell methodology these "when" conditions multiplied with their
for ECOs also require a smart of way of probability. This can be formulated as shown
reducing spare cell leakages with minimum below:
changes to lower metals. So there is a need for
a smart approach with very minimum changes Pr(when1)*Val1 + Pr(when2)*Val2 + [1 - Pr(when1) -
Pr(when2)]*Total_Val (1)
to existing design flows to address spare cell
leakage. Pr (when1), Indicates the probability that the
III. STATE DEPENDENT LEAKAGE POWER first condition will occur (i.e. "! A*B" will be
true). Pr(when2), Indicates the probability that
The CMOS gates leakage power the second condition will occur (i.e"A*!B" will be
consumption would depend on the different true). The signal probability values Pr(A),
states taken by the inputs of the gates [23]. Pr(B), and so on will be obtained from the net
This is referred as state dependent leakage switching activity file provided as the input to
power consumption of the CMOS gates. For a the EDA tools. General formula for calculation
gate which has “n” inputs, there can be 2n of state dependent leakage power can be
states for which the leakage power given as follows:
consumption is found using the simulation
models of the circuit and is stored in a format Pr(when1)*Val1+Pr(when2)*Val2+…
which can used by the EDA tools to estimate Pr(when2n)*Val2n+[1-Pr(when1)-Pr(when2)-
the state dependent leakage power of those …Pr(when2n)]*Total_Val (2)
gates. Every cell would contribute to the state Where “n” stands for the no of inputs of the gate and
dependent leakage power including the spare
cells in the design. The silicon vendor models Total_Val= cell_leakage_power (3)
these state dependent leakage tables in the
form of .lib (liberty) format [24]. Below is an
example of state dependent leakage values
IV. PROPOSED METHOD
specified in .lib for AND gate:
For illustration let’s assume that the AND
cell_leakage_power : 1.0 ; gate in above example .lib is a spare cell. This
leakage_power() {
when : "!A B" ;
gate can have 4 different combinations (C1,
value : 1.5 ; C2, C3 and C4) of the A and B and hence four
} different state dependent leakage power
leakage_power() { values. If the state dependent leakage power
when : "A !B" ; table of this AND gate would be summarized
value : 2.0 ;
}
as shown in Table 1. As per the traditional
approach, if A and B inputs of the AND gate
The EDA tools will calculate the total are tied to ground, C4 would be evaluated to
leakage power consumption using above be true and the leakage value would be V4 as
power models for leakage power optimization per the table and the probability of occurrence
of functional paths. In the above power model of other conditions C1, C2 and C3 will be zero.
example there are two "when" conditions; each Now from equation (2) Pr(C1), Pr(C2), Pr(C3) is
"when" condition will be evaluated and zero as A and B of the AND gate is tied to
www.ijascse.in Page 5
6. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
Vds2=(nkT/q(1+2+))*ln((A1/A2)eqVdd/nkT+1) (8)
Vds(i)=(nkT/q(1+2+))*ln(1+(Ai-1/Ai)(1-eqVds(i-1)/nkT)) (9)
ground and it’s leakage power can be given
as: Vdd is the power supply voltage. Vg, Vd, and
Psdlp of AND gate =Pr(whenC4)*V4 =1*V4= V4 (4)
Vs are the gate voltage, drain voltage, and
source voltage of the CMOS transistor
Pr(whenC4) = 1 as the inputs are tied to respectively. The bulk is connected to ground.
ground and hence when this condition will be Vth is the zero bias threshold voltage. is the
evaluated to be true. But the leakage value V4 body effect coefficient. is the DIBL
may not be the lowest value of power in the coefficient, representing the effect of Vds
table. This is the problem with the traditional (Vds=Vd-Vs) on threshold voltage. C’ox is the
approach of connecting all spare cell inputs to gate oxide capacitance. 0 is the zero bias
ground. So we propose a state dependent mobility. n is the subthreshold swing coefficient
leakage optimization method to idle spare cells of the transistor. Considering the stacking
where we assign a optimal state to inputs effect equation (8) shows Vds2 in terms of Vdd
which will guarantee lowest possible leakage. and equation (9) shows Vds(i) in terms of Vds(i-
In the proposed algorithm or flow we would be 1) by equating the currents.
finding out the minimum leakage value Vmin for
the spare gate and find the corresponding input TABLE I. STATE DEPENDENT LEAKAGE POWER OF 2-INPUT AND GATE
condition Cmin from .lib models and tie the
When Condition Leakage Power Value
spare cell inputs based on this condition. If a
spare master gate say “spareN” has n input
C1(A, B) V1
pins, then there can be 2n when conditions or
states in the power model table and 2n values
C2(A!, B) V2
of the leakage power values. So the minimum
state dependent leakage power of the spare
C3(A, B!) V3
master as per the proposed flow would be:
P[minsdlp,spareN] = Pr(whenCmin) * Vmin (5) C4(A! B!) V4
As the inputs of the spare master “spareN” are
tied to always evaluate condition Cmin,
P[minsdlp,spareN] = Vmin for the spare master A. Problem formation and algorithm
“spareN”. If there are “m” instances of this
Now our problem is defined as follows:
spare master “spareN” in the design then as
Given a set of placed spare cell instances in a
per the proposed flow the total minimum
layout, our objective is to find the optimal state
leakage power consumption would be:
which gives minimum leakage value form state
Total P[sdlp,spareN] = m * P[minsdlp,spareN] (6) dependent leakage power table of the
corresponding .lib (liberty) files and tie them
The total standby power in equation (6) can be accordingly to their inputs. Our algorithm
represented by model proposed in [25] as SDLPT_Based_Sparecell_Connection_Algorith
follows. m is shown in Figure 3. This proposed
algorithm is written using tcl in order to be used
Isub=Aeq(Vg-Vs-Vth-Vs+Vds)/nkT (1-e-qVds/kT) (7) in placement or post routing stages of physical
design flow. The physical implementation flow
where A=0C’ox(W/Leff)(kT/q)2e1.8 for the proposed method is shown in Figure 4.
www.ijascse.in Page 6
7. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
V. EXPERIMENTAL RESULTS
Our algorithm was used to tie the spare
cells inputs with optimal state which promises
low standby leakage on Low Voltage
Differential Signalling (LVDS) design. We have
used
Figure 3. SDLPT_Based_Sparecell_Connection_Algorithm
TABLE II. LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING HVT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD
% of % of
%
Spare Cell Spare Cell Spare Cell % Spare Cell
Spare Reduction
Total Overall Leakage Leakage in Leakage Reduction Leakage in
Technology Cells in the
S.No Cell Design with Design with in Spare Design
(HVT cells) Count overall
Count Leakage Traditional with Proposed Cells with
(%) Design
Flow Traditional Flow Leakage proposed
leakage
Flow Flow
1 65nm 291 30(10.3) 23.454nW 1.051nW 4.48111 691.515pW 34.20409 2.99428 -1.48111
2 45nm 382 30(7.8) 6.508uW 325.125nW 4.99577 250.049nW 23.09143 3.88702 -1.09577
3 40nm 547 50(9.1) 192.856nW 8.518nW 4.41677 6.987nW 17.9737 3.6519 -0.71677
4 32nm 372 30(8.0) 26.196uW 878.018nW 3.35173 793.798nW 9.59206 3.04 -0.35173
5 28nm 608 50(7.3) 4.376uW 85.092nW 1.94452 54.222nW 36.27838 1.24788 -0.74452
TABLE III. LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING SVT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD
% of % of
%
Spare Cell Spare Cell Spare Cell % Spare Cell
Spare Reduction
Total Overall Leakage Leakage in Leakage Reduction Leakage in
Technology Cells in the
S.No Cell Design with Design with in Spare Design
(SVT cells) Count overall
Count Leakage Traditional with Proposed Cells with
(%) Design
Flow Traditional Flow Leakage proposed
leakage
Flow Flow
1 65nm 289 30(10.3) 305.601nW 15.953nW 5.22021 10.597nW 33.57362 3.52945 -1.72021
2 45nm 383 30(7.8) 21.488uW 1.096uW 5.10052 774.427nW 29.3406 3.65875 -1.40052
3 40nm 546 50(9.1) 1.191uW 49.799nW 4.18128 36.356nW 26.99452 3.08741 -1.08128
4 32nm 378 30(7.9) 87.164uW 3.694uW 4.23799 3.332uW 9.79968 3.83862 -0.43799
5 28nm 553 50(9.0) 35.303uW 789.896nW 2.23748 406.740nW 48.50715 1.16478 -1.03748
TABLE IV. LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING LVT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD
www.ijascse.in Page 7
8. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
% of % of
%
Spare Cell Spare Cell Spare Cell % Spare Cell
Spare Reduction
Total Overall Leakage Leakage in Leakage Reduction Leakage in
Technology Cells in the
S.No Cell Design with Design with in Spare Design
(LVT cells) Count overall
Count Leakage Traditional with Proposed Cells with
(%) Design
Flow Traditional Flow Leakage proposed
leakage
Flow Flow
1 65nm 290 30(10.3) 1.204uW 61.769nW 5.13032 40.283nW 34.78444 3.40656 -1.73032
2 45nm 383 30(7.8) 47.422uW 2.145uW 4.52322 1.510uW 29.60373 3.22739 -1.32322
3 40nm 407 50(12) 2.970uW 224.308nW 7.55246 151.559nW 32.43264 5.23113 -2.35246
4 32nm 340 30(8.8) 578.984uW 31.447uW 5.43141 22.198uW 29.41139 3.8962 -1.53141
5 28nm 560 50(8.9) 123.511uW 2.729uW 2.20952 1.483uW 45.65775 1.21294 -1.00952
TABLE V. LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING OPTIMIAL LIBRARY CELL MIX FOR AT-SPEED LOWEST POWER WITH PROPOSED METHOD
% of % of
%
Technology Spare Cell Spare Cell Spare Cell % Spare Cell
Reduction
Node Total Spare Overall Leakage Leakage in Leakage Reduction Leakage in
in the
S.No (Mix of Cell Cells Design with Design with in Spare Design
overall
HVT, SVT Count Count Leakage Traditional with Proposed Cells with
Design
& LVT %) Flow Traditional Flow Leakage proposed
leakage
Flow Flow
1 65nm 298 30(10.0) 50.242nW 6.018nW 11.97803 3.993nW 33.64905 8.28131 -3.69672
2 45nm 385 30(7.7) 6.161uW 931.709nW 15.12269 669.898nW 28.10008 11.35576 -3.76693
3 40nm 493 50(10.1) 586.520nW 68.188nW 11.62586 47.649nW 30.12114 8.41883 -3.20703
4 32nm 417 30(7.1) 30.655uW 1.817uW 5.92725 1.640uW 9.74133 5.38093 -0.54632
5 28nm 540 50(7.3) 59.705uW 895.802nW 1.50038 481.001nW 46.30499 0.81127 -0.68911
design suits. First 15 sets of layouts as shown
in Table-II, Table-III & Table-IV are
implemented for each threshold (VT) cells
across all mentioned technology libraries
separately to observe the leakage variation.
The second set of 5 layouts as shown in Table-
V are created using all combinations of HVT,
SVT & LVT cells to demonstrate real design
scenario with optimal library cell mix for at-
speed lowest power design. After synthesis we
have done the floorplan, placement and
placement optimizations using Synopsys IC
Compiler®. At this point we inserted various
spare cells into the layout and sprinkled them
Figure 4. Proposed Leakage Minimization Flow evenly across the layout. We have inserted 7
Synopsys SAED 32nm Multi-threshold library to 12% of total design cells as spare cells in
and 65nm, 45nm, 40nm & 28nm Synopsys these layouts. Figure 5 shows the spare cells
Design Ware Multi-threshold libraries distribution in LVDS design which are
consisting of HVT, SVT & LVT cells. For this highlighted in white throughout the layout. We
we carried out synthesis on LVDS RTL using have selected spare cells based on
these technology logical libraries using conclusions made in [9] with majority of INV,
Synopsys’s Design Compiler® to get gate level BUF, NAND, OR and few NOR gates. We have
netlist. We have implemented for sets of also included few scanable flops per each
www.ijascse.in Page 8
9. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
with proposed flow and it is consistent across
different VT cells. This results in 1.7 to 0.7% of
overall designs leakage recovery which is very
clock group. In the second set of layouts in significant for any handheld device chip. The
Table-II the combination of HVT, SVT & LVT results from Table-III shows real design
cells are maintained as per the timing scenario with mix of different VT cells shows
requirements and number of LVT spare cells an overall designs leakage recovery of 3.7% to
are restricted up to 20% of total spare cells. 0.7% with proposed spare cell connections.
Only for 28nm technology 14% LVT cells and Also with the recent enhancements in routing
67% of SVT cells are used during synthesis for technology to handle special power cells comb
meeting timing. For the remaining technologies routing of spare cells as per proposed method
LVT cells percentage is restricted to below 2% is not an issue. The input connections made by
and SVT cell to below 30% of total design cells the tool during the routing as per the proposed
count. HVT cells are used to primarily to optimal inputs states for the spare cells OR
reduce the leakage power by maintain design and XNOR in SAED 32nm layout is shown in
time and total negative slack (TNS). At this Figure 6.
point we have made two copies of these
layouts in each design directory for
demonstrating variation in overall design
leakage due to spare cells when they are
connected in traditional (constant insertion
method) versus proposed methods. After
spreading spare or ECO cells in to the layout at
placement stage we have used our tcl based
algorithm to assign optimal states derived from
state dependent leakage tables to the input of
spare cells. Similarly other set of layout spare
cell inputs are connect to ground (VSS). After
Figure 5. Spare Cells Distribution across the layout in LVDS design
this we proceeded to clock tree synthesis and
finished routing and routing optimizations using
IC Compiler® on all layouts. For this
implementation starting form Synthesis we
have used fast process, high temperature and
high voltage corner which is the worst case
PVT corner for leakage where the leakage
values trend will as expected and without
leakage inversion. Now finally at this point to
analyze the leakage power of the design and
spare cells contribution toward designs
leakage in all layouts we have used
Synopsys’s PrimeTime-PX® signoff power
analysis tool. The result in Table-II shows the Figure 6. Spare Cells OR and XNOR connections after routing
comparison between the spare cell leakage
power numbers between traditional and
proposed flows and their contributions to VI. CONCLUSIONS
overall design leakage. Nearly 48% to 30% of In this paper we proposed a new state
leakage recovery in spare cells is observed dependent leakage tables based connections
www.ijascse.in Page 9
10. Oct. 31 IJASCSE Vol 1 Issue 3, 2012
future", IEEE International Conference on
Microelectronic Systems Education, 2009, pp. 20-
24
[10] Goldman R., Bartleson K., Wood T., Kranen K., Cao
C., Melikyan V., "Synopsys' Interoperable Process
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