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nmos_fabrication_setps for fabrivcationsteps.pptx
- 1. NMOS Fabrication —Step-by- step Basic to intermediate overview with diagrams Generated: Aug 9, 2025
- 2. Overview: NMOS FabricationFlow Start with p-type silicon wafer Isolation (STI or LOCOS) Gate oxide growth and gate formation LDD implant, sidewall spacers, S/D implants Anneal, silicidation, ILD, contacts and metallization
- 3. 1) Starting wafer P-typesilicon wafer (substrate) Clean (RCA) and HF dip to remove native oxide
- 4. 2) Isolation (STI) Etchshallow trenches in silicon where devices will be separated Fill trenches with oxide and planarize (CMP)
- 5. 3) Well /threshold implants Form p-well or n-well as required (implant boron/other dopants) Controls body doping and threshold voltage
- 6. 4) Gate oxideformation Thermal oxidation to grow thin SiO2 layer (~a few nm) High-quality oxide is critical for reliability
- 7. 5) Polysilicon gateformation Deposit polysilicon and dope it to make it conductive Pattern gate with photolithography and etch
- 8. 6) LDD implant(Lightly-Doped Drain) Low-dose n-type implant near gate edges Reduces peak electric field and hot-carrier effects
- 9. 7) Sidewall spacers Depositconformal dielectric and anisotropically etch back Spacers set offset for the heavy S/D implant
- 10. 8) Source/Drain heavyimplant High-dose n+ implant to form low-resistance S/D regions Implant done after spacers to keep junctions offset
- 11. 9) Anneal /dopant activation Rapid thermal anneal (RTA) activates dopants and repairs damage Controls junction depth and electrical activation
- 12. 10) Silicidation andcontacts orm self-aligned silicide (salicide) on S/D and gate to reduce resistance Open contacts in ILD and fill with tungsten or metal plugs
- 13. 11) Metallization &passivation Deposit metal interconnects (Al or Cu damascene process) Add passivation layer and complete back-end processing
- 14. Summary & ModernVariants planar NMOS flow — variants include high-k/metal gate, strained Si, FinFETs specifics (thickness, doses) depend on technology node
Editor's Notes
- #2 High-level process flow for a typical planar NMOS.
- #3 The wafer is the foundation — quality matters.
- #4 Prevents electrical leakage between devices.
- #5 Used in CMOS; for single NMOS on p-substrate this step may be minimal.
- #6 Gate oxide thickness affects threshold and leakage.
- #7 Gate defines where the channel will form.
- #8 Helps device reliability especially at higher Vds.
- #9 Controls overlap capacitance and S/D profile.
- #10 Forms the conductive source and drain contacts.
- #11 Short, high-temperature anneals are common for shallow junctions.
- #12 Silicide lowers contact resistance for better performance.
- #13 Multiple metal layers connect devices into circuits.
- #14 Advanced nodes change materials and geometry.