Details of 8255A

1. Programmable
Peripheral Interface
(PPI) 8255A
Md. Motaleb Hossen Manik
Lecturer
Dept. of CSE, KUET

2. Introduction
• 40 pin IC, contains 3
programmable 8-bit ports
namely port A, B, and port
C
• Port C is divided into 2 four-
bit ports (C upper and C lower)
• Each port can be
programmed to work either
an input or an output port

3. Block Diagram
3
• Contains 2 control
groups
• Group A contains
port A and port C upper
• Group B contains
port B and port C lower

4. Pins and Signals
4
• D7-D0: bidirectional data lines.
Transfer data, control, or status bytes
• A1-A0: used to address the ports and
control word register of 8255

5. Cont.
• WR and RD: allow data
transfer to and from the ports/
control word register and
microprocessor
• CS: used to enable the 8255
• RESET: used to clear the
ports and control register

6. Pins and Signals
6
• PA0-PA7: serves as input,
output, or bidirectional data
lines
• PB0-PB7: serves as input
or output data lines.
• PC0-PC7: serves as
data/control lines. Also
assists the I/O function for
port A and port B

7. Control Word Register
• 8 bits long
• D7 = 0, BSR mode
• D7 = 1, I/O mode

8. Port and Its Modes

9. Port Address Calculation
• Chip is selected when A7
is high and A6-A2 is low
• For 16 bis address, use
A15 to A2 instead of A7-A2

10. BSR Mode

11. I/O Modes: Mode 0
• Simple I/O mode
• All four ports can be used individually
• No handshaking is needed

12. I/O Modes: Mode 1
• Input and output with a simple
handshake
• Uses three pins of C port as the
control signal

13. I/O Modes: Mode 1 as
Input
• STB: an input device loads data into
a port by making STB low
• IBF: an acknowledge signal to the
peripheral
• INTR: interrupt CPU by making this
signal high when STB and IBF and
INTE go high at a time

14. I/O Modes: Mode 1 as
Output
• OBF: goes low when CPU writes a
data byte into a port of 8255 and
informs the peripheral to take the
data
• ACK: peripheral acknowledge by
this signal after it receives data from
8255
• INTR: 8255 sends this signal to the
microprocessor when it receives
ACK from the peripheral

15. I/O Modes: Mode 2
• Only port A operates in this mode.
• Port A is used for both sending and receiving data to and
from the peripheral.
• Five pins of port C (PC3-PC7) are used to carry the
control signals
• When port A operates in mode-2, port B can be operated
in mode-0 or mode-1

16. I/O Modes: Mode 2
• STB: an input device loads data into the port
by making STB low
• IBF: an acknowledge signal to the peripheral
• OBF: goes low when the CPU writes a data
byte into the port and informs the peripheral to
take the data.
• ACK: peripheral acknowledge by this signal
after it receives data from 8255.
• INTR: 8255 sends this signal to the
microprocessor when it receives ACK from the
peripheral.

17. Some Exercises
1. Identify the port address for the
figure
2. Identify the mode 0 control word to
config port A and port cL as output &
port B and port cu as an input port
3. Write a program to read the DIP
switch and display the reading from
port B at port A and port cL at port
cu, respectively
A1
5
A1
A0
.
.
.
Port A
Port
Cu
Port
Cl
Port B
C/
S

18. Solution of Exercise 1
A15 . . A2 A1 A0 Hex Port
1 0 0 0 0 0 8000
H
A
1 0 0 0 0 1 8001
H
B
1 0 0 0 1 0 8002 C
A1
5
A1
A0
.
.
.
Port A
Port
Cu
Port
Cl
Port B
C/
S

19. Solution of Exercise 2
1 0 0 0 1 0 1 0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0

20. Solution of Exercise 3
1 0 0 0 0 0 1 1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Output: Port A, Port cu
Input: Port B, Port CL
=
83H

21. Cont.
MVI A, 83H
STA 8003H
LDA 8001H
STA 8000H
LDA 8002H
ANI 0FH
RLC
RLC
RLC
RLC
LDA 8003H
HLT

22. Exercise 4
• Write a BSR control word
subroutine to set bits PC7
and PC3 and reset them
after 10ms. Use the
schematic as follows and
assume that a delay
subroutine is available
A7
A6
A2
A1
A0
C/S A
B
C
CWR

23. Answer of Exercise 4
A7 A6 A5 A4 A3 A2 A1 A0 Hex Port
1 0 0 0 0 0 0 0 80H A
1 0 0 0 0 0 0 1 81H B
1 0 0 0 0 0 1 0 82H C
1 0 0 0 0 0 1 1 83H CW
R
First, generate port
addresses

24. Cont.
• To set PC7
• To reset PC7
• To set PC3
• To reset PC3
D7 D6 D5 D4 D3 D2 D1 D0 Hex
0 0 0 0 1 1 1 1 0F H
D7 D6 D5 D4 D3 D2 D1 D0 Hex
0 0 0 0 0 1 1 1 07 H
D7 D6 D5 D4 D3 D2 D1 D0 Hex
0 0 0 0 1 1 1 0 0E H
D7 D6 D5 D4 D3 D2 D1 D0 Hex
0 0 0 0 0 1 1 0 06 H

25. Cont.
MVI A, 0FH
OUT 83H
MVI A,07H
OUT 83H
CALL delay
MVI 06H
OUT 83H
MVI 0EH
OUT 83H
RET
Reset PC3
Reset PC3
Set PC3
Set PC7
Stack

26. Exercise 5 (DIY)
Design an interfacing circuit considering the following to read
data from the A/D converter. Use the 8255A in the Memory
Mapped I/O
i. Set up port A to read data
ii. Set up bit PC0 to start conversion and bit PC7 to read
the ready status of the converter
A1
5
A1
A0
.
.
.
Port A
Port
Cu
Port
Cl
Port B
C/
S

27. References
• Microprocessors Principles and Applications by Ajit Pal