This document contains the resume of Aruljothi K. It summarizes her personal and contact details, academic qualifications, work experience, skills, publications, projects, and a declaration. She has an M.E in VLSI Design from Sri Shakthi Institute of Engineering and Technology and a B.E in Computer Science and Engineering from Excel Engineering College. She has over 1 year of work experience as a Transaction Monitoring Officer at Allsec Technologies. Her skills include VLSI concepts, Verilog, VHDL, C/C++, Java, and EDA tools like Cadence and Xilinx. She has published a paper and presented at conferences on power gating techniques.

1. ARULJOTHI.K
8/50- II main road,
 aruljothikcse@gmail.com Udayam nagar,
 91- 9443806834 Velachery,
Chennai-600042,
Tamilnadu.
CAREER OBJECTIVE
To establish myself as a good engineer by working in a Progressive environment that encourages
continuous learning and provides exposure to new ideas for professional growth.
ACADAMIC CREDENTIALS
 M.E [VLSI DESIGN] at Sri Shakthi Institute of Engineering andTechnology, Coimbatore in
2014, with an aggregate of 74%.
 B.E [Computer Science and Engineering] from Excel Engineering College, Namakkal, (Anna
University of Technology, Coimbatore) in 2011 with an aggregate of 79%.
 HSC, Kalaimagal Kalvi Nilayam Girls Higher Secondary School,Erode,in 2007 with 76%.
 SSLC, Kalaimagal Kalvi Nilayam Girls Higher Secondary School, Erode, in 2005 with 84 %.
WORKED EXPERIENCE
Organization : Allsec Technologies,Velachery,Chennai.
Designation : Transaction Monitoring Officer (Dell CQM).
Duration : 2011-2012.
SKILL SET
 Basic knowledge of VLSI concepts of RTL synthesis, Layout, Routing , Timing , CTS,
Placement.
 Familiar with ASIC Back-end Design Methodologies and verification flows, Digital Design
technologies, CMOS fundamentals,VHDL, Verilog HDL.
 Application packages : ModelSim 6.3f, Xilinx 14.2 ISE Suit.
 Programming Languages : C, C++,Java,and J2EE.
 Operating Systems : Windows,Linux.
 Database : MS Access.
 EDA tools : Cadence(Virtuoso Schematic, ADE (L, XL) SOC
Encounter, rc Launch.
 Scripting : Tcl, Perl.

2. JOURNAL PUBLISHED
 Published my PG project “Leakage Power Reduction Using Power Gating And Multi-Vt Techniques“ in
“International Journal of Advanced Research in Computer Engineering & Technology” in Volume 3
Issue 1.
PAPERS PRESENTED
 Participated in International Conference on “Power Gating Using Power Switches” conducted by Easa
College of Engineering and Technology.
 Presented a paper in a National Conference on” Fine Grain power gating Approach Using Sleep Signals”
conducted by EasaCollege of Engineering and Technology.
VLSI PROJECT AND TRAINING
 Completed Net list to GDSII flow for Two Designs.
M.E project done on the topic “Leakage Power Reduction Using Power Gating And
Multi-Vt Techniques”
1) Tool: Cadence Soc Encounter
Design I : dma_mac
Frequency : 125 MHz
Technology : 45nm
Size : 2560 x 2560 μm2
2) Design II : Leon_processor
Gate count : 363936
Frequency : 125 MHz
Technology : 45nm
Size : 988.585 x 705.010 μm2
PERSONAL DETAILS
Date of birth : 22-01-1990
Gender : Female
Marital Status : Married

3. Husband’s Name : P.Vijayasarathy
Languages Known : Tamil,English
DECLARATION
I hereby declare that the above mentioned particulars are true to the best of my knowledge.
Place: Chennai
Date: (ARULJOTHI.K)