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Bhavya Gudipudi
EXTRA CURRICULAR ACTIVITIES
Email ID
Bhavyagudipudi365@gmail.com
MOBILE NO : +91 8106059664
PERSONAL DATA
Date of Birth : 26 August1994
Gender : Female
Nationality : Indian
Marital Status : Single
KNOWN LANGUAGES
Telugu
English
Hindi(Elementary proficiency)
ADDRESS.
H.NO : 11-10-770/3/7,
Raparthi nagar-2,
Khammam,
Telangana.
 CAREER OBJECTIVE
 To be associated with a progressive organization that provides
opportunity to contribute towards the growth of the organization
and also to apply my knowledge which I have gained through my
education.
 EDUCATION QUALIFICATION
 B. tech (Electronics and communication Engineering) in KITS
engineering college with 74.1% from JNTUH (2011-2015).
 Intermediate in Sri vidhya junior college with 75.7%
 SSC in Vignan High School with 72%
 TECHNICAL SKILLS
 C, .NET
 PERSONAL SKILLS
 Confidence and strong belief in completing the assigned work
successfully within a given time.
 Always strives for betterment and perfection in whatever work I
take up
 Ability to work well under pressure and have zeal to learn new
things.
 Positive thinking
• participated in HANDS ON PCB DESIGNING workshop
• participated in quiz competition conducted by THE HINDU
• participated in workshop conducted by ECIL
• participated in EKATHRA conducted by KITS
• Participated in NSS CAMP
B.TECH ACADEMIC PROJECT DETAILS
Project Undertaken
1. An efficient FPGA Implementation of ADVANCED ENCRYPTION STANDARD algorithm
PROJECT DESCRIPTION:
AES is the most secure symmetric encryption technique that has gained worldwide
acceptance the AES based on the Rijndael algorithm is an efficient cryptographic technique that
includes generation of ciphers for encryption and inverse ciphers for decryption higher security and
speed of encryption/decryption is ensured by operators like Sub Bytes, Mix Columns, Shift Rows, and
Key Scheduling.
Extensive research has been conducted at development of s-box, mix columns on dedicated
ASIC and FPGA to speed up the AES algorithm and to reduce circuit area
DECLARATION
I hereby declare that statements made in this document are true to the best of my
knowledge and belief.
PLACE:
DATE:
(Bhavya Gudipudi)

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Bhavya resume fresher

  • 1. Bhavya Gudipudi EXTRA CURRICULAR ACTIVITIES Email ID Bhavyagudipudi365@gmail.com MOBILE NO : +91 8106059664 PERSONAL DATA Date of Birth : 26 August1994 Gender : Female Nationality : Indian Marital Status : Single KNOWN LANGUAGES Telugu English Hindi(Elementary proficiency) ADDRESS. H.NO : 11-10-770/3/7, Raparthi nagar-2, Khammam, Telangana.  CAREER OBJECTIVE  To be associated with a progressive organization that provides opportunity to contribute towards the growth of the organization and also to apply my knowledge which I have gained through my education.  EDUCATION QUALIFICATION  B. tech (Electronics and communication Engineering) in KITS engineering college with 74.1% from JNTUH (2011-2015).  Intermediate in Sri vidhya junior college with 75.7%  SSC in Vignan High School with 72%  TECHNICAL SKILLS  C, .NET  PERSONAL SKILLS  Confidence and strong belief in completing the assigned work successfully within a given time.  Always strives for betterment and perfection in whatever work I take up  Ability to work well under pressure and have zeal to learn new things.  Positive thinking
  • 2. • participated in HANDS ON PCB DESIGNING workshop • participated in quiz competition conducted by THE HINDU • participated in workshop conducted by ECIL • participated in EKATHRA conducted by KITS • Participated in NSS CAMP B.TECH ACADEMIC PROJECT DETAILS Project Undertaken 1. An efficient FPGA Implementation of ADVANCED ENCRYPTION STANDARD algorithm PROJECT DESCRIPTION: AES is the most secure symmetric encryption technique that has gained worldwide acceptance the AES based on the Rijndael algorithm is an efficient cryptographic technique that includes generation of ciphers for encryption and inverse ciphers for decryption higher security and speed of encryption/decryption is ensured by operators like Sub Bytes, Mix Columns, Shift Rows, and Key Scheduling. Extensive research has been conducted at development of s-box, mix columns on dedicated ASIC and FPGA to speed up the AES algorithm and to reduce circuit area DECLARATION I hereby declare that statements made in this document are true to the best of my knowledge and belief. PLACE: DATE: (Bhavya Gudipudi)