Skanda M J is seeking opportunities in VLSI design, verification, and automation. He has a Master's in VLSI Design from Vellore Institute of Technology with a CGPA of 8.29. His projects include investigating memristor crossbar array architecture, implementing delta sigma ADCs, designing low power adders and a BCD adder using carry select correction. He has experience in EDA tools like Cadence and experience working as a transaction risk investigator.

1. Address
302, G.B.Apartment,
Garden School road,
Ankappa layout,
Subramanyapura post
Bangalore- 560 061
Phone: 9686021103
Name: SKANDA M J
Email: skanda.mj@gmail.com
Objective: To utilize the opportunities given, or created by myself to the maximum
extent and accomplish all my goals, by working towards the overall development of the
organization and the individual in the ever expanding field of VLSI Design, Verification
and Automation.
Educational Qualification:
Master of Technology, VLSI Design at Vellore Institute of Technology, Vellore.
COURSE ACADEMIC
YEAR
INSTITUTION UNIVERSITY CGPA
M.Tech, VLSI
Design
2014-15 Vellore Institute of
Technology (VIT)
VIT University 8.29
COURSE INSTITUTION BOARD AGG % ACADEMIC
YEAR
X std V.V.S Pandit
Nehru High
School, Mysore
Karnataka
Secondary
Education
Examination Board
91.2 2005-06
XII std Sadvidya
Composite Pre-
University
College, Mysore
Department Of
Pre-University
Education,
Karnataka
64.83 2007-08
B.E
(ECE)
Bangalore
Institute of
Technology
Visvesvaraya
Technological
University
60.43 2008-12

2. Projects:
1. Investigation of performing matrix multiplication using memristor crossbar array
architecture – Carried out for Master Thesis component of the course.
2. Implementation of continuous time delta sigma ADC Compensated for More than
One Cycle Excess Loop Delay – Carried out as a team of two for research
interest.
3. Design of Clock Mesh for 3D ICs. - Carried out as a team of two for the SET
conference as a part of the course for Fall semester 2014-15. A capacitance based
clock mesh was developed for 2 layer 3D ICs. Tools used – MATLAB, NGSpice.
4. Design of Low Power Multi bit Data Oriented Adders. - Carried out as a team of
three for the SET conference as a part of the course for Winter semester 2014-15.
Analysis of 4 design styles of 2 bit adders and their data dependency for low
power. Tools used – Cadence Virtuoso, MATLAB
5. ASIC implementation of Low power modified BCD adder using Carry Select
Correction technique. –Carried out as a team of three for the lab component as a
part of the course for Winter semester 2014-15. Analysis of Carry select
correction technique and modification of koggistone architecture used in it for
low power. Tools used – Cadence NC Launch, Encounter
6. GSM Based Airport Automation. – Carried out as a team of four for the final year
project during under-graduation course (B.E.) during academic year 2011-2012.
Special Areas of interest: Memory Design, Analog Design, Low Power Design,
Physical Design Automation.
EDA tools: Cadence NC-launch, Virtuoso, RTL Compiler, SOC Encounter, Altera
Quartus II, Modelsim, MATLAB, NG-Spice, Silvaco TCAD.
Programming languages: Verilog, Spice, MATLAB, C, Perl, Tcl, ALP for 8051 and
8086.
Achievements: Secured First Place in Intra-College Aptitude Test 2010-11 conducted by
Placement Cell, BIT.
Participated and Won prizes in Chess Tournaments.
Work experience:
Worked as a Transaction Risk Investigator at Amazon.com for 1 year (October 2012 –
November 2013).

3. Languages Known:
Language Write Speak
English Yes Yes
Kannada Yes Yes
Hindi Yes Yes
German Yes Yes
Telugu No Yes
Tamil No Yes
Personal Details:
Father’s Name: JAYESHA M R
Mother’s Name: SHYAMALA H B
Date of Birth: 26th
August, 1990
Father’s occupation: Bank Official
Mother’s occupation: House-Wife
Hobbies: Playing chess, Volleyball, Sudoku, Acting, Learning new languages.
Please visit my LinkedIn page :- https://in.linkedin.com/in/skanda-m-j-273b4834