3. CMOS VLSI Design
11: Adders Slide 3
Single-Bit Addition
Half Adder Full Adder
A B Cout S
0 0
0 1
1 0
1 1
A B C Cout S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B
S
Cout
A B
C
S
Cout
out
S
C
out
S
C
4. CMOS VLSI Design
11: Adders Slide 4
Single-Bit Addition
Half Adder Full Adder
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
A B C Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A B
S
Cout
A B
C
S
Cout
out
S A B
C A B
out ( , , )
S A B C
C MAJ A B C
5. CMOS VLSI Design
11: Adders Slide 5
PGK
For a full adder, define what happens to carries
– Generate: Cout = 1 independent of C
• G =
– Propagate: Cout = C
• P =
– Kill: Cout = 0 independent of C
• K =
6. CMOS VLSI Design
11: Adders Slide 6
PGK
For a full adder, define what happens to carries
– Generate: Cout = 1 independent of C
• G = A • B
– Propagate: Cout = C
• P = A B
– Kill: Cout = 0 independent of C
• K = ~A • ~B
7. CMOS VLSI Design
11: Adders Slide 7
Full Adder Design I
Brute force implementation from eqns
out ( , , )
S A B C
C MAJ A B C
A
B
C
S
Cout
MAJ
A
B
C
A
B B
B
A
C
S
C
C
C
B B
B
A A
A B
C
B
A
C
B
A A B C
Cout
C
A
A
B
B
8. CMOS VLSI Design
11: Adders Slide 8
Full Adder Design II
Factor S in terms of Cout
S = ABC + (A + B + C)(~Cout)
Critical path is usually C to Cout in ripple adder
S
S
Cout
A
B
C
Cout
MINORITY
9. CMOS VLSI Design
11: Adders Slide 9
Layout
Clever layout circumvents usual line of diffusion
– Use wide transistors on critical path
– Eliminate output inverters
10. CMOS VLSI Design
11: Adders Slide 10
Full Adder Design III
Complementary Pass Transistor Logic (CPL)
– Slightly faster, but more area
A
C
S
S
B
B
C
C
C
B
B
Cout
Cout
C
C
C
C
B
B
B
B
B
B
B
B
A
A
A
11. CMOS VLSI Design
11: Adders Slide 11
Full Adder Design IV
Dual-rail domino
– Very fast, but large and power hungry
– Used in very fast multipliers
Cout
_h
A_h B_h
C_h
B_h
A_h
Cout
_l
A_l B_l
C_l
B_l
A_l
S_h
S_l
A_h
B_h B_h
B_l
A_l
C_l
C_h C_h
12. CMOS VLSI Design
11: Adders Slide 12
Carry Propagate Adders
N-bit adder called CPA
– Each sum bit depends on all previous carries
– How do we compute all these carries quickly?
+
BN...1
AN...1
SN...1
Cin
Cout
11111
1111
+0000
0000
A4...1
carries
B4...1
S4...1
Cin
Cout
00000
1111
+0000
1111
Cin
Cout
13. CMOS VLSI Design
11: Adders Slide 13
Carry-Ripple Adder
Simplest design: cascade full adders
– Critical path goes from Cin to Cout
– Design full adder to have fast carry delay
Cin
Cout
B1
A1
B2
A2
B3
A3
B4
A4
S1
S2
S3
S4
C1
C2
C3
14. CMOS VLSI Design
11: Adders Slide 14
Inversions
Critical path passes through majority gate
– Built from minority + inverter
– Eliminate inverter and use inverting full adder
Cout
Cin
B1
A1
B2
A2
B3
A3
B4
A4
S1
S2
S3
S4
C1
C2
C3
15. CMOS VLSI Design
11: Adders Slide 15
Generate / Propagate
Equations often factored into G and P
Generate and propagate for groups spanning i:j
Base case
Sum:
:
:
i j
i j
G
P
:
:
i i i
i i i
G G
P P
0:00:00inGCP
0:00:00inGCP
0:0 0
0:0 0
G G
P P
i
S
16. CMOS VLSI Design
11: Adders Slide 16
Generate / Propagate
Equations often factored into G and P
Generate and propagate for groups spanning i:j
Base case
Sum:
: : : 1:
: : 1:
i j i k i k k j
i j i k k j
G G P G
P P P
:
:
i i i i i
i i i i i
G G A B
P P A B
0:00:00inGCP
0:00:00inGCP
0:0 0
0:0 0 0
in
G G C
P P
1:0
i i i
S P G
33. CMOS VLSI Design
11: Adders Slide 33
Tree Adder
If lookahead is good, lookahead across lookahead!
– Recursive lookahead gives O(log N) delay
Many variations on tree adders
37. CMOS VLSI Design
11: Adders Slide 37
Tree Adder Taxonomy
Ideal N-bit tree adder would have
– L = log N logic levels
– Fanout never exceeding 2
– No more than one wiring track between levels
Describe adder with 3-D taxonomy (l, f, t)
– Logic levels: L + l
– Fanout: 2f + 1
– Wiring tracks: 2t
Known tree adders sit on plane defined by
l + f + t = L-1
