1. MENTOR
Mr.A.V.Krishna
ASST.PROFESSOR
ECE Dept.
Batch NO:11
Ch.J.Gayathri(11JG1A0421)
A.Satya(11JG1A0403)
S.Tejaswani(12JG5A0402)
K.Amrutha(11JG1A0450)

2. Adders
Full Adders
Ripple Carry Adder
Carry Look Ahead Adder
Carry Save Adder
Carry Select Adder

3. Objectives
The main objective of this project is design and
implementation of different adders, and obtain a
comprehensive overview of different adder’s
Power and delay constraints.

4. Adders are the logic circuits designed to perform high
speed arithmetic operations and are important
components in digital systems because of their
extensive use in other basic operations.

5. Full Adder is a combinational circuit that performs
the addition of three bits. The binary adder circuit is
an important building block of digital arithmetic
circuits.

6. RCA is simple several full adders connected in series
so that the carry must propagate through every full
adder before the addition is complete.

10. Test Vector
Generator
X
Y
A
B
TEST BENCH DUT
X[7:0]
Y[7:0]
S
Co
S[7:0]
Adders

11. X Y C O/P
2 4 0 6
2 6 1 9
3 12 0 15
34 68 1 103
6 14 0 20

13. X Y C EXPECTED
O/P
O/P
2 4 0 6 6
2 6 1 9 9
3 12 0 15 15
34 68 1 103 103
6 14 0 20 20
TEST IS PASSED

14. A carry-look ahead adder improves speed by
reducing the amount of time required to determine
carry bits.

15. Assume you want to add two operands A and B
A=0110
B=0101
Pi=0011
+
For propagator and generator
o Pi = Ai ⊕ Bi
oGi = Ai · Bi
Equations
For Sum and Carry out
oSumi = Pi ⊕ Ci
o Ci+1 = Gi + ( Pi · Ci)
Gi=0100
Sumi=0011
Ci+1=0100

18. Test Vector
Generator
X
Y
A
B
TEST BENCH DUT
X[15:0]
Y[15:0]
S
Co
S[15:0]
Carry
Look
Ahead
Adder

19. X Y C O/P
32 32 0 64
32 32 1 65
8 8 0 16
8 12 1 21
40 32 0 72

21. X Y C EXPECTED
O/P
O/P
32 32 0 64 64
32 32 1 65 65
8 8 0 16 16
8 12 1 21 21
40 32 0 72 72
TEST IS PASSED

22. A carry-save adder is a type of digital adder used
in computer micro architecture to compute.
Full
Adder
Block
Xi Yi
CinCout
Si
Xi Yi Zi
Ci Si
Carr-Save
Adder
Block

23. Assume you want to add two operands A and B
A=0011
B=0101
S=0110
A=0011
B=0101
C=0001
S=0110
C=0001
TS=1000

26. Test Vector
Generator
X
Y
A
B
TEST BENCH DUT
X[7:0]
Y[7:0]
S
Co
S[7:0]
Carry
Save
Adder

27. X Y O/P
16 20 36
24 84 108
2 12 14
24 20 44
16 20 36

29. X Y EXPECTED
O/P
O/P
16 20 36 36
24 84 108 108
2 12 14 14
24 20 44 44
16 20 36 36
TEST IS PASSED

30. In electronics, a carry-select adder is a particular way
to implement an adder, which is a logic element that
computes the (n+1)-bit sum of two n-bit numbers. The
carry-select adder is simple but rather fast, having a
gate level depth of O(√n) .

33. Test Vector
Generator
X
Y
A
B
TEST BENCH DUT
X[7:0]
Y[7:0]
S
Co
S[7:0]
Carry
Select
Adder

34. X Y C O/P
6 2 0 8
2 5 1 8
0 4 0 4
8 1 1 10
8 8 0 16

36. X Y C EXPECTED
O/P
O/P
6 2 0 8 8
2 5 1 8 8
0 4 0 4 4
8 1 1 10 10
8 8 0 16 16
TEST IS PASSED

37. A field programmable gate array (FPGA) is a
semiconductor device that can be configured by the
customer or designer after manufacturing hence the
name “field programmable”.

38. Techniques No. Of Gates Delay
8 bit Ripple carry adder
16 bit Ripple carry adder
26
50
20.394ns
33.378ns
16 bit Carry Look Ahead
Adder
38 13.902ns
8 bit Carry Save Adder 25 18.644ns
8 bit Carry Select Adder 26 17.026ns

39. •8 bit ripple carry adder has less delay and gate count
compared with 16 bit ripple carry adder. As no. of bits
increase, the delay increases.
•In Carry look ahead adder the grouping of four 4 bit
ripple carry adders will result in reducing the no .of gate
count and delay
•When compared to ripple carry adder the gate count
and delay is less in carry save adder .
•When compared to ripple carry adder the delay is less in
carry select adder but the gate count remains same.

40. Finished Tasks
Implementation
 Ripple Carry Adder
 Carry Look Ahead
Adder
 Carry Save Adder
 Carry Select Adder
Pending Tasks
FPGA Configuration