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Presentation on
DESIGN PROJECTS
EEE 454
VLSI I Laboratory
Prepared By:
Group -1
Naimul Hassan Md. Redwan Islam
Student No ...
DESIGN PROJECT 1:
OPTIMUM DESIGN
OF A 3 INPUT XOR
GATE
KEY ALGORITHM
CMOS
TRANSMISSION
GATE
CMOS
TRANSMISSION
GATE
CMOS
TRANSMISSION
GATE
CMOS
TRANSMISSION
GATE
CMOS NOT
GATE
B
...
Cadence Schematic of CMOS 3 input XOR gate
Symbol Created from the Schematic
Simulation Circuit for CMOS 3 input XOR gate
Timing Simulation Result in ADE L
Average Delay
Calculated
from Cadence
Calculator
About 152 ps
Final Layout Design of CMOS 3 input XOR Gate
Area Calculation of the Layout
Total Length
4.22μm
Total Width
3.27μm
Total Area
13.79μm2
Product of Area and
Propagation delay
318,604.16 μm2 ps2
DESIGN PROJECT 2 :
DESIGN OF ALU WITH
SHIFTER
ALU
A
B
S
Cin
Shifter
H0
H1
F
Cout
O
Operations of the ALU
Operation No F Cout
1 A 0
2 A+1 1 if A = 24 -1
3 A+B 1 if (A+B) ≥ 24
4 A+B+1 1 if (A+B) ≥ 24 -1
5 A-...
Operations of the shifter
H1 H0 Operation Function
0 0 O=F Transfer (no shift)
0 1 O=SHR(F) Shift 1-bit right
1 0 O=SHL(F)...
Arrangement of Operations selected for Group 1
S2 S1 S0 Cin Operation
0 0 0 0 3
0 0 0 1 6
0 0 1 0 2
0 0 1 1 1
0 1 0 0 4
0 ...
Function Mapping for Adder Inputs
S2 S1 S0 Cin
F Xi Yi Cin *
0 0 0 0 A+B Ai Bi 0
0 0 0 1 A-B Ai ~Bi 1
0 0 1 0 A+1 Ai 0 1
0...
Final Equation for Adder Inputs
SCHEMATICS OF
BASIC GATES
SCHEMATICS OF
LOGIC BLOCKS
Final Schematic for logical simulation
Simulation results
THANKS
Vlsi presentation final
Vlsi presentation final
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Vlsi presentation final

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This presentation was VLSI I laboratory project, which was the most painful, yet the most satisfying, the most challenging, yet the most entertaining, the most tiresome, yet the most amusing and maybe the most memorable project of my BUET life, with the most talented mind I have ever seen, Naimul Hassan, (of course, he did almost all of the work, i just volunteered). The presentation contains only raw information about our work and the cells and schematics of Cadence, but it surely missed the enormous memories behind it -- the sleepless nights, hours and hours in front of PC, confusing simulation results, confusing errors, recursive DRC and LVS errors, and after the completion, me and Naim, hugging each other and crying with happiness. Surely this was the most memorable project of my life till now (and if I don't get VLSI II, this would be the most memorable project of my entire life). A really special thanks to Dr. A. B. M. Harun-Ur-Rashid Sir, Professor, Department of Electrical and Electronic Engineering, BUET and Kanak Datta Sir, Lecturer, Department of Electrical and Electronic Engineering, BUET, for assigning us the project in order to get a good practice of the most valuable software in the world Cadence.

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Vlsi presentation final

  1. 1. Presentation on DESIGN PROJECTS EEE 454 VLSI I Laboratory Prepared By: Group -1 Naimul Hassan Md. Redwan Islam Student No – 1006074 Student No - 1006066
  2. 2. DESIGN PROJECT 1: OPTIMUM DESIGN OF A 3 INPUT XOR GATE
  3. 3. KEY ALGORITHM CMOS TRANSMISSION GATE CMOS TRANSMISSION GATE CMOS TRANSMISSION GATE CMOS TRANSMISSION GATE CMOS NOT GATE B B A ~A ~B C ~C C A xor B A xor B xor C
  4. 4. Cadence Schematic of CMOS 3 input XOR gate
  5. 5. Symbol Created from the Schematic
  6. 6. Simulation Circuit for CMOS 3 input XOR gate
  7. 7. Timing Simulation Result in ADE L
  8. 8. Average Delay Calculated from Cadence Calculator About 152 ps
  9. 9. Final Layout Design of CMOS 3 input XOR Gate
  10. 10. Area Calculation of the Layout Total Length 4.22μm Total Width 3.27μm Total Area 13.79μm2
  11. 11. Product of Area and Propagation delay 318,604.16 μm2 ps2
  12. 12. DESIGN PROJECT 2 : DESIGN OF ALU WITH SHIFTER
  13. 13. ALU A B S Cin Shifter H0 H1 F Cout O
  14. 14. Operations of the ALU Operation No F Cout 1 A 0 2 A+1 1 if A = 24 -1 3 A+B 1 if (A+B) ≥ 24 4 A+B+1 1 if (A+B) ≥ 24 -1 5 A-B-1 1 if A > B 6 A-B 1 if A ≥ B 7 A-1 1 if A ≠ 0 8 A 1 9 A|B 0 10 A^B 0 11 A&B 0 12 A’ 0
  15. 15. Operations of the shifter H1 H0 Operation Function 0 0 O=F Transfer (no shift) 0 1 O=SHR(F) Shift 1-bit right 1 0 O=SHL(F) Shift 1-bit left 1 1 O=0 Transfer 0
  16. 16. Arrangement of Operations selected for Group 1 S2 S1 S0 Cin Operation 0 0 0 0 3 0 0 0 1 6 0 0 1 0 2 0 0 1 1 1 0 1 0 0 4 0 1 0 1 5 0 1 1 0 7 0 1 1 1 8 1 0 0 0 11 1 0 1 0 9 1 1 0 0 10 1 1 1 0 12 otherwise Clear F
  17. 17. Function Mapping for Adder Inputs S2 S1 S0 Cin F Xi Yi Cin * 0 0 0 0 A+B Ai Bi 0 0 0 0 1 A-B Ai ~Bi 1 0 0 1 0 A+1 Ai 0 1 0 0 1 1 A Ai 0 0 0 1 0 0 A+B+1 Ai Bi 1 0 1 0 1 A-B-1 Ai ~Bi 0 0 1 1 0 A-1 Ai 1 0 0 1 1 1 A Ai 1 1 1 0 0 0 A & B A & B 0 0 1 0 1 0 A | B A | B 0 0 1 1 0 0 A^B Ai Bi 0 1 1 1 0 ~A ~Ai 0 0 otherwise 0 0 0 0
  18. 18. Final Equation for Adder Inputs
  19. 19. SCHEMATICS OF BASIC GATES
  20. 20. SCHEMATICS OF LOGIC BLOCKS
  21. 21. Final Schematic for logical simulation
  22. 22. Simulation results
  23. 23. THANKS

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