The document summarizes a research paper that proposes a low density parity check (LDPC) algorithm for insertion/deletion channels. It begins by providing background on LDPC codes and how they are finding increasing use for reliable information transfer over bandwidth-constrained links with noise. It then describes the specific system model of a concatenated coding scheme using an outer error correcting code and inner marker code. The document analyzes the achievable transmission rates using this scheme through both bit-level and symbol-level maximum a posteriori probability (MAP) detection algorithms. It finds that the symbol-level approach confirms an advantage over codes optimized for additive white Gaussian noise channels.
LDPC BASED ERROR CORRECTION WITH BIT LEVEL AND SYMBOL LEVEL SYNCHRONIZATION USING MARKER CODE OPTIMIZATION
Low-density parity check code with error-correction capabilities and Marker code for synchronization purposes are used
The marker code structures offer the ultimate achievable rate when standard bit-level synchronization are performed
Symbol-level synchronization algorithm works on group of bits and show how it improves the achievable rate along with the error rate performance
When multiple pass decoding is performed the extrinsic information transfer (EXIT) charts are used to analyze the receiver
This document provides an overview of coding theory and recent advances in low-density parity-check (LDPC) codes. It discusses Shannon's channel coding theorem and how modern error-correcting codes achieve rates close to channel capacity. LDPC codes are described as having sparse parity-check matrices and being decoded iteratively using message passing. The performance of LDPC codes can be analyzed using density evolution and threshold calculations. Linear programming decoding is introduced as an alternative decoding approach that has connections to message passing decoding.
A new channel coding technique to approach the channel capacityijwmn
After Shannon’s 1948 channel coding theorem, we have witnessed many channel coding techniques developed to achieve the Shannon limit. A wide range of channel codes is available with different complexity levels and error correction performance. Many powerful coding schemes have been deployed in the power-limited Additive White Gaussian Noise (AWGN) channel. However, it seems like we have arrived at an end of advancement path, for most of the existing channel codes. This article introduces a new coding technique that can either be used as the last coding stage of concatenated coding scheme or in parallel configuration with other powerful channel codes to achieve reliable error performance with moderately complex decoding. We will go through an example to understand the overall approach of the proposed coding technique, and finally we will look at some simulation results over an AWGN channel to demonstrate its potential.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An efficient transcoding algorithm for G.723.1 and G.729A ...Videoguy
This document proposes an efficient transcoding algorithm to translate between the G.723.1 and G.729A speech coding standards. The algorithm has four main steps: 1) converting line spectral pair parameters between the two codecs, 2) converting pitch intervals using a smoothing technique, 3) performing a fast adaptive codebook search, and 4) performing a fast fixed codebook search. Objective and subjective tests show the algorithm achieves comparable speech quality to tandem encoding/decoding with 26-38% lower complexity and shorter delay.
The document discusses a study that implemented low density parity check (LDPC) decoding using a min sum algorithm with reduced complexity compared to existing methods. It used quadrature phase-shift keying (QPSK) modulation to improve bit error rate over previous approaches that used binary phase-shift keying (BPSK) modulation. The proposed method was able to achieve a lower bit error rate than other existing techniques using fewer iterations, improving performance flexibility by varying the code size. It implemented LDPC decoding on an irregular parity check matrix using a split row technique to reduce interconnect complexity and increase parallelism in the row processing stage compared to standard decoding algorithms.
1) The document discusses a Max Log MAP algorithm for decoding turbo codes used in LTE systems. Max Log MAP reduces complexity compared to the Log MAP algorithm while maintaining similar decoding performance.
2) Turbo codes achieve error correction close to the Shannon limit through iterative decoding between two soft-input soft-output decoders using extrinsic information.
3) The Max Log MAP algorithm approximates the logarithm calculation in turbo decoding to reduce complexity, maintaining performance close to but slightly worse than the standard Log MAP algorithm.
REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N VLSICS Design
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
LDPC BASED ERROR CORRECTION WITH BIT LEVEL AND SYMBOL LEVEL SYNCHRONIZATION USING MARKER CODE OPTIMIZATION
Low-density parity check code with error-correction capabilities and Marker code for synchronization purposes are used
The marker code structures offer the ultimate achievable rate when standard bit-level synchronization are performed
Symbol-level synchronization algorithm works on group of bits and show how it improves the achievable rate along with the error rate performance
When multiple pass decoding is performed the extrinsic information transfer (EXIT) charts are used to analyze the receiver
This document provides an overview of coding theory and recent advances in low-density parity-check (LDPC) codes. It discusses Shannon's channel coding theorem and how modern error-correcting codes achieve rates close to channel capacity. LDPC codes are described as having sparse parity-check matrices and being decoded iteratively using message passing. The performance of LDPC codes can be analyzed using density evolution and threshold calculations. Linear programming decoding is introduced as an alternative decoding approach that has connections to message passing decoding.
A new channel coding technique to approach the channel capacityijwmn
After Shannon’s 1948 channel coding theorem, we have witnessed many channel coding techniques developed to achieve the Shannon limit. A wide range of channel codes is available with different complexity levels and error correction performance. Many powerful coding schemes have been deployed in the power-limited Additive White Gaussian Noise (AWGN) channel. However, it seems like we have arrived at an end of advancement path, for most of the existing channel codes. This article introduces a new coding technique that can either be used as the last coding stage of concatenated coding scheme or in parallel configuration with other powerful channel codes to achieve reliable error performance with moderately complex decoding. We will go through an example to understand the overall approach of the proposed coding technique, and finally we will look at some simulation results over an AWGN channel to demonstrate its potential.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An efficient transcoding algorithm for G.723.1 and G.729A ...Videoguy
This document proposes an efficient transcoding algorithm to translate between the G.723.1 and G.729A speech coding standards. The algorithm has four main steps: 1) converting line spectral pair parameters between the two codecs, 2) converting pitch intervals using a smoothing technique, 3) performing a fast adaptive codebook search, and 4) performing a fast fixed codebook search. Objective and subjective tests show the algorithm achieves comparable speech quality to tandem encoding/decoding with 26-38% lower complexity and shorter delay.
The document discusses a study that implemented low density parity check (LDPC) decoding using a min sum algorithm with reduced complexity compared to existing methods. It used quadrature phase-shift keying (QPSK) modulation to improve bit error rate over previous approaches that used binary phase-shift keying (BPSK) modulation. The proposed method was able to achieve a lower bit error rate than other existing techniques using fewer iterations, improving performance flexibility by varying the code size. It implemented LDPC decoding on an irregular parity check matrix using a split row technique to reduce interconnect complexity and increase parallelism in the row processing stage compared to standard decoding algorithms.
1) The document discusses a Max Log MAP algorithm for decoding turbo codes used in LTE systems. Max Log MAP reduces complexity compared to the Log MAP algorithm while maintaining similar decoding performance.
2) Turbo codes achieve error correction close to the Shannon limit through iterative decoding between two soft-input soft-output decoders using extrinsic information.
3) The Max Log MAP algorithm approximates the logarithm calculation in turbo decoding to reduce complexity, maintaining performance close to but slightly worse than the standard Log MAP algorithm.
REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N VLSICS Design
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
Performance analysis and implementation for nonbinary quasi cyclic ldpc decod...ijwmn
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with
significantly better performance. Although various kinds of low-complexity iterative decoding algorithms
have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high
complexity and long latency. In this brief, highly efficient check node processing scheme, which the
processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are
proposed. Compare with previous works, less than 52% could be reduced for the latency of check node
unit. In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NBQC-
LDPC decoder.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
Master's Degree Thesis on High Order Modulation and Coding Shemes for Satellite Transmitters
Advisors
Prof.dr. Roberto Garello
Eng.dr. Domenico Giancristofaro
The Reliability in Decoding of Turbo Codes for Wireless CommunicationsIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Turbo codes are a type of error correcting code that can achieve performance close to the theoretical maximum allowed by Shannon's limit. Turbo codes use an iterative decoding process between two recursive systematic convolutional encoders separated by an interleaver. This iterative decoding allows turbo codes to correct errors very efficiently. Turbo codes are used in applications like deep space communications and mobile phone networks due to their ability to operate reliably at low signal-to-noise ratios.
This document summarizes a research paper that proposes using genetic algorithms and differential evolution to optimize the interleaver design for turbo codes. Turbo codes achieve performance close to the theoretical limit by using parallel concatenation of recursive systematic convolutional codes. The interleaver permutes the input bits, which affects turbo code performance. This research aims to use evolutionary algorithms to find higher performing turbo code interleavers compared to conventional designs. It compares the proposed approaches to the traditional genetic algorithm method and finds that differential evolution performs well for optimizing turbo code interleaver design.
This document discusses using low density generator matrix (LDGM) codes for source coding and joint source-channel coding of correlated sources. Key points:
- LDGM codes can achieve near-Shannon limit performance for channel coding with lower complexity than LDPC codes. Serial and parallel concatenated LDGM codes are proposed.
- LDGM codes are applied to source coding of correlated sources modeled by a hidden Markov model. Simulation results show the codes achieve rates close to the theoretical limits.
- LDGM codes are also used for joint source-channel coding of correlated sources over independent noisy channels. Different decoding schedules are evaluated. Results show the codes perform well for both AWGN and Rayleigh fading channels.
Error correcting coding has become one essential part in nearly all the modern data transmission and
storage systems. Low density parity check (LDPC) codes are a class of linear block code has the superior
performance closer to the Shannon’s limit. In this paper two error correcting codes from the family of
LDPC codes specifically Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Nonbinary
low density parity check (NB-LDPC) codes are compared in terms of power consumption, number of
iterations and other parameters. For better performance of EG-LDPC codes, Maximum Likelihood (ML)
Algorithm was proposed. NB-LDPC codes can provide better error correcting performance with an
average of 10 to 30 iterations but has high decoding complexity which can be improve by EG-LDPC codes
with ML algorithm having only three iterations for detecting and correcting errors. One step majority logic
decodable (MLD) codes is a subclass of EG-LDPC codes are used to avoid high decoding complexity. The
power Consumed by NB-LDPC codes is 2.729W whereas the power consumed by EG-LDPC codes with ML
algorithm is 1.148W.
The document describes a new code consistency maintenance protocol called DHV for wireless sensor networks. DHV allows nodes to detect version differences and identify newer code versions using only necessary bit-level information, requiring far fewer messages and bits transmitted than previous protocols. Simulations and experiments show DHV reduces messages by 50%, converges faster, and reduces transmitted bits by 40-60% compared to the state-of-the-art DIP protocol.
This document discusses the design and implementation of low density parity check (LDPC) codes. It begins with an introduction to LDPC codes, including their representation using parity check matrices and Tanner graphs. It then describes encoding and decoding algorithms for LDPC codes, focusing on belief propagation and message passing algorithms for decoding. Specifically, it covers hard decision decoding, soft decision decoding, and how LDPC codes can detect and correct errors. The document also discusses the construction of LDPC codes, mentioning methods proposed by Gallager, McKay and Neal, and for repeat accumulation codes.
This document provides an overview of low-density parity-check (LDPC) codes. It discusses Shannon's coding theorem and the evolution of coding technology. LDPC codes were invented by Gallager in 1963 and have simple decoding algorithms that allow them to achieve performance close to the Shannon limit. The document defines regular and irregular LDPC codes using parity check matrices and Tanner graphs. It also discusses code construction, applications of LDPC codes in wireless communications standards, and concludes that LDPC codes are becoming the mainstream in coding technology.
This document discusses low-density parity-check (LDPC) codes. It begins with an overview of LDPC codes, noting they were originally invented in the 1960s but gained renewed interest after turbo codes. It then covers LDPC code performance and construction, including generator and parity check matrices. Various representations of LDPC codes are examined, such as matrix and graphical representations using Tanner graphs. Applications of LDPC codes include wireless, wired, and optical communications. In conclusions, turbo codes achieved theoretical limits with a small gap and led to new codes like LDPC codes, which provide high-speed and high-throughput performance close to the Shannon limit.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document discusses turbo codes, a type of forward error correction code. Turbo codes use parallel concatenated convolutional encoders with pseudorandom interleaving and iterative decoding. This structure allows turbo codes to achieve error correction performance very close to the theoretical limit defined by the Shannon capacity. Some key advantages of turbo codes are their remarkable power efficiency and ability to support delivery of multimedia services through design tradeoffs. However, turbo codes also have long latency and poor performance at very low bit error rates.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
The document presents a novel approach for forward error correction (FEC) decoding based on the belief propagation (BP) algorithm in LTE and WiMAX systems. Specifically, it proposes representing tail-biting convolutional codes and turbo codes using parity check matrices, which allows both code types to be decoded using a unified BP algorithm. This provides a lower complexity decoding architecture compared to traditional approaches. Simulation results show the BP algorithm achieves near-identical performance to maximum a posteriori (MAP) decoding for turbo codes, while being less complex. Representing codes with parity check matrices thus enables a universal decoder for LTE and WiMAX using a single BP algorithm.
The document discusses turbo codes, which are a type of error correction code used in communication systems. Turbo codes work by concatenating two or more simple convolutional codes with an interleaver between them. This structure allows for iterative decoding that can achieve performance close to the theoretical maximum. The key aspects covered are the turbo code concepts, log likelihood algebra used in decoding, the purpose and types of interleaving, and how recursive systematic convolutional codes are used as the component codes of a turbo code.
The document discusses turbo codes, which are a type of error correction code that can achieve low bit error rates close to the Shannon limit. Turbo codes work by encoding the data using two or more simple component codes on interleaved versions of the input and then iteratively decoding the outputs of the component decoders. This iterative decoding allows turbo codes to outperform conventional codes with lower complexity. The document provides background on channel coding, forward error correction, and convolutional codes before explaining how turbo codes are constructed and decoded.
This document summarizes forward error correction techniques using convolutional encoders and Viterbi decoders. It first provides background on communication channels and the need for error correction when transmitting data. It then describes convolutional coding, a technique that maps a continuous stream of input bits to a continuous stream of encoded output bits using shift registers, with the encoded bits depending on current and past input bits. The key aspects of convolutional encoders are discussed, including parameters like the number of output bits, input bits, and shift registers. Generator polynomials are also introduced as characterizing the encoder connections. Viterbi decoding is highlighted as a maximum likelihood algorithm for decoding the trellis structure of convolutional codes based on soft decisions.
Survey on Error Control Coding TechniquesIJTET Journal
This document discusses various error control coding techniques used to ensure correct data transmission over noisy channels. It describes automatic repeat request and forward error correction as the two main approaches. Specific coding schemes covered include parity codes, Hamming codes, BCH codes, Reed-Solomon codes, LDPC codes, convolutional codes, and turbo codes. Reed-Solomon codes can correct multiple burst errors with high code rates. LDPC codes provide performance close to the Shannon limit with lower complexity than turbo codes. The document provides an overview of the coding techniques and their encoding and decoding processes.
Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers IJECEIAES
This document presents a study on the performance of a low density parity check (LDPC) coded orthogonal frequency division multiplexing (OFDM) system using space time block coding (STBC) under various digital modulations and channel conditions. The system incorporates a 3/4 rate convolutional encoder and a LDPC encoder. At the receiver, maximum ratio combining is implemented for channel equalization. Simulation results show that the LDPC coded OFDM system outperforms an uncoded system, and provides lower bit error rates under binary phase shift keying modulation in an additive white Gaussian noise channel.
A beautiful suit can fit into any occasion. Especially, if the occasion demands an ethnic wear, you can either go for suits or sarees. Both can look equally elegant. Saree can at times be too cumbersome, and if it is not a very formal occasion, a suit is the best attire you can choose.
http://www.nallucollection.com/salwar/party-wear.html
Este documento resume las tres etapas de la adolescencia: la inicial de 10 a 14 años donde ocurren cambios físicos como el aumento de estatura y masa muscular; la media de 12 a 16 años donde continúan los cambios puberales y hay un enfoque en la apariencia; y la tardía de 16 a 19 años donde se alcanza la madurez física y se establece la identidad personal. Explica que la adolescencia conlleva cambios fisiológicos, psicológicos y sociológicos que influyen en el desarrollo
Performance analysis and implementation for nonbinary quasi cyclic ldpc decod...ijwmn
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with
significantly better performance. Although various kinds of low-complexity iterative decoding algorithms
have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high
complexity and long latency. In this brief, highly efficient check node processing scheme, which the
processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are
proposed. Compare with previous works, less than 52% could be reduced for the latency of check node
unit. In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NBQC-
LDPC decoder.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
Master's Degree Thesis on High Order Modulation and Coding Shemes for Satellite Transmitters
Advisors
Prof.dr. Roberto Garello
Eng.dr. Domenico Giancristofaro
The Reliability in Decoding of Turbo Codes for Wireless CommunicationsIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Turbo codes are a type of error correcting code that can achieve performance close to the theoretical maximum allowed by Shannon's limit. Turbo codes use an iterative decoding process between two recursive systematic convolutional encoders separated by an interleaver. This iterative decoding allows turbo codes to correct errors very efficiently. Turbo codes are used in applications like deep space communications and mobile phone networks due to their ability to operate reliably at low signal-to-noise ratios.
This document summarizes a research paper that proposes using genetic algorithms and differential evolution to optimize the interleaver design for turbo codes. Turbo codes achieve performance close to the theoretical limit by using parallel concatenation of recursive systematic convolutional codes. The interleaver permutes the input bits, which affects turbo code performance. This research aims to use evolutionary algorithms to find higher performing turbo code interleavers compared to conventional designs. It compares the proposed approaches to the traditional genetic algorithm method and finds that differential evolution performs well for optimizing turbo code interleaver design.
This document discusses using low density generator matrix (LDGM) codes for source coding and joint source-channel coding of correlated sources. Key points:
- LDGM codes can achieve near-Shannon limit performance for channel coding with lower complexity than LDPC codes. Serial and parallel concatenated LDGM codes are proposed.
- LDGM codes are applied to source coding of correlated sources modeled by a hidden Markov model. Simulation results show the codes achieve rates close to the theoretical limits.
- LDGM codes are also used for joint source-channel coding of correlated sources over independent noisy channels. Different decoding schedules are evaluated. Results show the codes perform well for both AWGN and Rayleigh fading channels.
Error correcting coding has become one essential part in nearly all the modern data transmission and
storage systems. Low density parity check (LDPC) codes are a class of linear block code has the superior
performance closer to the Shannon’s limit. In this paper two error correcting codes from the family of
LDPC codes specifically Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Nonbinary
low density parity check (NB-LDPC) codes are compared in terms of power consumption, number of
iterations and other parameters. For better performance of EG-LDPC codes, Maximum Likelihood (ML)
Algorithm was proposed. NB-LDPC codes can provide better error correcting performance with an
average of 10 to 30 iterations but has high decoding complexity which can be improve by EG-LDPC codes
with ML algorithm having only three iterations for detecting and correcting errors. One step majority logic
decodable (MLD) codes is a subclass of EG-LDPC codes are used to avoid high decoding complexity. The
power Consumed by NB-LDPC codes is 2.729W whereas the power consumed by EG-LDPC codes with ML
algorithm is 1.148W.
The document describes a new code consistency maintenance protocol called DHV for wireless sensor networks. DHV allows nodes to detect version differences and identify newer code versions using only necessary bit-level information, requiring far fewer messages and bits transmitted than previous protocols. Simulations and experiments show DHV reduces messages by 50%, converges faster, and reduces transmitted bits by 40-60% compared to the state-of-the-art DIP protocol.
This document discusses the design and implementation of low density parity check (LDPC) codes. It begins with an introduction to LDPC codes, including their representation using parity check matrices and Tanner graphs. It then describes encoding and decoding algorithms for LDPC codes, focusing on belief propagation and message passing algorithms for decoding. Specifically, it covers hard decision decoding, soft decision decoding, and how LDPC codes can detect and correct errors. The document also discusses the construction of LDPC codes, mentioning methods proposed by Gallager, McKay and Neal, and for repeat accumulation codes.
This document provides an overview of low-density parity-check (LDPC) codes. It discusses Shannon's coding theorem and the evolution of coding technology. LDPC codes were invented by Gallager in 1963 and have simple decoding algorithms that allow them to achieve performance close to the Shannon limit. The document defines regular and irregular LDPC codes using parity check matrices and Tanner graphs. It also discusses code construction, applications of LDPC codes in wireless communications standards, and concludes that LDPC codes are becoming the mainstream in coding technology.
This document discusses low-density parity-check (LDPC) codes. It begins with an overview of LDPC codes, noting they were originally invented in the 1960s but gained renewed interest after turbo codes. It then covers LDPC code performance and construction, including generator and parity check matrices. Various representations of LDPC codes are examined, such as matrix and graphical representations using Tanner graphs. Applications of LDPC codes include wireless, wired, and optical communications. In conclusions, turbo codes achieved theoretical limits with a small gap and led to new codes like LDPC codes, which provide high-speed and high-throughput performance close to the Shannon limit.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document discusses turbo codes, a type of forward error correction code. Turbo codes use parallel concatenated convolutional encoders with pseudorandom interleaving and iterative decoding. This structure allows turbo codes to achieve error correction performance very close to the theoretical limit defined by the Shannon capacity. Some key advantages of turbo codes are their remarkable power efficiency and ability to support delivery of multimedia services through design tradeoffs. However, turbo codes also have long latency and poor performance at very low bit error rates.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
The document presents a novel approach for forward error correction (FEC) decoding based on the belief propagation (BP) algorithm in LTE and WiMAX systems. Specifically, it proposes representing tail-biting convolutional codes and turbo codes using parity check matrices, which allows both code types to be decoded using a unified BP algorithm. This provides a lower complexity decoding architecture compared to traditional approaches. Simulation results show the BP algorithm achieves near-identical performance to maximum a posteriori (MAP) decoding for turbo codes, while being less complex. Representing codes with parity check matrices thus enables a universal decoder for LTE and WiMAX using a single BP algorithm.
The document discusses turbo codes, which are a type of error correction code used in communication systems. Turbo codes work by concatenating two or more simple convolutional codes with an interleaver between them. This structure allows for iterative decoding that can achieve performance close to the theoretical maximum. The key aspects covered are the turbo code concepts, log likelihood algebra used in decoding, the purpose and types of interleaving, and how recursive systematic convolutional codes are used as the component codes of a turbo code.
The document discusses turbo codes, which are a type of error correction code that can achieve low bit error rates close to the Shannon limit. Turbo codes work by encoding the data using two or more simple component codes on interleaved versions of the input and then iteratively decoding the outputs of the component decoders. This iterative decoding allows turbo codes to outperform conventional codes with lower complexity. The document provides background on channel coding, forward error correction, and convolutional codes before explaining how turbo codes are constructed and decoded.
This document summarizes forward error correction techniques using convolutional encoders and Viterbi decoders. It first provides background on communication channels and the need for error correction when transmitting data. It then describes convolutional coding, a technique that maps a continuous stream of input bits to a continuous stream of encoded output bits using shift registers, with the encoded bits depending on current and past input bits. The key aspects of convolutional encoders are discussed, including parameters like the number of output bits, input bits, and shift registers. Generator polynomials are also introduced as characterizing the encoder connections. Viterbi decoding is highlighted as a maximum likelihood algorithm for decoding the trellis structure of convolutional codes based on soft decisions.
Survey on Error Control Coding TechniquesIJTET Journal
This document discusses various error control coding techniques used to ensure correct data transmission over noisy channels. It describes automatic repeat request and forward error correction as the two main approaches. Specific coding schemes covered include parity codes, Hamming codes, BCH codes, Reed-Solomon codes, LDPC codes, convolutional codes, and turbo codes. Reed-Solomon codes can correct multiple burst errors with high code rates. LDPC codes provide performance close to the Shannon limit with lower complexity than turbo codes. The document provides an overview of the coding techniques and their encoding and decoding processes.
Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers IJECEIAES
This document presents a study on the performance of a low density parity check (LDPC) coded orthogonal frequency division multiplexing (OFDM) system using space time block coding (STBC) under various digital modulations and channel conditions. The system incorporates a 3/4 rate convolutional encoder and a LDPC encoder. At the receiver, maximum ratio combining is implemented for channel equalization. Simulation results show that the LDPC coded OFDM system outperforms an uncoded system, and provides lower bit error rates under binary phase shift keying modulation in an additive white Gaussian noise channel.
A beautiful suit can fit into any occasion. Especially, if the occasion demands an ethnic wear, you can either go for suits or sarees. Both can look equally elegant. Saree can at times be too cumbersome, and if it is not a very formal occasion, a suit is the best attire you can choose.
http://www.nallucollection.com/salwar/party-wear.html
Este documento resume las tres etapas de la adolescencia: la inicial de 10 a 14 años donde ocurren cambios físicos como el aumento de estatura y masa muscular; la media de 12 a 16 años donde continúan los cambios puberales y hay un enfoque en la apariencia; y la tardía de 16 a 19 años donde se alcanza la madurez física y se establece la identidad personal. Explica que la adolescencia conlleva cambios fisiológicos, psicológicos y sociológicos que influyen en el desarrollo
Presentacion consejos consultivos cuenta publica salud comunal 2013Myriam Rodríguez Melo
El documento presenta las directivas de los consejos consultivos de Cesfam Garín y la información de sus actividades. Lista los nombres y cargos de las directivas de ambos consejos consultivos y resume sus planes de trabajo, que incluyen la difusión de información sobre salud, la capacitación en temas legales y la validación de protocolos con los usuarios. También describe reuniones y asambleas realizadas con diversos grupos de la comunidad para diagnosticar problemas y necesidades de salud desde una perspectiva participativa.
The impact of innovation on travel and tourism industries (World Travel Marke...Brian Solis
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We’re all trying to find that idea or spark that will turn a good project into a great project. Creativity plays a huge role in the outcome of our work. Harnessing the power of collaboration and open source, we can make great strides towards excellence. Not just for designers, this talk can be applicable to many different roles – even development. In this talk, Seasoned Creative Director Sara Cannon is going to share some secrets about creative methodology, collaboration, and the strong role that open source can play in our work.
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1) The document discusses the opportunity for technology to improve organizational efficiency and transition economies into a "smart and clean world."
2) It argues that aggregate efficiency has stalled at around 22% for 30 years due to limitations of the Second Industrial Revolution, but that digitizing transport, energy, and communication through technologies like blockchain can help manage resources and increase efficiency.
3) Technologies like precision agriculture, cloud computing, robotics, and autonomous vehicles may allow for "dematerialization" and do more with fewer physical resources through effects like reduced waste and need for transportation/logistics infrastructure.
Space time block coding is a technique used in wireless communication to transmit multiple copies of a data stream across a number of antennas and to exploit the various received versions of the data to improve the reliability of data transfer. The fact that the transmitted signal must traverse a potentially difficult environment with scattering, reflection, refraction and so on and may then be further corrupted by thermal noise in the receiver means that some of the received copies of the data may be closer to the original signal than others. This redundancy results in a higher chance of being able to use one or more of the received copies to correctly decode the received signal. In fact, space–time coding combines all the copies of the received signal in an optimal way to extract as much information from each of them as possible.
This document summarizes a research paper that proposes using parallel concatenated turbo codes in wireless sensor networks in an adaptive way. The key points are:
1) Turbo codes can achieve near-Shannon limit performance but decoding is complex, making them difficult to implement on energy-constrained sensor nodes.
2) The proposed approach shifts the complex turbo decoding to the base station while sensor nodes implement encoding and basic error correction.
3) At sensor nodes, a parallel concatenated convolutional code (PCCC) circuit encodes data and detects/corrects errors in forwarded packets. This improves energy efficiency and reliability over the wireless sensor network.
PERFORMANCE OF ITERATIVE LDPC-BASED SPACE-TIME TRELLIS CODED MIMO-OFDM SYSTEM...ijcseit
This paper presents the bit error rate (BER) performance of the low density parity check (LDPC) based
space-time trellis coded 2×2 multiple-input multiple-output orthogonal frequency-division multiplexing
(STTC-MIMO-OFDM) system on text message transmission. The system under investigation incorporates
1/2-rated LDPC encoding scheme under various digital modulations (BPSK, QPSK and QAM) over an
additative white gaussian noise (AWGN) and other fading (Raleigh and Rician) channels for two transmit
and two receive antennas. At the receiving section of the simulated system, Minimum Mean-Square-Error
(MMSE) channel equalization technique has been implemented to extract transmitted symbols without
enhancing noise power level. The effectiveness of the proposed system is analyzed in terms of BER with
signal-to-noise ratio (SNR). It is observable from the Matlab based simulation study that the proposed
system outperforms with BPSK as compared to other digital modulation schemes at relatively low SNRs
under AWGN, Rayleigh and Rician fading channels. The transmitted text message is found to have
retrieved effectively at the receiver under implementation of iterative sum-product LDPC decoding
algorithm. It has also been anticipated that the performance of the LDPC-based STTC-MIMO-OFDM
system degrades with the increase of noise power.
A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEMVLSICS Design
Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model.
Simulation of Turbo Convolutional Codes for Deep Space MissionIJERA Editor
In satellite communication deep space mission are the most challenging mission, where system has to work at very low Eb/No. Concatenated codes are the ideal choice for such deep space mission. The paper describes simulation of Turbo codes in SIMULINK . The performance of Turbo code is depend upon various factor. In this paper ,we have consider impact of interleaver design in the performance of Turbo code. A details simulation is presented and compare the performance with different interleaver design .
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
In recent years, cooperative communication is a hot topic of research and it is a powerful physical layer
technique to combat fading in wireless relaying scenario. Concerning with the physical layer issues, in this
paper it is focussed on with providing a better space time block coding (STBC) scheme and incorporating it
in the cooperative relaying nodes to upgrade the system performance. Recently, the golden codes have
proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario
than any other code. However, a serious limitation associated with it is its increased decoding complexity.
This paper attempts to resolve this challenge through suitable modification of golden code such that a less
complex sphere decoder could be used without much compromising the error rates. The decoder complexity
is analyzed through simulation and it proves to exhibit less complexity compared to the conventional
(Maximum likelihood) ML decoder. The single relay cooperative STBC consisting of source, relay and
destination are considered. The cooperative protocol strategy considered in the relay node is Decode and
forward (DF) protocol. The proposed modified golden code with less complex sphere decoder is
implemented in the nodes of the cooperative relaying system to achieve better performance in the system.
The simulation results have validated the effectiveness of the proposed scheme by offering better BER
performance, minimum outage probability and increased spectral efficiency compared to the non
cooperative transmission method.
This document provides an overview of simulation of a turbo encoder and decoder. It discusses the key components of a turbo encoder including two convolutional encoders separated by an interleaver. It describes convolutional encoding, interleaving, puncturing, and different decoding techniques like SOVA and MAP decoding. It lists applications of turbo codes in areas like mobile radio, digital video, and deep space communications. Finally, it concludes that turbo codes can achieve remarkable performance with low complexity encoding and decoding algorithms, making them well-suited for applications like deep space communications.
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This document reviews high throughput polar encoders. It discusses how polar codes achieve channel capacity and are becoming popular error correcting codes. It then summarizes the methodology used in the paper, which proposes a pipelined FPGA architecture for polar code encoding to reduce hardware complexity for long codes. This involves a partially parallel approach compared to fully parallel architectures. The conclusions discuss providing this pipelined architecture to optimize hardware usage.
Performance Analysis of DRA Based OFDM Data Transmission With Respect to Nove...IJERA Editor
In this paper, we have analyzed the performance characteristics of OFDM data transmission with regard to a new high speed RS decoding algorithm. The various characteristics identified are mainly speed and accuracy of the transmission irrespective of channel behaviour. We consider two cases viz. data transmission without error control and data transmission with error control. Each of these cases are duly analyzed and it is proven that high speed RS decoding algorithms can actually benefit OFDM data transmission for advanced communication systems only if implemented at the hardware (VLSI) level because of significant processing overhead involved in software based implementation even though the algorithm may have lower computational complexity.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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This document discusses improving the bit error rate of OFDM transmission using turbo codes. It provides an overview of OFDM and its benefits, including its ability to combat multipath interference. However, OFDM results in burst errors that can degrade coding efficiency. The document proposes using turbo codes with OFDM since turbo codes can achieve performance close to the Shannon limit. It reviews the basic principles of turbo code design and encoding/decoding. The rest of the document outlines simulations done to test the performance of a turbo code combined with OFDM over AWGN and impulsive noise channels.
This document discusses the design of low-density parity-check (LDPC) codes that provide unequal error protection (UEP) when used with higher order constellations (HOCs) like 8-PSK and 64-QAM. The proposed method divides the variable node degree distribution into sub-distributions corresponding to protection classes from the source coding and modulation classes of the HOC. An iterative linear programming approach is used to optimize the sub-distributions to enhance the UEP capability of the code for different signal-to-noise ratios, while reducing the overall bit error rate by accounting for the different bit error probabilities of the HOC. Simulation results show significant bit error rate reductions compared to codes optimized for binary phase-shift keying
Performance analysis of al fec raptor code over 3 gpp embms networkeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Performance analysis of al fec raptor code over 3 gpp embms networkeSAT Journals
Abstract Long Term Evolution (LTE) is the current standard for mobile networks based on Third Generation Partnership Project. LTE includes enhanced multimedia broadcast and multicast services (MBMS), also called as Evolved multimedia broadcast and multicast services (eMBMS) where the same content is transmitted to multiple users in one specific area. eMBMS is a new function defined in 3GPP Release 8 specification that supports the delivery of content and streaming to group users into LTE mobile networks. In LTE an important point of demanding multimedia services is to improve the robustness against packet losses. In this direction, in order to support effective point-to-multipoint download and streaming delivery, 3GPP has included an Application Layer Forward Error Correction (AL-FEC) scheme in the standard eMBMS. The standard AL-FEC system is based on systematic, fountain Raptor codes. Raptor coding is very useful in case of packet loss during transmission as it recover all data back from insufficient data at receiver terminal .In our work, in response to the emergence of an enhanced AL-FEC scheme, a raptor code has been implemented and performance is evaluated and the simulation results are obtained. Index Terms: long term evolution; multimedia broadcast multicast services; forward error correction; raptor codes
New Structure of Channel Coding: Serial Concatenation of Polar Codesijwmn
This document summarizes a research paper that proposes a new channel coding structure using serial concatenation of polar codes. The proposed method concatenates two polar codes in series with an interleaver in between to rearrange bits. This is done to improve the reliability and performance of polar codes at low error rates. Experimental results show that the proposed serial concatenation of polar codes achieves a lower bit error rate than standard polar codes alone for different block lengths and code rates.
New Structure of Channel Coding: Serial Concatenation of Polar Codesijwmn
In this paper, we introduce a new coding and decoding structure for enhancing the reliability and performance of polar codes, specifically at low error rates. We achieve this by concatenating two polar codes in series to create robust error-correcting codes. The primary objective here is to optimize the behavior of individual elementary codes within polar codes. In this structure, we incorporate interleaving, a technique that rearranges bits to maximize the separation between originally neighboring symbols. This rearrangement is instrumental in converting error clusters into distributed errors across the entire sequence. To evaluate their performance, we proposed to model a communication system with seven components: an information source, a channel encoder, a modulator, a channel, a demodulator, a channel decoder, and a destination. This work focuses on evaluating the bit error rate (BER) of codes for different block lengths and code rates. Next, we compare the bit error rate (BER) performance between our proposed method and polar codes.
New Structure of Channel Coding: Serial Concatenation of Polar Codesijwmn
In this paper, we introduce a new coding and decoding structure for enhancing the reliability and performance of polar codes, specifically at low error rates. We achieve this by concatenating two polar codes in series to create robust error-correcting codes. The primary objective here is to optimize the behavior of individual elementary codes within polar codes. In this structure, we incorporate interleaving, a technique that rearranges bits to maximize the separation between originally neighboring symbols. This rearrangement is instrumental in converting error clusters into distributed errors across the entire sequence. To evaluate their performance, we proposed to model a communication system with seven components: an information source, a channel encoder, a modulator, a channel, a demodulator, a channel decoder, and a destination. This work focuses on evaluating the bit error rate (BER) of codes for different block lengths and code rates. Next, we compare the bit error rate (BER) performance between our proposed method and polar codes.
This document describes a space-time block coding (STBC) orthogonal frequency-division multiplexing (OFDM) system for text message transmission over fading channels using multiple transmit antennas. It evaluates the bit error rate (BER) performance of the system using different digital modulation schemes (BPSK, QPSK, QAM-8) over additive white Gaussian noise (AWGN) channels and fading channels. Low-density parity-check (LDPC) coding is concatenated with convolutional coding in the system to improve error performance. Simulation results show that the system is effective in retrieving the transmitted text message under noise and fading conditions, and that BER performance degrades with increasing noise power as expected.
This document summarizes a research paper that proposes a space-time block coded (STBC) orthogonal frequency-division multiplexing (OFDM) system for text message transmission over fading channels using multiple transmit antennas. The system utilizes low-density parity-check channel coding concatenated with convolutional coding. Simulation results show that the proposed system achieves good error rate performance, especially when using BPSK modulation with 2x4 transmit antennas in AWGN, Rayleigh, and Rician fading channels. The system is effective in properly identifying and retrieving transmitted text messages in noisy and fading environments.
1. A.Durga Prakash, I.V.G.Manohar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1583-1591
A Design Of Low Density Parity Check Algorithm For
Insertion/Deletion Channels
A.DURGA PRAKASH I.V.G.MANOHAR
M.Tech Student Scholar, DECS, M.Tech, Asst Professor
Dept of Electronics and Communication Dept of Electronics and Communication
Engineering, Engineering,
Nalanda Institute of Engineering and technology, Nalanda Institute of Engineering and technology,
Sattenapalli (M); Guntur (Dt); A.P, India Sattenapalli (M); Guntur (Dt); A.P, India
Abstract
Low-density parity-check (LDPC) code is software patents has made LDPC attractive to some.
a linear error correcting code, a method of LDPC codes were forgotten until Gallager's work was
transmitting a message over a noisy transmission discovered in 1996. Turbo codes, another class of
channel, and is constructed using a sparse capacity approaching codes discovered in 1993,
bipartite graph. LDPC codes are capacity- became the coding scheme of choice in the late
approaching codes, LDPC codes are finding 1990s, used for applications such as deep space
increasing use in applications requiring reliable satellite communications.
and highly efficient information transfer over
bandwidth or return channel–constrained links in However, in the last few years, the advances
the presence of data-corrupting noise. In this in low-density parity-check codes have seen them
Paper we investigating a promising technique for surpass turbo codes in terms of error floor and
insertion, deletion and substitution errors. performance in the higher code rate range, leaving
Information exchange between the inner decoder turbo codes better suited for the lower code rates
and outer decoder is not allowed in iterative only. A memory less channel with synchronization
decoding. Through numerical evaluations, we first errors is defined as a channel in which each input
find the marker code structures which offer the symbol independently of other symbols is
ultimate achievable rate when standard bit-level transformed into a word of random (including also
synchronization are performed. The output results zero) length, and at the output of the channel the
which confirm the advantage of the newly ordinal number of the input symbol from which the
designed codes over the ones optimized for the given output symbol was obtained is unknown[2]. For
standard additive white Gaussian noise (AWGN) such channels Shannon’s theorem on transmission
channels, In AWGN channel severe rates for which noise stable coding methods exist, is
synchronization problems formulated and proved. The binary symmetric
channel, where each bit is independently received in
Keywords- Insertion/deletion channel, marker error with probability p, and the binary erasure
codes, synchronization, LDPC code design. channel, where each bit is erased with probability p,
enjoy a long and rich history. Shannon developed the
I. INTRODUCTION fundamental results on the capacity of such channels
Low-density parity-check (LDPC) codes are in the 1940’s, and in recent years, through the
a class of linear block LDPC codes. The name comes development and analysis of low-density parity-check
from the characteristic of their parity-check matrix codes and related families of codes, we understand
which contains only a few 1’s in comparison to the how to achieve near-capacity performance for such
amount of 0’s. Their main advantage is that they channels extremely efficiently[3].
provide a performance which is very close to the
capacity for a lot of different channels and linear time Before beginning, it is worth asking why this
complex algorithms for decoding. Furthermore are class of problems is important. From a strictly
they suited for implementations that make heavy use practical perspective, such channels are arguably
of parallelism. LDPC codes are finding increasing harder to justify than channels with errors or erasures.
use in applications requiring reliable and highly While codes for synchronization have been suggested
efficient information transfer over bandwidth or for disk drives, watermarking, or general channels
return channel–constrained links in the presence of where timing errors may occur, immediate
data-corrupting noise.[1]. Although implementation applications are much less clear than for advances in
of LDPC codes has lagged behind that of other codes, erasure-correcting and error-correcting codes.
notably turbo codes, the absence of encumbering However, this may be changing. In the past, symbol
synchronization has been handled separately from
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2. A.Durga Prakash, I.V.G.Manohar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1583-1591
coding, using timing recovery techniques that were bits 𝑇 is a constant system parameter while the
expensive but reasonable given overall system number of received bits 𝑅 is a random variable
performance [4]-[5]. Indeed, even the model we depending on the realization of the insertion/deletion
suggest assumes some high-level synchronization, as process. We can think of the channel as the cascade
both sender and receiver know that n bits are being of two sub-channels where, in the first sub-channel,
sent in a transmission; still, the model appears most each input bit gets deleted (with probability 𝑃 𝑑), or
natural and appropriate, and there is clear goal in experiences an insertion error (with probability 𝑃 𝑖), or
handling transmission sizes n efficiently and with a is correctly transmitted (with probability 𝑃 𝑡 = 1 − 𝑃 𝑑
high coding rate. − 𝑃 𝑖), while the second sub-channel is a BSC with
substitution probability 𝑃 𝑠.1 As proposed an input bit
With recent improvements in coding theory, experiencing an insertion error gets replaced by two
it may become increasingly common that uniformly distributed random bits, we point out that
synchronization errors will prove a bottleneck for different models for the insertion process exist. We
practical channels. Because we are currently so far assume that insertion, deletion, and substitution errors
away from having good coding schemes for even the are all IID, and that the transmitter and the receiver
most basic synchronization channels, in practice have no information on the positions at which the
coding is rarely if ever considered as a viable solution errors occur[16].
to synchronization. If efficient codes for
synchronization problems can be found, it is likely We adopt the coding scheme depicted in
that applications will follow. If such codes are even a Figure 1, which consists of the interleaved serial
fraction as useful as codes for erasures or errors have concatenation of an outer error-correcting code with
been, they will have a significant impact [6]-[9]. The an inner marker code. Specifically, the information
work we describe on capacity lower bounds bits are first encoded by means of a powerful channel
demonstrates that there is more potential here than code (e.g., a turbo or LDPC code), then the
has perhaps been realized. transmitted sequence is formed by inserting pilot bits,
which are often referred to as markers, to the
Of course, coding theory often has interleaved sequence of coded bits. The marker bits
applications outside of engineering, and channels and their positions in the transmitted sequence are
with deletions and insertions prove no exception, known to the receiver, which exploits this
appearing naturally in biology. Symbols from DNA information in the MAP detector to recover the
and RNA are deleted and inserted (and transposed, synchronization errors due to insertions/deletions, as
and otherwise changed) as errors in genetic processes. explained later. For simplicity, we only focus on the
Understanding deletion channels and related case of regular marker codes with rate[17].
problems may eventually give us important insight
into these genetic processes.
The paper is organized as follows. In the
next section, the system model is described. In
Section III, we review the standard bit-level MAP
detection algorithm and numerically evaluate the
ultimate rate achievable by interleaved concatenated
coding schemes. In Section IV, we introduce the
symbol-level MAP detection algorithm and compare
the relevant achievable rates with those characterizing
the standard bit-level approach. Error-rate results for
a practical LDPC coded scheme are also reported for Figure .1 Block diagram of the considered
both bit-level and symbol level detection[10]-[15]. concatenated coding scheme. Interleaving and
The EXIT chart-based LDPC code design process for deinterleaving blocks are denoted by Π and Π −1,
the insertion and deletion channels is provided in respectively.
Section V along with example designs. Finally,
concluding remarks are given in Section VI.
(1)
II. SYSTEM DESCRIPTION i.e., the case when the same marker
We consider transmission over binary consisting of 𝑁𝑀 consecutive bits is inserted every
channels impaired by insertion, deletion, and 𝑁 𝐶 bits at the output of the outer encoder. Hence, if
substitution errors, according to the model proposed . the outer code rate is denoted by 𝑟 𝐶, the overall code
rate is 𝑟 = 𝑟 𝐶 𝑟 𝑀. We notice that the same coding
Let = {𝑥𝑘}𝑇𝑘=1 and = {𝑦𝑛}𝑅 𝑛=1 be the
scheme was considered. while a similar scheme
sequences of bits at the channel input and channel
adopting watermark codes instead of marker codes
output, respectively, where the number of transmitted
was considered. At the receiver side, given the a
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3. A.Durga Prakash, I.V.G.Manohar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1583-1591
priori log-likelihood ratios (L-values) log (𝑥 𝑘=0)/ received, possibly after being corrupted by the
(𝑥 𝑘=1) , the MAP detection is first executed to channel or not. We are interested in the exact ―frame
generate the conditional probability 𝜉 𝑘(𝑥 𝑘) = 𝑃( |𝑥 𝑘) synchronization‖ scenario, in which 𝐷0,0 and 𝐷 𝑇, 𝑅 are
true with probability one, the values of 𝑇 and 𝑅 being
for 𝑘 {1, 2, . . ., 𝑇 } and 𝑥 𝑘 {0, 1} by exploiting known to the receiver. This assumption is not critical
the perfect a priori information from the marker code. since frame synchronization can be obtained with
Then the extrinsic information on the transmitted bits great accuracy. For a better illustration of the
can be easily obtained as log ( |𝑥 𝑘=0)/( |𝑥 𝑘=1) = resynchronization process, a two-dimensional grid is
log 𝜉 𝑘(0)/𝜉 𝑘(1). After being deinterleaved, the a created to represent the synchronization errors. As the
posteriori information, i.e., the sum of a priori and rows and columns on the grid correspond to the
extrinsic L-values, feeds the outer decoder, which transmitted and received bits 𝑥 𝑘, 𝑘 ∈ {1, . . . , 𝑇 } and
finally generates an estimate of the information bits. 𝑦 𝑛, 𝑛 ∈ {1, . . .,𝑅}, respectively. The solid line refers
We point out that decoding performance can be to a particular channel realization and the dotted line
improved by adopting iterative schemes based on the indicates the channel without any insertion or
exchange of extrinsic information between the MAP deletion errors. There are only three possible moves
detector and the outer decoder. But, since the MAP to reach a certain state. A diagonal move from the top
detector is typically the bottleneck of the receiver in left corner to the bottom right corner on the grid
terms of latency, we assume that the MAP detection indicates a successful transmission, i.e., no insertion
is executed only once in Sections III and IV. Iterative or deletion, but the bit may not be correctly received.
detection/decoding is considered in Section V where An insertion event is represented by a diagonal move
specific outer code designs are pursued9[18]. in two adjacent blocks and a vertical move denotes a
deletion event. Let us also define the function and the
III. BIT-LEVEL SYNCHRONIZATION coefficients[19].
Let us first review the bit-level MAP
detection algorithm for the considered channel model.
The algorithm, which already appeared with some
differences in the channel model, is similar to the
general forward backward algorithm (FBA), but it
cannot be derived by means of the standard approach
discussed because the channel model is not a finite- (2)
state Markov chain. According to the turbo principle,
the code constraints induced by the outer code are
(3)
neglected in the derivation of the algorithm, and the
bits are considered to be statistically independent,
namely the a priori probability 𝑃 ( Π) is factorized (4)
These coefficients can be computed by
as =1 𝑃(𝑥 𝑘), where 𝑃(𝑥 𝑘) is 1/2 if 𝑥 𝑘 is a code bit,
means of the following forward recursion (where the
while it is 0 (or 1) if 𝑥 𝑘 is a pilot bit.
differences with respect to are due to the adopted
channel model being different):
(5)
and the following backward recursion:
(6)
which are both initialized by exploiting the ―frame
synchronization‖ assumption. Finally, the target
conditional probability can be computed as
Figure 2: Synchronization represented by a path on a
two dimensional grid (7)
A. Bit Level MAP Detection:
Let us define the binary event 𝐷 𝑘, 𝑛, with 𝑘 ∈ {1, 2, . .
., 𝑇 }, and 𝑛 ∈ {0, 1, . . .,𝑅}, which denotes whether,
of the first 𝑘 transmitted bits, exactly 𝑛 bits are
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4. A.Durga Prakash, I.V.G.Manohar / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue4, July-August 2012, pp.1583-1591
B. Achievable Rates by a Specific Marker Code:
An interesting information-theoretic
problem that arises is the following: what is the
ultimate rate at which we can reliably transmit
information through the considered concatenated
coding scheme? An approximate solution to this
problem can be found where the authors investigate
the BCJR-once bound and characterize the capacity
of a BSC with a time-varying substitution probability
and conjecture that it provides an accurate
characterization of the information rate. Here, we
pursue a more precise solution to the problem. First,
we notice that the ultimate rate 𝑟𝐶 for the outer code
that can be achieved through the considered
concatenated coding system is given by the mutual
information between the independent and uniformly Figure. 3. Achievable rates for different deletion
distributed bits at the input of the interleave at the channels for the marker ―01‖ inserted every 𝑁𝑐 bits
transmitter side and the soft information at the output
of the deinterleaved at the receiver side (see Figure.
1). Because of the complicated MAP detector, this
mutual information cannot be computed in closed
form, but it can be easily evaluated through Monte
Carlo simulations with a large number of channel
realizations by obtaining the histogram of the
distribution of the extrinsic information (L-
values).[20]-[21]. The reason we choose histograms
instead of the Arnold-Loeliger algorithm is that the
latter only gives the no-interleaving mutual
information while our focus is mainly on interleaved
systems using a soft damper, as discussed in Section
IV. Interestingly, this numerical method is equivalent
to the evaluation of the EXIT chart for the MAP
detector, particularly of its left-most point . In fact,
the left-most point of a detection EXIT chart gives
the ultimate rate achievable by the outer code when it
is concatenated with the inner detector through an Figure 4. Achievable rates for different insertion and
interleave and iterative detection/decoding is not deletion channels for the marker ―01‖ inserted every
allowed. Hence, for a given marker code with rate 𝑟 𝑀, 𝑁𝑐 bits
we can evaluate the ultimate value of 𝑟 𝐶 by means of Some results obtained by means of the
this numerical method, and then compute the ultimate proposed information rate evaluation method of the
overall rate as 𝑟 = 𝑟 𝐶 𝑟 𝑀. We will exploit this result in previous subsection. Particularly, in Figure 3, it is
the next subsection to find optimal marker codes for shown how the overall rate varies, for different
channels with insertions and deletions. deletion channels (𝑃 𝑖 = 𝑃 𝑠 = 0), as a function of 𝑁 𝐶,
when the two bit marker ―01‖ is inserted every 𝑁 𝐶
C. Marker Code Optimization: information-carrying bits[22]. For each value of the
In this section, we study the problem of deletion probability 𝑃 𝑑, a clear maximum is obtained,
selecting a good marker code. We first notice that a which determines the marker code rate that is
lower marker code rate or smaller 𝑁𝐶 leads to better information-theoretically optimal. Not surprisingly,
synchronization capabilities since the positions of the as deletions become more frequent, the achievable
insertions and deletions can be located more rate decreases, so does the rate of the optimal marker
precisely; however, this is obtained with an increased code, since an effective synchronization process
overhead. This argument suggests that an optimal requires more pilot bits. As another example,
marker code rate 𝑟𝑀 exists for different marker codes compares the impacts of insertion, deletion and
used over an insertion/deletion channel. substitution errors on the achievable rates with the
constraint that 𝑃 𝑖 + 𝑃 𝑑 + 𝑃 𝑠 = 0.03. It is clear that for
this particular example, the deletion errors cause
more severe damage than the insertion errors to the
performance while the substitution errors degrade the
capacity much less than the synchronization errors.
Note that these achievable rates are only valid if a
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Vol. 2, Issue4, July-August 2012, pp.1583-1591
single synchronization stage is employed (single-pass IV. SYMBOL-LEVEL
decoding) and they are violated when an iterative SYNCHRONIZATION
decoding/synchronization scheme is adopted. We also One key observation is that, since
note that the gap to the existing Shannon capacity insertion/deletion channels have memory, the soft
lower bounds is also large. For instance, a lower information at the output of the MAP detector
bound for the capacity of an i.i.d. deletion channel corresponding to two bits with different time indices
with 𝑃𝑑 = 0.05 is 0.728 while the maximum rate is correlated. Hence, information is lost when such
found is less than 0.6. correlations are neglected, which is exactly what is
done in our concatenated system because of the
presence of the interleaver/deinterleave [26]. On the
other hand, interleaving is fundamental because it
allows us to split the decoding process into two serial
steps, namely the inner detection and the outer
decoding; the other option being joint
detection/decoding, which would be computationally
infeasible. In the following, we propose a solution
that allows us to recover part of the information loss
while preserving the interleaving process, hence also
its advantage of splitting the decoding process into an
inner detection and an outer decoding.
A. Symbol Level MAP Detection:
We introduce MAP detection at the symbol
level, defining a symbol as a group of 𝑚 consecutive
bits. Consequently, the 𝑇 transmitted bits are
partitioned into Ts symbols
The proposed approach can be used not only taking values on .
to find the optimal rate for a given marker code, but The last symbol, however, may consists of less than
also to compare different marker codes. As an 𝑚 bits, but we assume that 𝑇/𝑚 = Ts is an integer for
example, the marker code ―00‖ is clearly not a good simplicity. In this case, synchronization can be
choice compared to ―01‖ since there is no transition carried out by means of a symbol-level FBA which is
between the two bits and the receiver cannot obtained by extending the bit level derivation given to
determine as precisely whether an insertion or the symbol-level case. In the following, we provide
deletion error happens prior to the specific marker.
the details of the algorithm.
On the other hand, for ―01‖, there is a transition in the
marker sequence and a single deletion or insertion
can be easily identified. In Figure. 5, we compare Let us re-define the binary event with 𝑘
four regular marker codes obtained by inserting the
markers ―0‖, ―01‖, ―001‖, and ―010‖ every 𝑁𝐶 and which denotes whether, of the first
information bits, for the case of a 𝑘 transmitted symbols (i.e., 𝑘𝑚 bits), exactly 𝑛 bits
deletion/substitution channel with 𝑃 𝑑 = 𝑃 𝑠 = 10−2. are received or not, possibly after being corrupted by
The results, which are given in terms of the overall the channel. With this redefinition of the event the
rate 𝑟 as a function of the marker code rate 𝑟 𝑀, show definitions in (2) and (3) still hold. As in the bit-level
that for this particular channel the best choice of case, the coefficients can be computed by means of
marker code among the three candidates is to insert the forward/backward recursions. For simplicity, we
the pilot bits ―01‖ every 18 information bits, which give here the formulations for the case 𝑚 = 2, i.e.,
provides an overall rate of about 0.75. It is also not bits are grouped as one symbol, noting that
surprising to see that the marker ―001‖ outperforms the extension to the case of 𝑚 > 2 is straightforward.
―010‖ for higher marker code rates. This is attributed In this case, there are 9 possible ways to reach a
to the following: it is more likely that more than one certain state on the trellis, and the resulting recursions
bit get deleted between two adjacent markers and are given as shown in (7) and (8), respectively, and
hence the marker ―010‖ may not be able to detect are both initialized by exploiting again the exact
these synchronization errors while the marker ―001‖ ―frame synchronization‖ assumption. Finally, the
still can. We conclude this section by noting that for target extrinsic information can be computed as
all the studied scenarios, the guidelines for marker shown in (9).
code design that we obtain through our analysis are in
good agreement with the approximate analysis B. Achievable Rate Improvement with Symbol
proposed[23]. Level Synchronization:
As an example use of the proposed
algorithm compares the mutual information between
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Vol. 2, Issue4, July-August 2012, pp.1583-1591
the symbols at the input of the interleaver at the
transmitter side and the soft information at the output
of the deinterleaver at the receiver side, for the case
of one-bit symbols and two-bit symbols. Specifically,
it is shown how the overall achievable rate varies, for
an IID deletion channel (𝑃𝑖 = 𝑃𝑠 = 0, 𝑃𝑑 = 0.01), as a
function of, when the two-bit marker ―01‖ is
inserted every information-carrying bits. For
comparison, the mutual information computed in the
absence of interleaving, i.e., by evaluating the
expectations using Monte
Carlo techniques with a large number of channel
simulations, and obtaining Figure 6: Achievable rate improvement through
is also shown[25]- symbol level decoding for the marker ―01‖ inserted
[26]. every 𝑁𝑐 bits.
This curve quantifies the transmission rate
loss due to interleaving. Since the complexity of the
algorithm grows exponentially in the group size 𝑚
which makes it infeasible for large values of 𝑚, only
the achievable rate for the case of 2- bit interleaving
is shown. It is clear that adopting symbol-level
detection recovers a significant part of the
interleaving loss, particularly as the marker code rate
increases. For instance, by comparing the two
relevant maximum achievable rates, we can conclude
that symbol-level detection is about 5% better in
capacity for the given example. Although omitted
from this paper, other simulation results also show
(8) similar gains for different channels, e.g., the
insertion-only channel and insertion/deletion
channels.
C. Exploiting Correlation via Demapper/Detector:
In this section, we consider a practical
coding scheme with the aim of confirming the
performance gain predicted by our information-
theoretic analysis for the symbol-level detection over
the bit-level detection. Specifically, we adopt a binary
LDPC code of length 16383 and rate = 0.87
concatenated with a marker code with rate =
30/32, obtained by inserting the marker ―01‖ every 30
(9) LDPC-coded bits. Hence, r = 0.8156 is obtained for
the overall code rate. We compare the performance
obtained by feeding the LDPC decoder with the soft
information produced by the bit level detector and the
symbol-level detector (with 𝑚 = 2 and 𝑚 = 3). In the
bit-level detection case, the output of the detector
directly feeds the LDPC decoder, which performs 100
self iterations and then produces the estimate of the
information bits. In the symbol-level detection case,
the output of the detector cannot directly feed the
LDPC decoder, which is binary and cannot manage
symbol-level soft information. Hence, to convert the
symbol-level information to bit-level information, we
adopt the soft demapper module proposed.
Specifically, we use iterative soft demapping (see
[27] for detailed formulations): for every 10 self
(10) iterations of the LDPC decoder, we perform one
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Vol. 2, Issue4, July-August 2012, pp.1583-1591
iteration of the soft demapper, so that the total variable and check nodes may offer a better
number of 100 self iterations of the LDPC decoder is performance but the check-regular LDPCs already
preserved for a fair comparison with the bit-level give good results as reported in the previous
case. literature. Suppose 𝐼 is the total number of different
The resulting frame-error rate (FER) and bit- variable node degrees of the LDPC code denoted by
error rate (BER) curves are compared for the case of 𝑖 = 1, . . . , 𝐼. Let 𝑎 𝑖 to be the fraction of variable
a deletion only channel. For comparison, the ultimate nodes with degree . The goal of code design is to
deletion probability 𝑃𝑑 at which a scheme with the find the set of parameters {𝜆𝑖} that provides the best
considered marker code and an outer code with rate decoding performance where
= 0.87 can provide reliable communications is also
shown— these values are obtained by means of the
information-theoretic analysis described in the
previous sections. An interesting fact is that a BER (11)
lower than is obtained by means of MAP Because of the first constraint, we need I ≥ 3 to have
detection with 𝑚 = 3 at values of the deletion any flexibility in our code design
probability at which bit-level detection cannot
converge even in the presence of an information- A. EXIT Chart Based Analysis of the Decoding
theoretically optimal code. The improvement Performance:
provided by the symbol-level detection is evident: for Since the outer LDPC decoder can be
a given BER, using a MAP detector with 𝑚 = 2 partitioned into LDPC variable node detector (VND)
allows the receiver to work with a deletion and LDPC check node detector (CND), for multiple-
probability increased by about with respect to the pass decoding, the information exchange between the
bit-level one, and the MAP detector with 𝑚 = 3 inner MAP detector and outer LDPC decoder is
provides an even greater robustness to deletion errors. further illustrated in Figure. 7, where Block A
consists of two sub-blocks which are referred to as
V. EXIT CHART-BASED OUTER LDPC FBA SISO and LDPC VND. Mutual information
CODE DESIGN FOR between the LDPC-coded bits and the corresponding
INSERTION/DELETION CHANNELS L-values, {𝐼𝐴, 𝐼𝐵, 𝐼𝑆, } [0, 1], are exchanged
In the previous sections, with the interest of between these blocks during the iterative decoding
reducing decoding latency, we focused on the case of process. It is worth mentioning that only the extrinsic
single-pass decoding for the outer code concatenated information, i.e., the difference between the a
with the inner marker code over insertion/deletion posteriori and the a priori L-values, is exchanged.
channels. We now consider an iterative scheme where
extrinsic information is exchanged between the MAP As stated in Section III, in the sub-block
detector (synchronization) block and the outer FBA SISO, MAP detection is applied on the received
decoder. This is motivated by the observation that sequence {𝑦 𝑘} with soft input a priori information
when iterative decoding is allowed, specifically given by 𝐼𝑉 and extrinsic L-values of the transmitted
designed LDPC codes for insertion and deletion bits are generated. measures the reliability of these
channels may provide performance gains over L-values. It is difficult to describe the relationship
between and in closed form, instead, Monte
Carlo simulations are performed to generate the so
called detection EXIT chart. A detection EXIT chart
example for insertion and deletion channels is shown
in Figure. 9 using bit level synchronization and the
marker code ―01‖. Marker code rates are chosen
based on the scheme proposed in Section III-C. The
variable nodes take as the a priori information and
perform the standard sum-product algorithm (SPA)
Figure. 7 Detailed decoder/detector block diagram at with information received from the LDPC CND. The
the receiver side. EXIT curve of the combined FBA SISO and LDPC
VND is described by the relationship between IA
In this section, we consider an LDPC code and IB given by where the function 𝐽(𝜎) is defined as
consisting of 𝑁 variable nodes and 𝑁 − 𝐾 check
nodes connected by an edge interleaver with rate =
𝐾/𝑁. For simplicity, only check regular LDPC codes (12)
are considered, i.e., every parity-check equation
involves a constant number of variable nodes,
denoted by We emphasize that joint design of
(13)
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Vol. 2, Issue4, July-August 2012, pp.1583-1591
In this case, can be numerically evaluated
degree to be 3. Listed LDPC code
from the detection EXIT chart using a polynomial
degree distributions guarantee convergence with the
approximation with input . For highest code rate for different deletion/insertion
instance, when 𝑃𝑖 =𝑃𝑑 = 0.01, we can write rates. Therefore, the overall code rate 𝑟, product of
and denotes the highest achievable rate when
iterative decoding is performed. For deletion
(1 probabilities of 0.01 and 0.1, the overall rates are
4) obtained as 0.860 and 0.486, respectively, where the
For a certain variable node degree distribution, the capacity lower bound is 0.919 for = 0.01 and
effective VND transfer curve is thus
0.531 for = 0.1. The corresponding gaps are
0.059 and 0.045 bits/channel use for the two cases,
which are clearly smaller than the one demonstrated
in Section III-C. We also expect that the gap to the
capacity bound can be further narrowed by allowing
(15)
At the CND, ―box plus‖ operation is 𝐼 > 3 and not fixing to be 3.
performed to generate IA from IB which can be The length of the LDPC codeword is set to
approximately written (it is useful to express it as the be 𝑁 = 5000 and the selected marker code rate is
inverse function). determined to maximize the transmission rate. we
calculate the ratio of the BERs of the two codes
(optimized one versus the AWGN-only code) when
the codes optimized for insertion and deletion
channels attain a BER. The higher the ratio, the
greater the improvement. Clearly, all of the codes
outperform the ones designed for AWGN channels.
However, the gap becomes less obvious as the
insertion/deletion rate decreases. This is not a
surprising result because for low insertion/deletion
probabilities, the detection EXIT charts tend to be flat
as illustrated. This is similar to the one for a memory
less AWGN channel[28]. In this case, specific design
Figure . 8 Detection EXIT chart for several insertion of an LDPC code for insertion/deletion channel may
and deletion channels for the marker ―01‖ inserted not be required since the gain is negligible. Similar
every 𝑁𝑐 bits. conclusions are drawn for ISI channels with short
channel impulse responses. Also, when the symbol-
level detection is performed, the left-most point in the
detection EXIT chart is much better than the bit-level
case as explained in Section IV-B. The rightmost
point in the detection EXIT chart is identical for both
cases since MAP detector achieves ideal
synchronization in this case. Therefore, the detection
EXIT chart for symbol level detection is flatter than
the one for the bit-level case. This observation
suggests that for channels with low insertion/deletion
rates, it is more likely that symbol-level detection
itself already yields a good performance and iterative
Figure. 9 Detection EXIT chart for several insertion decoding and LDPC code design may not be needed,
and deletion channels for AWGN the marker ―01‖ which is also an obvious fact, since when 𝑚 = 𝑇 ,
inserted every 𝑁𝑐 bits optimal detection (i.e., for synchronization purposes)
is achieved and there is no gain with iterative
B. LDPC Code Design Example for decoding/demapping. Clearly, this is not feasible in
Insertion/Deletion Channels: practice since the detection complexity in 𝑚 is
Design examples are using the bit level exponential and 𝑇 is typically large.
synchronization algorithm for several
insertion/deletion channels, deletion only channels VI. CONCLUSION
and insertion-only channels, respectively. We We have studied performance of an outer
choose 𝐼 = 3 and fix the average variable node LDPC code concatenated with an inner marker code
for data transmission over insertion/deletion channels.
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Vol. 2, Issue4, July-August 2012, pp.1583-1591
Two decoding strategies are considered: single-pass [11] S. E. Tavares and M. Fukada, ―Matrix
decoding and multi-pass decoding with information approach to synchronization recovery for
exchange between the inner detector and the outer binary cyclic codes.‖
decoder. For the first case, through numerical mutual [12] G. Seguin, ―On synchronizable binary cyclic
information analyses, we have developed a technique codes.‖
that allows us to optimize the marker code based on [13] L. Cheng and H. Ferreira, ―Rate-compatible
the ultimate rate achievable by the concatenated path-pruned convolutional codes and their
scheme. Moreover, we have presented a new symbol- applications on channels with insertion,
level detection algorithm, which has been proved to deletion and substitution errors.‖
outperform the standard bit-level one in terms of [14] T. G. Swart and H. C. Ferreira,
achievable rates. An iterative detector/demapper is ―Insertion/deletion correcting coding
also designed which is able to exploit the results of schemes based on convolution coding.‖
the symbol level synchronizer. Finally, when iterative [15] M. F. Mansour and A. H. Tewfik,
decoding is allowed, we have shown that by choosing ―Convolutional codes for channels with
good variable and check node degree distributions, substitutions, insertions, and deletions.‖
LDPC codes designed for insertion/deletion channels [16] V. I. Levenshtein, ―Binary codes capable of
offer better error correcting capabilities than those correcting deletions, insertions and
optimal for the AWGN-only channels. Simulation reversals.‖
results related to practical LDPC codes showing clear [17] H. C. Ferreira, T. G. Swart, and M. P. dos
performance gains have been provided for both cases Santos, ―Using parallelinterconnected
under consideration. Although we only focus on the Viterbi decoders to correct insertion/deletion
marker codes (as the inner synchronization code), errors.‖
similar analyses and design procedure can also be [18] L. Schulman and D. Zuckerman,
applied to other concatenated coding schemes, e.g., ―Asymptotically good codes correcting
an LDPC code concatenated with an inner watermark insertions, deletions, and transpositions.‖
code. [19] M. C. Davey and D. J. Mackay, ―Reliable
communication over channels with
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