SlideShare a Scribd company logo
White Paper 
Intel® IXP23XX Product Line of 
Network Processors 
Performance of the Intel® IXP23XX 
Product Line of Network Processors for 
Access and Edge Network Applications 
www.intel.com/go/ 
networkprocessors
Contents 
Introduction ............................................................................................................................................................................ 2 
Product line overview ....................................................................................................................................................... 2 
Performance metrics ............................................................................................................................................................... 3 
Performance assessment of the Intel® IXP2350 network processor ........................................................................................ 3 
ATM RAN application example ......................................................................................................................................... 4 
Additional application examples ...................................................................................................................................... 5 
Conclusion .............................................................................................................................................................................. 5 
Introduction 
Manufacturers of access and edge equipment have long 
sought the ideal balance of performance and programming 
flexibility in a processing platform. The fact is, applications 
such as ATM-based Radio Access Networks, DSL Access 
Multiplexers (DSLAMs), Wireless Local Area Network (WLAN) 
access points, WAN multi-service switches, and others, must 
support a range of protocols and line rates to meet application 
requirements. Standards-based interfaces and reusable code 
can help ensure reliable performance as well as accelerate 
time-to-market and leverage software assets across multiple 
solutions. And for equipment manufacturers to maximize 
profitability they must choose the right network processor— 
one that is neither over-powered nor under-powered, yet offers 
plenty of headroom in which to innovate. 
Intel offers an ideal solution with the Intel® IXP23XX product 
line of network processors, designed to enable a broad range 
of access and edge applications. Built on the same hardware 
and software architecture as the entire Intel® IXP2XXX product 
line, the IXP23XX network processors support deep packet 
inspection, traffic management, and forwarding at up to 2 
Gbps line rates in a single chip, while providing the headroom 
developers need to deliver value-added network services. 
Product line overview 
The IXP23XX product line includes the Intel® IXP2325 
network processor, which supports up to 2.5 giga-operations 
per second with two 32-bit independent multi-threaded 
microengines, and the Intel® IXP2350 network processor, 
which supports up to 4.9 giga-operations per second with four 
32-bit independent multi-threaded microengines. Variants of 
2 
each network processor are available with Intel XScale® core 
operating frequencies ranging from 600 MHz to 1200 MHz, 
and fast path microengine operating frequencies ranging 
from 300 MHz to 900 MHz. Both network processors are 
fully programmable, yet have the processing power to run 
applications that previously required expensive, high-speed 
ASICs and external control plane processors. 
As with all network processors in the entire Intel IXP2XXX 
product line, the IXP23XX network processors execute data 
plane tasks in parallel across individual microengines. The 
Intel® Internet Exchange Architecture (Intel® IXA) Software 
Framework complements the IXP2XXX modular hardware 
architecture by providing tested software building blocks, called 
microblocks, that developers can use to quickly assemble 
functional sequences, or pipelines, that perform specific 
network functions. These microblocks are highly reusable 
across applications; for example, an IP forwarding microblock 
could be used in a DSLAM application with an ATM media 
interface, as well as in a WAN multi-service switch. 
In this white paper, Intel presents a performance assessment of 
the Intel IXP2350 network processor for a variety of common 
access and edge applications. In the application examples 
discussed, packets are processed in microblocks and 
executed across the microengines within the IXP2350 network 
processor, processing a comprehensive set of functions 
for a variety of data rates and communications protocols. 
As the performance assessment will show, the IXP2350 
network processor offers robust performance with substantial 
headroom even under the most demanding conditions.
Performance metrics and IP 
forwarding example 
When examining the performance capabilities of a network 
processor, it is important to first consider the performance 
metrics used. Two of the primary performance metrics used in 
the communications and networking industry are packet rate 
and data rate (see Table 1). 
In network processors, the unit of work is a packet and, 
therefore, packet size is a critical parameter in characterizing 
performance. For example, smaller packets will require a 
greater number of packets per second to be processed at 
a given data rate. Since a certain amount of overhead is 
associated with each packet (e.g., table lookups, header 
updates, enqueues/dequeues), a greater number of smaller 
packets being processed per second will mean more work 
for the network processor and, consequently, less headroom 
available for value-added features. Conversely, with a fewer 
number of larger packets at the same data rate, the network 
processor can complete the same task with less work, thereby 
retaining greater headroom to support value-added features. 
A simple application such as IP forwarding for Ethernet 
packets illustrates this point. An IP forwarding application can 
be implemented in three stages: packet receive, IP forwarding 
based on longest prefix match and packet transmit. Table 
2 presents estimated performance and packet processing 
headroom for the Intel® IXP2350 network processor in 
this application. 
Communications protocols, such as Gigabit Ethernet and 
OC-12, each support different minimum-sized packets 
3 
and carry different levels of overhead. Therefore, for any 
given data rate, performance—measured in ‘million packets 
per second’—will ultimately be a factor of packet size and 
overhead. With maximum data rates of 3.6 Gbps in the 
IPv4 forwarding example in Table 2, it is evident that the 
percentage of headroom in the IXP2350 network processor 
increases as the packet size grows. 
Performance assessment of the 
Intel® IXP2350 network processor 
In assessing the performance of the IXP2350 network 
processor, Intel chose to use minimum packet sizes in all 
application examples. By taking this approach, the IXP2350 
network processor is subjected to the most demanding 
conditions likely to be encountered in the real world. Even in 
these “worst case” scenarios, the IXP2350 network processor 
demonstrates robust performance with ample headroom in 
which equipment vendors can add value. 
To determine performance capabilities for the IXP2350 
network processor, Intel calculated the headroom available 
with all four microengines processing minimum-sized packets 
with a robust set of application functions at a given data 
rate. These calculations are based on data from an Intel 
IXP23XX cycle and data accurate simulator and on previously 
measured data for the Intel® IXP2400 network processor 
extrapolated to match the specifications of the IXP2350 
network processor. 
Ethernet Packet Size Intel® IXP2350 Network Processor 
• Intel XScale® core – 900 MHz 
• Microengines (ME) – 900 MHz 
64 B 25% ME headroom (5.35 Mpps**) 
128 B 58% ME headroom (3.04 Mpps**) 
512 B 75% ME headroom (0.85 Mpps**) 
1518 B 78% ME headroom (0.30 Mpps**) 
Table 2: IPv4 Forwarding over Ethernet Performance 
** Based on maximum bus frequency and associated data rate of 3.6 Gbps 
on the media interface. 
Data rate is the total number of Megabits-per-second (Mbps) that a network-ing 
element can handle. Packet rate is the number of million-packets-per-sec 
(Mpps) that the networking element can handle. The relation between the 
data rate and packet rate is simple: 
Data rate (Mbps) 
Packet rate (Mpps) = ----------------------- 
8x Packet size (bytes) 
Table 1: Packet Rates vs. Data Rates
ATM RAN application example 
The ATM RAN application is intended for transport line cards 
in the 3 GPP UTRAN network. In this application, the Intel® 
IXP2350 network processor is tasked with processing packets 
from the line interface to the backplane and out a second line 
interface. Figures 1 and 2 illustrate the full set of functions 
In this performance assessment, two configurations of the 
line interface are analyzed: 2xOC-3, which is best suited for 
the Iub interface of the RNC, and 16 T1/E1, which is best 
suited for the Iub interface of Node B. In both configurations, 
4 
/!-#ELL 
TO)NTEL83CALEš 
performed by the microengines within the IXP2350 network 
processor for the ATM RAN application. 
%NCAPSULATION 
!!, 
3$5 
!!,33#32X 
0ROCESSING 
)05$0 
%N1UEUE 
!4- 0ACKET 
#ELL 
!4- 
#ELL 
/!- 
0ROCESSING 
!4-54/0)!	 
0HYSICALIF	 
28FROM-3 
!4-2X 
!UTOPUSH 
FROM-3 
!4- 
#ELLS 
!4-
4# 
SWON.0%	 
!!,#03 
2X 
#03 
0ACKETS 
0ROCESSING 
!!,2X 
0ROCESSING 
0RIORITY 
3CHEDULER 
4XTO-3 
,%NCAP	 
'IG%THERNET4X 
!!, 
3$5 
)0V 
4RANSMIT 
7RITETO 
-3 
Figure 1: Data flow from the line interface to backplane. These software blocks are implemented on the microengines of the IXP2350 network processor. 
2XFROM-3 
'IG%THERNET2X 
!UTOPUSH 
FROM-3 
)05$0 
$ECAPSULATION 
!!,33#3 
4X 
0ROCESSING 
!!,4X 
0ROCESSING 
4- 
7RITEOUT 
4- 
3CHEDULER 
$E1UEUE 
#03 
0ACKETS 
!!, 
3$5 
)0V 
0ACKET 
!!, 
3$5 
!4-#ELL 
%N1UEUE 
!!,#034X 
0ROCESSING 
4- 
3HAPER 1- 
LOW#ONTROL 
4XTO-3 
!4-4X 
!4-
4# 
SWON.0%	 
7RITETO 
!4- -3 
#ELLS 
!4-54/0)!	 
0HYSICALIF	 
/!- 
0ROCESSING 
Figure 2: Data flow from the backplane to the line interface. These software blocks are implemented on the microengines of the IXP2350 network processor.
performance is quoted under “worst-case,” minimum-sized 
packet conditions. Additional specifications include: 
• 100% AAL2 traffic 
• One AAL2 cell embedded with two 20 B CPS packets 
• One 20 B CPS packet is mapped to an Ethernet packet 
on the backplane 
Under these conditions, the Intel® IXP2350 network processor 
provided performance results as shown in Table 3. 
Even when subjected to the most rigorous performance 
conditions in this ATM RAN application example, the IXP2350 
network processor delivers ample headroom to perform 
additional packet classification, Quality of Service algorithms, 
or other value-added functions. 
Additional application examples 
In addition to ATM RAN, Intel has assessed the performance 
capabilities of the IXP2350 network processor for several 
other common access and edge applications, including 
• IP RAN 
• ATM+IP RAN 
• Wi-Fi Aggregator/L2 Switches 
• IP Routers 
• DSLAM 
• Metro/Edge RPR 
• Wi-Fi to Ethernet Bridge 
In each case, running a comprehensive range of application 
functions using minimum-sized packets, the IXP2350 network 
processor delivered line rate performance at up to 2 Gbps 
with sufficient headroom to support additional application 
services.1 With each packet undergoing multiple individual 
processes on the microengines, these results illustrate that 
the IXP2350 network processor has the processing power 
needed to support a broad range of access and edge 
network applications. 
Conclusion 
The Intel® IXP23XX product line of network processors offers 
network equipment manufacturers a powerful mid-range 
platform that extends the fully programmable Intel® IXA 
architecture to new, lower cost/performance points for access 
and edge applications, including broadband access devices, 
wireless infrastructure systems, routers and multi-service 
switches. Robust processing performance for demanding, 
minimum-size packet applications means that customers 
can use these network processors with confidence to deliver 
value-added network services.2 Because the IXP23XX 
product line integrates key architectural features from the 
Intel® IXP2XXX product line, developers can take advantage 
of seamless performance scalability and software reuse from 
T1/E1 to OC-192/10 Gbps line rates. 
Line Interface 
Configuration 
Intel® IXP2350 
Network Processor Variant 
Microengine 
Headroom 
2xOC-3 900 MHz Intel® XScale core 
900 MHz Microengines 
28% 
16 T1/E1 600 MHz Intel XScale core 
300 MHz Microengines 
56% 
Table 3: Performance results for the ATM RAN application 
5 
1 Actual results will vary depending on how individual vendor applications are written. 
2 Performance comparisons should be based on minimum-sized packets.
This page intentionally left blank
Intel® Internet Exchange Architecture (Intel® IXA) 
Intel® IXA is a packet processing architecture that provides a foundation for software portability across multiple generations of network 
processors. Intel IXA is based on programmable microengines, Intel XScale® technology and the Intel IXA Software Framework. Additional 
information on Intel IXA and the Intel network processor product lines is available at the addresses listed below. 
Intel Access 
Intel® Network Processors Web page www.intel.com/go/networkprocessors 
Intel® Communications Alliance www.intel.com/go/ica 
Intel in Communications http://intel.com/communications 
Other Intel Support: 
Intel® Technical Document Center http://intel.com/go/techdoc 
(800) 548-4725 7 a.m. to 7 p.m. CST (U.S. and Canada) 
International locations please contact your local sales office. 
General Information Hotline (800) 628-8686 or (916) 356-3104 5 a.m. to 5 p.m. PST 
For more information, visit the Intel web site at: developer.intel.com 
UNITED STATES AND CANADA 
EUROPE 
ASIA-PACIFIC 
Intel Corporation 
Intel Corporation (UK) Ltd. 
Intel Semiconductor Ltd. 
Robert Noyce Bldg. 
Pipers Way 
32/F Two Pacific Place 
2200 Mission College Blvd. 
Swindon 
88 Queensway, Central 
P.O. Box 58119 
Wiltshire SN3 1RJ 
Hong Kong, SAR 
Santa Clara, CA 95052-8119 
UK 
USA 
JAPAN 
Intel Japan (Tsukuba HQ) 
5-6 
Tokodai Tsukuba-shi 
300-2635 Ibaraki-ken 
Japan 
SOUTH AMERICA 
Intel Semiconductores do Brasil LTDA 
Av. Dr. Chucri Zaidan, 940-10o andar 
04583-904 São Paulo, SP 
Brazil 
Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those 
tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the 
performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, 
visit http://www.intel.com/performance/resources/limits.htm 
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR 
SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF 
INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, 
COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel may make changes to specifications, product descriptions, and plans at any time, without notice. 
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The 
furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, 
or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. 
The Intel® IXP23XX Product Line of Network Processors may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. 
Current characterized errata are available upon request. 
Intel, the Intel logo and Intel XScale are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. 
*Other names and brands may be claimed as the property of others. 
Copyright © 2004 Intel Corporation. All rights reserved. 1004/QUA/CM/PDF Please Recycle 304114-001US

More Related Content

What's hot

Review on Transmission and Reception of Data through USB in VHDL
Review on Transmission and Reception of Data through USB in VHDLReview on Transmission and Reception of Data through USB in VHDL
Review on Transmission and Reception of Data through USB in VHDL
IRJET Journal
 
Lightweight hamming product code based multiple bit error correction coding s...
Lightweight hamming product code based multiple bit error correction coding s...Lightweight hamming product code based multiple bit error correction coding s...
Lightweight hamming product code based multiple bit error correction coding s...
journalBEEI
 
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr AlgorithmAn Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
IJERA Editor
 
Dl34689693
Dl34689693Dl34689693
Dl34689693
IJERA Editor
 
Ad4103173176
Ad4103173176Ad4103173176
Ad4103173176
IJERA Editor
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)
Ashwin Shroff
 
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic MultiplierVHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
IRJET Journal
 
VLSI GDI Technology
VLSI GDI TechnologyVLSI GDI Technology
VLSI GDI Technology
Techno Electronics
 
Hyper Transport Technology
Hyper Transport TechnologyHyper Transport Technology
Hyper Transport Technology
nayakslideshare
 
Fpga based low power and high performance address generator for wimax deinter...
Fpga based low power and high performance address generator for wimax deinter...Fpga based low power and high performance address generator for wimax deinter...
Fpga based low power and high performance address generator for wimax deinter...
eSAT Journals
 
Fpga based low power and high performance address
Fpga based low power and high performance addressFpga based low power and high performance address
Fpga based low power and high performance address
eSAT Publishing House
 
Transmission and reception of data through usb using
Transmission and reception of data through usb usingTransmission and reception of data through usb using
Transmission and reception of data through usb using
eSAT Publishing House
 
Ethernet base divice control
Ethernet base divice controlEthernet base divice control
Ethernet base divice control
Bhushan Deore
 
Reconfigurable and versatile bil rc architecture
Reconfigurable and versatile bil rc architectureReconfigurable and versatile bil rc architecture
Reconfigurable and versatile bil rc architecture
eSAT Publishing House
 
A010240110
A010240110A010240110
A010240110
IOSR Journals
 
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
TRACK B: Multicores & Network On Chip Architectures/ Oren HollanderTRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
chiportal
 
Reconfigurable and versatile bil rc architecture design with an area and powe...
Reconfigurable and versatile bil rc architecture design with an area and powe...Reconfigurable and versatile bil rc architecture design with an area and powe...
Reconfigurable and versatile bil rc architecture design with an area and powe...
eSAT Publishing House
 
Ix3416271631
Ix3416271631Ix3416271631
Ix3416271631
IJERA Editor
 
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET -  	  Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...IRJET -  	  Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET Journal
 
Reducing the Number Of Transistors In Carry Select Adder
Reducing the Number Of Transistors In Carry Select AdderReducing the Number Of Transistors In Carry Select Adder
Reducing the Number Of Transistors In Carry Select Adder
paperpublications3
 

What's hot (20)

Review on Transmission and Reception of Data through USB in VHDL
Review on Transmission and Reception of Data through USB in VHDLReview on Transmission and Reception of Data through USB in VHDL
Review on Transmission and Reception of Data through USB in VHDL
 
Lightweight hamming product code based multiple bit error correction coding s...
Lightweight hamming product code based multiple bit error correction coding s...Lightweight hamming product code based multiple bit error correction coding s...
Lightweight hamming product code based multiple bit error correction coding s...
 
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr AlgorithmAn Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
 
Dl34689693
Dl34689693Dl34689693
Dl34689693
 
Ad4103173176
Ad4103173176Ad4103173176
Ad4103173176
 
Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)Gate Diffusion Input Technology (Very Large Scale Integration)
Gate Diffusion Input Technology (Very Large Scale Integration)
 
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic MultiplierVHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
VHDL Implementation of High Speed and Low Power BIST Based Vedic Multiplier
 
VLSI GDI Technology
VLSI GDI TechnologyVLSI GDI Technology
VLSI GDI Technology
 
Hyper Transport Technology
Hyper Transport TechnologyHyper Transport Technology
Hyper Transport Technology
 
Fpga based low power and high performance address generator for wimax deinter...
Fpga based low power and high performance address generator for wimax deinter...Fpga based low power and high performance address generator for wimax deinter...
Fpga based low power and high performance address generator for wimax deinter...
 
Fpga based low power and high performance address
Fpga based low power and high performance addressFpga based low power and high performance address
Fpga based low power and high performance address
 
Transmission and reception of data through usb using
Transmission and reception of data through usb usingTransmission and reception of data through usb using
Transmission and reception of data through usb using
 
Ethernet base divice control
Ethernet base divice controlEthernet base divice control
Ethernet base divice control
 
Reconfigurable and versatile bil rc architecture
Reconfigurable and versatile bil rc architectureReconfigurable and versatile bil rc architecture
Reconfigurable and versatile bil rc architecture
 
A010240110
A010240110A010240110
A010240110
 
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
TRACK B: Multicores & Network On Chip Architectures/ Oren HollanderTRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
TRACK B: Multicores & Network On Chip Architectures/ Oren Hollander
 
Reconfigurable and versatile bil rc architecture design with an area and powe...
Reconfigurable and versatile bil rc architecture design with an area and powe...Reconfigurable and versatile bil rc architecture design with an area and powe...
Reconfigurable and versatile bil rc architecture design with an area and powe...
 
Ix3416271631
Ix3416271631Ix3416271631
Ix3416271631
 
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET -  	  Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...IRJET -  	  Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...
 
Reducing the Number Of Transistors In Carry Select Adder
Reducing the Number Of Transistors In Carry Select AdderReducing the Number Of Transistors In Carry Select Adder
Reducing the Number Of Transistors In Carry Select Adder
 

Similar to IXP 23XX Network processor

Conference Paper: Universal Node: Towards a high-performance NFV environment
Conference Paper: Universal Node: Towards a high-performance NFV environmentConference Paper: Universal Node: Towards a high-performance NFV environment
Conference Paper: Universal Node: Towards a high-performance NFV environment
Ericsson
 
Communication Performance Over A Gigabit Ethernet Network
Communication Performance Over A Gigabit Ethernet NetworkCommunication Performance Over A Gigabit Ethernet Network
Communication Performance Over A Gigabit Ethernet Network
IJERA Editor
 
BivioPerformanceWP0605
BivioPerformanceWP0605BivioPerformanceWP0605
BivioPerformanceWP0605
Pablo Liesenberg
 
Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...
Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...
Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...
Jaipal Dhobale
 
IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...
IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...
IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...
IRJET Journal
 
Serial interface module for ethernet based applications
Serial interface module for ethernet based applicationsSerial interface module for ethernet based applications
Serial interface module for ethernet based applications
eSAT Journals
 
Implementation of intelligent wide area network(wan)- report
Implementation of intelligent wide area network(wan)- reportImplementation of intelligent wide area network(wan)- report
Implementation of intelligent wide area network(wan)- report
Jatin Singh
 
Performance analysis and implementation of modified sdm based noc for mpsoc o...
Performance analysis and implementation of modified sdm based noc for mpsoc o...Performance analysis and implementation of modified sdm based noc for mpsoc o...
Performance analysis and implementation of modified sdm based noc for mpsoc o...
eSAT Journals
 
N017147679
N017147679N017147679
N017147679
IOSR Journals
 
Performance Evaluation of Ipv4, Ipv6 Migration Techniques
Performance Evaluation of Ipv4, Ipv6 Migration TechniquesPerformance Evaluation of Ipv4, Ipv6 Migration Techniques
Performance Evaluation of Ipv4, Ipv6 Migration Techniques
IOSR Journals
 
Latency considerations in_lte
Latency considerations in_lteLatency considerations in_lte
Latency considerations in_lte
Mary McEvoy Carroll
 
ETHERNET PACKET PROCESSOR FOR SOC APPLICATION
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONETHERNET PACKET PROCESSOR FOR SOC APPLICATION
ETHERNET PACKET PROCESSOR FOR SOC APPLICATION
cscpconf
 
Design issues in cc2530 znp multi hop sensor networks
Design issues in cc2530 znp multi hop sensor networksDesign issues in cc2530 znp multi hop sensor networks
Design issues in cc2530 znp multi hop sensor networks
Sreekesh Padmanabhan
 
Nt1310 Unit 5 Algorithm
Nt1310 Unit 5 AlgorithmNt1310 Unit 5 Algorithm
Nt1310 Unit 5 Algorithm
Angie Lee
 
Design of a low power processor for Embedded system applications
Design of a low power processor for Embedded system applicationsDesign of a low power processor for Embedded system applications
Design of a low power processor for Embedded system applications
ROHIT89352
 
IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...
IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...
IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...
IRJET Journal
 
Examen1ccna3v5.0
Examen1ccna3v5.0Examen1ccna3v5.0
Examen1ccna3v5.0
Juan Carlos Banegas
 
Lightweight ANU-II block cipher on field programmable gate array
Lightweight ANU-II block cipher on field programmable gate  arrayLightweight ANU-II block cipher on field programmable gate  array
Lightweight ANU-II block cipher on field programmable gate array
IJECEIAES
 
Yu linux-tsm2004
Yu linux-tsm2004Yu linux-tsm2004
Yu linux-tsm2004
alegara
 
Automatically partitioning packet processing applications for pipelined archi...
Automatically partitioning packet processing applications for pipelined archi...Automatically partitioning packet processing applications for pipelined archi...
Automatically partitioning packet processing applications for pipelined archi...
Ashley Carter
 

Similar to IXP 23XX Network processor (20)

Conference Paper: Universal Node: Towards a high-performance NFV environment
Conference Paper: Universal Node: Towards a high-performance NFV environmentConference Paper: Universal Node: Towards a high-performance NFV environment
Conference Paper: Universal Node: Towards a high-performance NFV environment
 
Communication Performance Over A Gigabit Ethernet Network
Communication Performance Over A Gigabit Ethernet NetworkCommunication Performance Over A Gigabit Ethernet Network
Communication Performance Over A Gigabit Ethernet Network
 
BivioPerformanceWP0605
BivioPerformanceWP0605BivioPerformanceWP0605
BivioPerformanceWP0605
 
Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...
Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...
Wired and Wireless Computer Network Performance Evaluation Using OMNeT++ Simu...
 
IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...
IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...
IRJET-Design of ARM Based Data Acquisition and Control System for Engine Asse...
 
Serial interface module for ethernet based applications
Serial interface module for ethernet based applicationsSerial interface module for ethernet based applications
Serial interface module for ethernet based applications
 
Implementation of intelligent wide area network(wan)- report
Implementation of intelligent wide area network(wan)- reportImplementation of intelligent wide area network(wan)- report
Implementation of intelligent wide area network(wan)- report
 
Performance analysis and implementation of modified sdm based noc for mpsoc o...
Performance analysis and implementation of modified sdm based noc for mpsoc o...Performance analysis and implementation of modified sdm based noc for mpsoc o...
Performance analysis and implementation of modified sdm based noc for mpsoc o...
 
N017147679
N017147679N017147679
N017147679
 
Performance Evaluation of Ipv4, Ipv6 Migration Techniques
Performance Evaluation of Ipv4, Ipv6 Migration TechniquesPerformance Evaluation of Ipv4, Ipv6 Migration Techniques
Performance Evaluation of Ipv4, Ipv6 Migration Techniques
 
Latency considerations in_lte
Latency considerations in_lteLatency considerations in_lte
Latency considerations in_lte
 
ETHERNET PACKET PROCESSOR FOR SOC APPLICATION
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONETHERNET PACKET PROCESSOR FOR SOC APPLICATION
ETHERNET PACKET PROCESSOR FOR SOC APPLICATION
 
Design issues in cc2530 znp multi hop sensor networks
Design issues in cc2530 znp multi hop sensor networksDesign issues in cc2530 znp multi hop sensor networks
Design issues in cc2530 znp multi hop sensor networks
 
Nt1310 Unit 5 Algorithm
Nt1310 Unit 5 AlgorithmNt1310 Unit 5 Algorithm
Nt1310 Unit 5 Algorithm
 
Design of a low power processor for Embedded system applications
Design of a low power processor for Embedded system applicationsDesign of a low power processor for Embedded system applications
Design of a low power processor for Embedded system applications
 
IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...
IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...
IRJET- Assessment of Network Protocol Packet Analysis in IPV4 and IPV6 on Loc...
 
Examen1ccna3v5.0
Examen1ccna3v5.0Examen1ccna3v5.0
Examen1ccna3v5.0
 
Lightweight ANU-II block cipher on field programmable gate array
Lightweight ANU-II block cipher on field programmable gate  arrayLightweight ANU-II block cipher on field programmable gate  array
Lightweight ANU-II block cipher on field programmable gate array
 
Yu linux-tsm2004
Yu linux-tsm2004Yu linux-tsm2004
Yu linux-tsm2004
 
Automatically partitioning packet processing applications for pipelined archi...
Automatically partitioning packet processing applications for pipelined archi...Automatically partitioning packet processing applications for pipelined archi...
Automatically partitioning packet processing applications for pipelined archi...
 

Recently uploaded

The Future of Wearable Technology in Healthcare: Innovations and Trends to Watch
The Future of Wearable Technology in Healthcare: Innovations and Trends to WatchThe Future of Wearable Technology in Healthcare: Innovations and Trends to Watch
The Future of Wearable Technology in Healthcare: Innovations and Trends to Watch
bluetroyvictorVinay
 
"IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER"
"IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER""IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER"
"IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER"
Emmanuel Onwumere
 
一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理
一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理
一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理
bttak
 
世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】
世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】
世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】
bljeremy734
 
买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样
买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样
买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样
nvoyobt
 
一比一原版办理(Caltech毕业证)加州理工学院毕业证
一比一原版办理(Caltech毕业证)加州理工学院毕业证一比一原版办理(Caltech毕业证)加州理工学院毕业证
一比一原版办理(Caltech毕业证)加州理工学院毕业证
kboqz
 
Company Profile of Tempcon - Chiller Manufacturer In India
Company Profile of Tempcon - Chiller Manufacturer In IndiaCompany Profile of Tempcon - Chiller Manufacturer In India
Company Profile of Tempcon - Chiller Manufacturer In India
soumotempcon
 
欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】
欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】
欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】
lopezkatherina914
 
We’re Underestimating the Damage Extreme Weather Does to Rooftop Solar Panels
We’re Underestimating the Damage Extreme Weather Does to Rooftop Solar PanelsWe’re Underestimating the Damage Extreme Weather Does to Rooftop Solar Panels
We’re Underestimating the Damage Extreme Weather Does to Rooftop Solar Panels
Grid Freedom Inc.
 
一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理
一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理
一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理
fyguxu
 
欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】
欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】
欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】
hanniaarias53
 
一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理
一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理
一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理
bttak
 
欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】
欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】
欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】
akrooshsaleem36
 
一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理
一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理
一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理
bttak
 
ℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkata
ℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkataℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkata
ℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkata
nhero3888
 
一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理
一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理
一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理
mbawufebxi
 
按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理
按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理
按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理
uwoso
 

Recently uploaded (17)

The Future of Wearable Technology in Healthcare: Innovations and Trends to Watch
The Future of Wearable Technology in Healthcare: Innovations and Trends to WatchThe Future of Wearable Technology in Healthcare: Innovations and Trends to Watch
The Future of Wearable Technology in Healthcare: Innovations and Trends to Watch
 
"IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER"
"IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER""IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER"
"IOS 18 CONTROL CENTRE REVAMP STREAMLINED IPHONE SHUTDOWN MADE EASIER"
 
一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理
一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理
一比一原版不列颠哥伦比亚大学毕业证(UBC毕业证书)学历如何办理
 
世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】
世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】
世预赛投注-世预赛投注投注官网app-世预赛投注官网app下载|【​网址​🎉ac123.net🎉​】
 
买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样
买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样
买(usyd毕业证书)澳洲悉尼大学毕业证研究生文凭证书原版一模一样
 
一比一原版办理(Caltech毕业证)加州理工学院毕业证
一比一原版办理(Caltech毕业证)加州理工学院毕业证一比一原版办理(Caltech毕业证)加州理工学院毕业证
一比一原版办理(Caltech毕业证)加州理工学院毕业证
 
Company Profile of Tempcon - Chiller Manufacturer In India
Company Profile of Tempcon - Chiller Manufacturer In IndiaCompany Profile of Tempcon - Chiller Manufacturer In India
Company Profile of Tempcon - Chiller Manufacturer In India
 
欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】
欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】
欧洲杯体彩-欧洲杯体彩比赛投注-欧洲杯体彩比赛投注官网|【​网址​🎉ac99.net🎉​】
 
We’re Underestimating the Damage Extreme Weather Does to Rooftop Solar Panels
We’re Underestimating the Damage Extreme Weather Does to Rooftop Solar PanelsWe’re Underestimating the Damage Extreme Weather Does to Rooftop Solar Panels
We’re Underestimating the Damage Extreme Weather Does to Rooftop Solar Panels
 
一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理
一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理
一比一原版(aiti毕业证书)澳洲悉尼翻译学院毕业证如何办理
 
欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】
欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】
欧洲杯赌钱-欧洲杯赌钱冠军-欧洲杯赌钱冠军赔率|【​网址​🎉ac10.net🎉​】
 
一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理
一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理
一比一原版圣托马斯大学毕业证(UST毕业证书)学历如何办理
 
欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】
欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】
欧洲杯投注-欧洲杯投注押注app-欧洲杯投注押注app官网|【​网址​🎉ac10.net🎉​】
 
一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理
一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理
一比一原版西三一大学毕业证(TWU毕业证书)学历如何办理
 
ℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkata
ℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkataℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkata
ℂall Girls Kolkata 😍 Call 0000000 Vip Escorts Service Kolkata
 
一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理
一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理
一比一原版(SBU毕业证书)肯特州立大学毕业证如何办理
 
按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理
按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理
按照学校原版(UPenn文凭证书)宾夕法尼亚大学毕业证快速办理
 

IXP 23XX Network processor

  • 1. White Paper Intel® IXP23XX Product Line of Network Processors Performance of the Intel® IXP23XX Product Line of Network Processors for Access and Edge Network Applications www.intel.com/go/ networkprocessors
  • 2.
  • 3. Contents Introduction ............................................................................................................................................................................ 2 Product line overview ....................................................................................................................................................... 2 Performance metrics ............................................................................................................................................................... 3 Performance assessment of the Intel® IXP2350 network processor ........................................................................................ 3 ATM RAN application example ......................................................................................................................................... 4 Additional application examples ...................................................................................................................................... 5 Conclusion .............................................................................................................................................................................. 5 Introduction Manufacturers of access and edge equipment have long sought the ideal balance of performance and programming flexibility in a processing platform. The fact is, applications such as ATM-based Radio Access Networks, DSL Access Multiplexers (DSLAMs), Wireless Local Area Network (WLAN) access points, WAN multi-service switches, and others, must support a range of protocols and line rates to meet application requirements. Standards-based interfaces and reusable code can help ensure reliable performance as well as accelerate time-to-market and leverage software assets across multiple solutions. And for equipment manufacturers to maximize profitability they must choose the right network processor— one that is neither over-powered nor under-powered, yet offers plenty of headroom in which to innovate. Intel offers an ideal solution with the Intel® IXP23XX product line of network processors, designed to enable a broad range of access and edge applications. Built on the same hardware and software architecture as the entire Intel® IXP2XXX product line, the IXP23XX network processors support deep packet inspection, traffic management, and forwarding at up to 2 Gbps line rates in a single chip, while providing the headroom developers need to deliver value-added network services. Product line overview The IXP23XX product line includes the Intel® IXP2325 network processor, which supports up to 2.5 giga-operations per second with two 32-bit independent multi-threaded microengines, and the Intel® IXP2350 network processor, which supports up to 4.9 giga-operations per second with four 32-bit independent multi-threaded microengines. Variants of 2 each network processor are available with Intel XScale® core operating frequencies ranging from 600 MHz to 1200 MHz, and fast path microengine operating frequencies ranging from 300 MHz to 900 MHz. Both network processors are fully programmable, yet have the processing power to run applications that previously required expensive, high-speed ASICs and external control plane processors. As with all network processors in the entire Intel IXP2XXX product line, the IXP23XX network processors execute data plane tasks in parallel across individual microengines. The Intel® Internet Exchange Architecture (Intel® IXA) Software Framework complements the IXP2XXX modular hardware architecture by providing tested software building blocks, called microblocks, that developers can use to quickly assemble functional sequences, or pipelines, that perform specific network functions. These microblocks are highly reusable across applications; for example, an IP forwarding microblock could be used in a DSLAM application with an ATM media interface, as well as in a WAN multi-service switch. In this white paper, Intel presents a performance assessment of the Intel IXP2350 network processor for a variety of common access and edge applications. In the application examples discussed, packets are processed in microblocks and executed across the microengines within the IXP2350 network processor, processing a comprehensive set of functions for a variety of data rates and communications protocols. As the performance assessment will show, the IXP2350 network processor offers robust performance with substantial headroom even under the most demanding conditions.
  • 4. Performance metrics and IP forwarding example When examining the performance capabilities of a network processor, it is important to first consider the performance metrics used. Two of the primary performance metrics used in the communications and networking industry are packet rate and data rate (see Table 1). In network processors, the unit of work is a packet and, therefore, packet size is a critical parameter in characterizing performance. For example, smaller packets will require a greater number of packets per second to be processed at a given data rate. Since a certain amount of overhead is associated with each packet (e.g., table lookups, header updates, enqueues/dequeues), a greater number of smaller packets being processed per second will mean more work for the network processor and, consequently, less headroom available for value-added features. Conversely, with a fewer number of larger packets at the same data rate, the network processor can complete the same task with less work, thereby retaining greater headroom to support value-added features. A simple application such as IP forwarding for Ethernet packets illustrates this point. An IP forwarding application can be implemented in three stages: packet receive, IP forwarding based on longest prefix match and packet transmit. Table 2 presents estimated performance and packet processing headroom for the Intel® IXP2350 network processor in this application. Communications protocols, such as Gigabit Ethernet and OC-12, each support different minimum-sized packets 3 and carry different levels of overhead. Therefore, for any given data rate, performance—measured in ‘million packets per second’—will ultimately be a factor of packet size and overhead. With maximum data rates of 3.6 Gbps in the IPv4 forwarding example in Table 2, it is evident that the percentage of headroom in the IXP2350 network processor increases as the packet size grows. Performance assessment of the Intel® IXP2350 network processor In assessing the performance of the IXP2350 network processor, Intel chose to use minimum packet sizes in all application examples. By taking this approach, the IXP2350 network processor is subjected to the most demanding conditions likely to be encountered in the real world. Even in these “worst case” scenarios, the IXP2350 network processor demonstrates robust performance with ample headroom in which equipment vendors can add value. To determine performance capabilities for the IXP2350 network processor, Intel calculated the headroom available with all four microengines processing minimum-sized packets with a robust set of application functions at a given data rate. These calculations are based on data from an Intel IXP23XX cycle and data accurate simulator and on previously measured data for the Intel® IXP2400 network processor extrapolated to match the specifications of the IXP2350 network processor. Ethernet Packet Size Intel® IXP2350 Network Processor • Intel XScale® core – 900 MHz • Microengines (ME) – 900 MHz 64 B 25% ME headroom (5.35 Mpps**) 128 B 58% ME headroom (3.04 Mpps**) 512 B 75% ME headroom (0.85 Mpps**) 1518 B 78% ME headroom (0.30 Mpps**) Table 2: IPv4 Forwarding over Ethernet Performance ** Based on maximum bus frequency and associated data rate of 3.6 Gbps on the media interface. Data rate is the total number of Megabits-per-second (Mbps) that a network-ing element can handle. Packet rate is the number of million-packets-per-sec (Mpps) that the networking element can handle. The relation between the data rate and packet rate is simple: Data rate (Mbps) Packet rate (Mpps) = ----------------------- 8x Packet size (bytes) Table 1: Packet Rates vs. Data Rates
  • 5. ATM RAN application example The ATM RAN application is intended for transport line cards in the 3 GPP UTRAN network. In this application, the Intel® IXP2350 network processor is tasked with processing packets from the line interface to the backplane and out a second line interface. Figures 1 and 2 illustrate the full set of functions In this performance assessment, two configurations of the line interface are analyzed: 2xOC-3, which is best suited for the Iub interface of the RNC, and 16 T1/E1, which is best suited for the Iub interface of Node B. In both configurations, 4 /!-#ELL TO)NTEL83CALEš performed by the microengines within the IXP2350 network processor for the ATM RAN application. %NCAPSULATION !!, 3$5 !!,33#32X 0ROCESSING )05$0 %N1UEUE !4- 0ACKET #ELL !4- #ELL /!- 0ROCESSING !4-54/0)! 0HYSICALIF 28FROM-3 !4-2X !UTOPUSH FROM-3 !4- #ELLS !4- 4# SWON.0% !!,#03 2X #03 0ACKETS 0ROCESSING !!,2X 0ROCESSING 0RIORITY 3CHEDULER 4XTO-3 ,%NCAP 'IG%THERNET4X !!, 3$5 )0V 4RANSMIT 7RITETO -3 Figure 1: Data flow from the line interface to backplane. These software blocks are implemented on the microengines of the IXP2350 network processor. 2XFROM-3 'IG%THERNET2X !UTOPUSH FROM-3 )05$0 $ECAPSULATION !!,33#3 4X 0ROCESSING !!,4X 0ROCESSING 4- 7RITEOUT 4- 3CHEDULER $E1UEUE #03 0ACKETS !!, 3$5 )0V 0ACKET !!, 3$5 !4-#ELL %N1UEUE !!,#034X 0ROCESSING 4- 3HAPER 1- LOW#ONTROL 4XTO-3 !4-4X !4- 4# SWON.0% 7RITETO !4- -3 #ELLS !4-54/0)! 0HYSICALIF /!- 0ROCESSING Figure 2: Data flow from the backplane to the line interface. These software blocks are implemented on the microengines of the IXP2350 network processor.
  • 6. performance is quoted under “worst-case,” minimum-sized packet conditions. Additional specifications include: • 100% AAL2 traffic • One AAL2 cell embedded with two 20 B CPS packets • One 20 B CPS packet is mapped to an Ethernet packet on the backplane Under these conditions, the Intel® IXP2350 network processor provided performance results as shown in Table 3. Even when subjected to the most rigorous performance conditions in this ATM RAN application example, the IXP2350 network processor delivers ample headroom to perform additional packet classification, Quality of Service algorithms, or other value-added functions. Additional application examples In addition to ATM RAN, Intel has assessed the performance capabilities of the IXP2350 network processor for several other common access and edge applications, including • IP RAN • ATM+IP RAN • Wi-Fi Aggregator/L2 Switches • IP Routers • DSLAM • Metro/Edge RPR • Wi-Fi to Ethernet Bridge In each case, running a comprehensive range of application functions using minimum-sized packets, the IXP2350 network processor delivered line rate performance at up to 2 Gbps with sufficient headroom to support additional application services.1 With each packet undergoing multiple individual processes on the microengines, these results illustrate that the IXP2350 network processor has the processing power needed to support a broad range of access and edge network applications. Conclusion The Intel® IXP23XX product line of network processors offers network equipment manufacturers a powerful mid-range platform that extends the fully programmable Intel® IXA architecture to new, lower cost/performance points for access and edge applications, including broadband access devices, wireless infrastructure systems, routers and multi-service switches. Robust processing performance for demanding, minimum-size packet applications means that customers can use these network processors with confidence to deliver value-added network services.2 Because the IXP23XX product line integrates key architectural features from the Intel® IXP2XXX product line, developers can take advantage of seamless performance scalability and software reuse from T1/E1 to OC-192/10 Gbps line rates. Line Interface Configuration Intel® IXP2350 Network Processor Variant Microengine Headroom 2xOC-3 900 MHz Intel® XScale core 900 MHz Microengines 28% 16 T1/E1 600 MHz Intel XScale core 300 MHz Microengines 56% Table 3: Performance results for the ATM RAN application 5 1 Actual results will vary depending on how individual vendor applications are written. 2 Performance comparisons should be based on minimum-sized packets.
  • 8. Intel® Internet Exchange Architecture (Intel® IXA) Intel® IXA is a packet processing architecture that provides a foundation for software portability across multiple generations of network processors. Intel IXA is based on programmable microengines, Intel XScale® technology and the Intel IXA Software Framework. Additional information on Intel IXA and the Intel network processor product lines is available at the addresses listed below. Intel Access Intel® Network Processors Web page www.intel.com/go/networkprocessors Intel® Communications Alliance www.intel.com/go/ica Intel in Communications http://intel.com/communications Other Intel Support: Intel® Technical Document Center http://intel.com/go/techdoc (800) 548-4725 7 a.m. to 7 p.m. CST (U.S. and Canada) International locations please contact your local sales office. General Information Hotline (800) 628-8686 or (916) 356-3104 5 a.m. to 5 p.m. PST For more information, visit the Intel web site at: developer.intel.com UNITED STATES AND CANADA EUROPE ASIA-PACIFIC Intel Corporation Intel Corporation (UK) Ltd. Intel Semiconductor Ltd. Robert Noyce Bldg. Pipers Way 32/F Two Pacific Place 2200 Mission College Blvd. Swindon 88 Queensway, Central P.O. Box 58119 Wiltshire SN3 1RJ Hong Kong, SAR Santa Clara, CA 95052-8119 UK USA JAPAN Intel Japan (Tsukuba HQ) 5-6 Tokodai Tsukuba-shi 300-2635 Ibaraki-ken Japan SOUTH AMERICA Intel Semiconductores do Brasil LTDA Av. Dr. Chucri Zaidan, 940-10o andar 04583-904 São Paulo, SP Brazil Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit http://www.intel.com/performance/resources/limits.htm INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel may make changes to specifications, product descriptions, and plans at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. The Intel® IXP23XX Product Line of Network Processors may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available upon request. Intel, the Intel logo and Intel XScale are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2004 Intel Corporation. All rights reserved. 1004/QUA/CM/PDF Please Recycle 304114-001US