This document discusses channel coding and error control coding. It describes different types of coding including source coding, channel coding, cryptographic coding, and line coding. It then focuses on channel coding, explaining that it works by introducing redundancy to transmitted data to minimize the effects of channel noise. Channel coding allows for error detection and correction at the receiver. Common channel coding techniques are block codes and convolutional codes. Block codes map source data into fixed length codewords while convolutional codes use variable length coding where each source bit influences multiple channel bits.
Data Communications (under graduate course) Lecture 5 of 5Randa Elanwar
Undergraduate course content:
Introduction: Types and sources of data, communication models, standards.
Data transmission: techniques, transmission media and characteristics.
Information theory: Information sources, information measure, entropy, source codes.
Line codes: characteristics, return-to-zero and non-return-to-zero signaling, bipolar alternate mark inversion, code (radix, redundancy and efficiency), important codes in current use, frequency spectra characteristics of common line codes, receiver clock synchronization, optical fiber systems, scramblers.
Modems: characteristics, modulation, equalization, control, V-standards.
Error Control: Transmission impairments, forward error control, linear block codes, feedback error control.
Space time block coding is a technique used in wireless communication to transmit multiple copies of a data stream across a number of antennas and to exploit the various received versions of the data to improve the reliability of data transfer. The fact that the transmitted signal must traverse a potentially difficult environment with scattering, reflection, refraction and so on and may then be further corrupted by thermal noise in the receiver means that some of the received copies of the data may be closer to the original signal than others. This redundancy results in a higher chance of being able to use one or more of the received copies to correctly decode the received signal. In fact, space–time coding combines all the copies of the received signal in an optimal way to extract as much information from each of them as possible.
This document summarizes forward error correction techniques using convolutional encoders and Viterbi decoders. It first provides background on communication channels and the need for error correction when transmitting data. It then describes convolutional coding, a technique that maps a continuous stream of input bits to a continuous stream of encoded output bits using shift registers, with the encoded bits depending on current and past input bits. The key aspects of convolutional encoders are discussed, including parameters like the number of output bits, input bits, and shift registers. Generator polynomials are also introduced as characterizing the encoder connections. Viterbi decoding is highlighted as a maximum likelihood algorithm for decoding the trellis structure of convolutional codes based on soft decisions.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
This document discusses channel coding. It defines linear block codes, which encode k information bits into n codeword bits through the addition of n-k check bits. The generator matrix defines the mapping of k message bits to n-bit codewords. Linear block codes have the property that the modulo-2 sum of any two codewords is also a valid codeword. Channel coding introduces redundancy to enable error detection and correction at the receiver. Common channel coding techniques include linear block codes, cyclic codes, and convolutional codes.
This document provides an overview of baseband radio transmission and digital signal processing techniques. It describes the key functions performed in baseband processing including analog to digital conversion, digital speech coding, channel coding and error correction, modulation and demodulation, multiplexing and multiple access, and digital signal processing. Standardization bodies and industry contributors that support wireless technologies are also acknowledged.
Data Communications (under graduate course) Lecture 5 of 5Randa Elanwar
Undergraduate course content:
Introduction: Types and sources of data, communication models, standards.
Data transmission: techniques, transmission media and characteristics.
Information theory: Information sources, information measure, entropy, source codes.
Line codes: characteristics, return-to-zero and non-return-to-zero signaling, bipolar alternate mark inversion, code (radix, redundancy and efficiency), important codes in current use, frequency spectra characteristics of common line codes, receiver clock synchronization, optical fiber systems, scramblers.
Modems: characteristics, modulation, equalization, control, V-standards.
Error Control: Transmission impairments, forward error control, linear block codes, feedback error control.
Space time block coding is a technique used in wireless communication to transmit multiple copies of a data stream across a number of antennas and to exploit the various received versions of the data to improve the reliability of data transfer. The fact that the transmitted signal must traverse a potentially difficult environment with scattering, reflection, refraction and so on and may then be further corrupted by thermal noise in the receiver means that some of the received copies of the data may be closer to the original signal than others. This redundancy results in a higher chance of being able to use one or more of the received copies to correctly decode the received signal. In fact, space–time coding combines all the copies of the received signal in an optimal way to extract as much information from each of them as possible.
This document summarizes forward error correction techniques using convolutional encoders and Viterbi decoders. It first provides background on communication channels and the need for error correction when transmitting data. It then describes convolutional coding, a technique that maps a continuous stream of input bits to a continuous stream of encoded output bits using shift registers, with the encoded bits depending on current and past input bits. The key aspects of convolutional encoders are discussed, including parameters like the number of output bits, input bits, and shift registers. Generator polynomials are also introduced as characterizing the encoder connections. Viterbi decoding is highlighted as a maximum likelihood algorithm for decoding the trellis structure of convolutional codes based on soft decisions.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
This document discusses channel coding. It defines linear block codes, which encode k information bits into n codeword bits through the addition of n-k check bits. The generator matrix defines the mapping of k message bits to n-bit codewords. Linear block codes have the property that the modulo-2 sum of any two codewords is also a valid codeword. Channel coding introduces redundancy to enable error detection and correction at the receiver. Common channel coding techniques include linear block codes, cyclic codes, and convolutional codes.
This document provides an overview of baseband radio transmission and digital signal processing techniques. It describes the key functions performed in baseband processing including analog to digital conversion, digital speech coding, channel coding and error correction, modulation and demodulation, multiplexing and multiple access, and digital signal processing. Standardization bodies and industry contributors that support wireless technologies are also acknowledged.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FEC-Forward Error Correction for Optics ProfessionalsMapYourTech
Forward error correction (FEC) adds redundancy to transmitted data to allow errors to be detected and corrected without retransmission. It works by encoding data at the transmitter and decoding it at the receiver. FEC provides increased transmission distance and reliability by improving the bit error rate. Reed-Solomon codes are commonly used for FEC as they can efficiently correct multiple errors within a code block. The amount of redundancy added depends on the code's error correction capability, with higher correction requiring more overhead bits.
FEC-Forward Error Correction for Optics Professionals..www.mapyourtech.comMapYourTech
Forward error correction (FEC) adds redundancy to transmitted data to allow the detection and correction of errors without retransmission. FEC works by encoding data at the transmitter and decoding it at the receiver. It allows reliable data transmission over noisy communication channels and improves performance metrics like bit error rate. Common FEC codes include Reed-Solomon codes, which offer good error correction ability and are widely used in optical communication systems to improve transmission distance and efficiency.
The document compares the performance of single stage and double stage interleavers in communication systems using turbo codes. A single stage interleaver uses one random interleaver between two convolutional encoders, while a double stage interleaver uses two interleavers in series. The document suggests that a double stage interleaver can improve the bit error rate (BER) of the system compared to a single stage interleaver by further scrambling the input bits. It also provides details on the components of a turbo code system such as convolutional encoders, interleavers, puncturing, and iterative decoding.
Vlsi Implementation of Low Power Convolutional Coding With Viterbi Decoding U...IOSR Journals
This document discusses the VLSI implementation of a low power convolutional coding system with Viterbi decoding using finite state machines (FSM). It begins with an introduction to convolutional encoding and Viterbi decoding. It then describes the convolutional encoder which uses a shift register, the state diagram representation, and provides an example of encoding an input sequence. It discusses the Viterbi decoder structure including the branch metric unit, add-compare-select unit, and survivor path memory. It presents the Viterbi algorithm for decoding and shows simulation results of encoding and decoding an input sequence using FSMs. It concludes that the Viterbi algorithm allows for error correction without retransmissions and recovering the original message accurately.
This document presents research on implementing CRC and Viterbi error correction techniques on a DSP processor. CRC-32 and Viterbi decoding algorithms for convolutional codes with rate 1/2 and different generator polynomials are simulated and implemented on a TMS320C5416 DSP chip. Additionally, a concept of serially concatenated CRC-convolutional coding is proposed, using a lookup table at the decoder to potentially reduce computations compared to traditional Viterbi decoding. Simulation results demonstrating CRC-8, CRC-32, and Viterbi decoding with various generator polynomials and error scenarios are shown. The techniques are successfully implemented on the DSP hardware.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
Turbo codes provide reliable communication at high data rates by combining concepts from block and convolutional codes. They use two convolutional encoders separated by an interleaver, producing redundant parity bits. During iterative decoding, probabilistic information from the first decoder is used as a priori information for the second decoder, and vice versa, improving the estimates of the transmitted bits at each iteration. Turbo codes achieve performance close to the theoretical channel capacity limit with low error rates. They have applications in deep space communications, mobile wireless systems, and other areas requiring high reliability transmission.
This document summarizes a research paper that proposes using parallel concatenated turbo codes in wireless sensor networks in an adaptive way. The key points are:
1) Turbo codes can achieve near-Shannon limit performance but decoding is complex, making them difficult to implement on energy-constrained sensor nodes.
2) The proposed approach shifts the complex turbo decoding to the base station while sensor nodes implement encoding and basic error correction.
3) At sensor nodes, a parallel concatenated convolutional code (PCCC) circuit encodes data and detects/corrects errors in forwarded packets. This improves energy efficiency and reliability over the wireless sensor network.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
The document summarizes a research paper that proposes a low density parity check (LDPC) algorithm for insertion/deletion channels. It begins by providing background on LDPC codes and how they are finding increasing use for reliable information transfer over bandwidth-constrained links with noise. It then describes the specific system model of a concatenated coding scheme using an outer error correcting code and inner marker code. The document analyzes the achievable transmission rates using this scheme through both bit-level and symbol-level maximum a posteriori probability (MAP) detection algorithms. It finds that the symbol-level approach confirms an advantage over codes optimized for additive white Gaussian noise channels.
This document summarizes techniques for error detection and correction in data communication systems. It discusses various error correction techniques including forward error correction using block codes, convolutional codes, and hybrid automatic repeat request. It focuses on convolutional codes and the Viterbi algorithm, describing the algorithm's use of branch metric computation, path metric computation, and traceback to decode data with the minimum accumulated error path. The document concludes that convolutional encoding with Viterbi decoding is an effective method for forward error correction in wireless communication systems.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
Noise Immune Convolutional Encoder Design and Its Implementation in Tanner ijcisjournal
With the rapid advances in integrated circuit(IC) technologies, number of functions on a chip was
increasing at a very fast rate, with which interconnect density is increasing especially in functional logic
chips. The on-chip noise affects are increasing and needs to be addressed. In this paper we have
implemented a convolution encoder using a technique that provides higher noise immunity. The encoder
circuit is simulated in Tanner 15.0 with data rate of 25Mbps and a clock frequency of 250MHz
NOISE IMMUNE CONVOLUTIONAL ENCODER DESIGN AND ITS IMPLEMENTATIONIN TANNERIJCI JOURNAL
With the rapid advances in integrated circuit(IC) technologies, number of functions on a chip was increasing at a very fast rate, with which interconnect density is increasing especially in functional logic chips. The on-chip noise affects are increasing and needs to be addressed. In this paper we have implemented a convolution encoder using a technique that provides higher noise immunity. The encoder circuit is simulated in Tanner 15.0 with data rate of 25Mbps and a clock frequency of 250MHz
Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.
This document analyzes the performance of digital audio broadcasting (DAB) systems using orthogonal frequency division multiplexing (OFDM) and Reed Solomon coding. It discusses the components of a DAB system including source coding, channel coding using Reed Solomon codes, transmission frame structure, and coded OFDM. Simulation results show the bit error rate versus signal-to-noise ratio for DAB modes I and II, demonstrating lower bit error rates at higher signal-to-noise ratios when using Reed Solomon coding compared to previous work. The document concludes the analysis and discusses limitations and potential future work.
Channel coding is used in digital communication systems to provide error control and allow reliable transmission of information over noisy channels. The two main methods of error control coding are forward error correction (FEC) and automatic repeat request (ARQ). FEC encodes redundant data into each message to allow the receiver to correct errors without requesting retransmissions, while ARQ relies on the receiver to request retransmission of corrupted data. Common types of FEC codes include block codes, cyclic codes, and convolutional codes, with each code characterized by parameters like coding rate and minimum distance that determine its error detection and correction capabilities.
LDPC BASED ERROR CORRECTION WITH BIT LEVEL AND SYMBOL LEVEL SYNCHRONIZATION USING MARKER CODE OPTIMIZATION
Low-density parity check code with error-correction capabilities and Marker code for synchronization purposes are used
The marker code structures offer the ultimate achievable rate when standard bit-level synchronization are performed
Symbol-level synchronization algorithm works on group of bits and show how it improves the achievable rate along with the error rate performance
When multiple pass decoding is performed the extrinsic information transfer (EXIT) charts are used to analyze the receiver
The Reliability in Decoding of Turbo Codes for Wireless CommunicationsIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
simplified modulation technique paves the way for more straightforward and
efficient control of multilevel inverters, enabling their widespread adoption and
integration into modern power electronic systems. Through the amalgamation of
sinusoidal pulse width modulation (SPWM) with a high-frequency square wave
pulse, this controlling technique attains energy equilibrium across the coupling
capacitor. The modulation scheme incorporates a simplified switching pattern
and a decreased count of voltage references, thereby simplifying the control
algorithm.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FEC-Forward Error Correction for Optics ProfessionalsMapYourTech
Forward error correction (FEC) adds redundancy to transmitted data to allow errors to be detected and corrected without retransmission. It works by encoding data at the transmitter and decoding it at the receiver. FEC provides increased transmission distance and reliability by improving the bit error rate. Reed-Solomon codes are commonly used for FEC as they can efficiently correct multiple errors within a code block. The amount of redundancy added depends on the code's error correction capability, with higher correction requiring more overhead bits.
FEC-Forward Error Correction for Optics Professionals..www.mapyourtech.comMapYourTech
Forward error correction (FEC) adds redundancy to transmitted data to allow the detection and correction of errors without retransmission. FEC works by encoding data at the transmitter and decoding it at the receiver. It allows reliable data transmission over noisy communication channels and improves performance metrics like bit error rate. Common FEC codes include Reed-Solomon codes, which offer good error correction ability and are widely used in optical communication systems to improve transmission distance and efficiency.
The document compares the performance of single stage and double stage interleavers in communication systems using turbo codes. A single stage interleaver uses one random interleaver between two convolutional encoders, while a double stage interleaver uses two interleavers in series. The document suggests that a double stage interleaver can improve the bit error rate (BER) of the system compared to a single stage interleaver by further scrambling the input bits. It also provides details on the components of a turbo code system such as convolutional encoders, interleavers, puncturing, and iterative decoding.
Vlsi Implementation of Low Power Convolutional Coding With Viterbi Decoding U...IOSR Journals
This document discusses the VLSI implementation of a low power convolutional coding system with Viterbi decoding using finite state machines (FSM). It begins with an introduction to convolutional encoding and Viterbi decoding. It then describes the convolutional encoder which uses a shift register, the state diagram representation, and provides an example of encoding an input sequence. It discusses the Viterbi decoder structure including the branch metric unit, add-compare-select unit, and survivor path memory. It presents the Viterbi algorithm for decoding and shows simulation results of encoding and decoding an input sequence using FSMs. It concludes that the Viterbi algorithm allows for error correction without retransmissions and recovering the original message accurately.
This document presents research on implementing CRC and Viterbi error correction techniques on a DSP processor. CRC-32 and Viterbi decoding algorithms for convolutional codes with rate 1/2 and different generator polynomials are simulated and implemented on a TMS320C5416 DSP chip. Additionally, a concept of serially concatenated CRC-convolutional coding is proposed, using a lookup table at the decoder to potentially reduce computations compared to traditional Viterbi decoding. Simulation results demonstrating CRC-8, CRC-32, and Viterbi decoding with various generator polynomials and error scenarios are shown. The techniques are successfully implemented on the DSP hardware.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
Turbo codes provide reliable communication at high data rates by combining concepts from block and convolutional codes. They use two convolutional encoders separated by an interleaver, producing redundant parity bits. During iterative decoding, probabilistic information from the first decoder is used as a priori information for the second decoder, and vice versa, improving the estimates of the transmitted bits at each iteration. Turbo codes achieve performance close to the theoretical channel capacity limit with low error rates. They have applications in deep space communications, mobile wireless systems, and other areas requiring high reliability transmission.
This document summarizes a research paper that proposes using parallel concatenated turbo codes in wireless sensor networks in an adaptive way. The key points are:
1) Turbo codes can achieve near-Shannon limit performance but decoding is complex, making them difficult to implement on energy-constrained sensor nodes.
2) The proposed approach shifts the complex turbo decoding to the base station while sensor nodes implement encoding and basic error correction.
3) At sensor nodes, a parallel concatenated convolutional code (PCCC) circuit encodes data and detects/corrects errors in forwarded packets. This improves energy efficiency and reliability over the wireless sensor network.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
The document summarizes a research paper that proposes a low density parity check (LDPC) algorithm for insertion/deletion channels. It begins by providing background on LDPC codes and how they are finding increasing use for reliable information transfer over bandwidth-constrained links with noise. It then describes the specific system model of a concatenated coding scheme using an outer error correcting code and inner marker code. The document analyzes the achievable transmission rates using this scheme through both bit-level and symbol-level maximum a posteriori probability (MAP) detection algorithms. It finds that the symbol-level approach confirms an advantage over codes optimized for additive white Gaussian noise channels.
This document summarizes techniques for error detection and correction in data communication systems. It discusses various error correction techniques including forward error correction using block codes, convolutional codes, and hybrid automatic repeat request. It focuses on convolutional codes and the Viterbi algorithm, describing the algorithm's use of branch metric computation, path metric computation, and traceback to decode data with the minimum accumulated error path. The document concludes that convolutional encoding with Viterbi decoding is an effective method for forward error correction in wireless communication systems.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
Noise Immune Convolutional Encoder Design and Its Implementation in Tanner ijcisjournal
With the rapid advances in integrated circuit(IC) technologies, number of functions on a chip was
increasing at a very fast rate, with which interconnect density is increasing especially in functional logic
chips. The on-chip noise affects are increasing and needs to be addressed. In this paper we have
implemented a convolution encoder using a technique that provides higher noise immunity. The encoder
circuit is simulated in Tanner 15.0 with data rate of 25Mbps and a clock frequency of 250MHz
NOISE IMMUNE CONVOLUTIONAL ENCODER DESIGN AND ITS IMPLEMENTATIONIN TANNERIJCI JOURNAL
With the rapid advances in integrated circuit(IC) technologies, number of functions on a chip was increasing at a very fast rate, with which interconnect density is increasing especially in functional logic chips. The on-chip noise affects are increasing and needs to be addressed. In this paper we have implemented a convolution encoder using a technique that provides higher noise immunity. The encoder circuit is simulated in Tanner 15.0 with data rate of 25Mbps and a clock frequency of 250MHz
Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.
This document analyzes the performance of digital audio broadcasting (DAB) systems using orthogonal frequency division multiplexing (OFDM) and Reed Solomon coding. It discusses the components of a DAB system including source coding, channel coding using Reed Solomon codes, transmission frame structure, and coded OFDM. Simulation results show the bit error rate versus signal-to-noise ratio for DAB modes I and II, demonstrating lower bit error rates at higher signal-to-noise ratios when using Reed Solomon coding compared to previous work. The document concludes the analysis and discusses limitations and potential future work.
Channel coding is used in digital communication systems to provide error control and allow reliable transmission of information over noisy channels. The two main methods of error control coding are forward error correction (FEC) and automatic repeat request (ARQ). FEC encodes redundant data into each message to allow the receiver to correct errors without requesting retransmissions, while ARQ relies on the receiver to request retransmission of corrupted data. Common types of FEC codes include block codes, cyclic codes, and convolutional codes, with each code characterized by parameters like coding rate and minimum distance that determine its error detection and correction capabilities.
LDPC BASED ERROR CORRECTION WITH BIT LEVEL AND SYMBOL LEVEL SYNCHRONIZATION USING MARKER CODE OPTIMIZATION
Low-density parity check code with error-correction capabilities and Marker code for synchronization purposes are used
The marker code structures offer the ultimate achievable rate when standard bit-level synchronization are performed
Symbol-level synchronization algorithm works on group of bits and show how it improves the achievable rate along with the error rate performance
When multiple pass decoding is performed the extrinsic information transfer (EXIT) charts are used to analyze the receiver
The Reliability in Decoding of Turbo Codes for Wireless CommunicationsIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Similar to Introduction to Channel Coding.pdf (20)
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
simplified modulation technique paves the way for more straightforward and
efficient control of multilevel inverters, enabling their widespread adoption and
integration into modern power electronic systems. Through the amalgamation of
sinusoidal pulse width modulation (SPWM) with a high-frequency square wave
pulse, this controlling technique attains energy equilibrium across the coupling
capacitor. The modulation scheme incorporates a simplified switching pattern
and a decreased count of voltage references, thereby simplifying the control
algorithm.
Null Bangalore | Pentesters Approach to AWS IAMDivyanshu
#Abstract:
- Learn more about the real-world methods for auditing AWS IAM (Identity and Access Management) as a pentester. So let us proceed with a brief discussion of IAM as well as some typical misconfigurations and their potential exploits in order to reinforce the understanding of IAM security best practices.
- Gain actionable insights into AWS IAM policies and roles, using hands on approach.
#Prerequisites:
- Basic understanding of AWS services and architecture
- Familiarity with cloud security concepts
- Experience using the AWS Management Console or AWS CLI.
- For hands on lab create account on [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
# Scenario Covered:
- Basics of IAM in AWS
- Implementing IAM Policies with Least Privilege to Manage S3 Bucket
- Objective: Create an S3 bucket with least privilege IAM policy and validate access.
- Steps:
- Create S3 bucket.
- Attach least privilege policy to IAM user.
- Validate access.
- Exploiting IAM PassRole Misconfiguration
-Allows a user to pass a specific IAM role to an AWS service (ec2), typically used for service access delegation. Then exploit PassRole Misconfiguration granting unauthorized access to sensitive resources.
- Objective: Demonstrate how a PassRole misconfiguration can grant unauthorized access.
- Steps:
- Allow user to pass IAM role to EC2.
- Exploit misconfiguration for unauthorized access.
- Access sensitive resources.
- Exploiting IAM AssumeRole Misconfiguration with Overly Permissive Role
- An overly permissive IAM role configuration can lead to privilege escalation by creating a role with administrative privileges and allow a user to assume this role.
- Objective: Show how overly permissive IAM roles can lead to privilege escalation.
- Steps:
- Create role with administrative privileges.
- Allow user to assume the role.
- Perform administrative actions.
- Differentiation between PassRole vs AssumeRole
Try at [killercoda.com](https://killercoda.com/cloudsecurity-scenario/)
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Design and optimization of ion propulsion dronebjmsejournal
Electric propulsion technology is widely used in many kinds of vehicles in recent years, and aircrafts are no exception. Technically, UAVs are electrically propelled but tend to produce a significant amount of noise and vibrations. Ion propulsion technology for drones is a potential solution to this problem. Ion propulsion technology is proven to be feasible in the earth’s atmosphere. The study presented in this article shows the design of EHD thrusters and power supply for ion propulsion drones along with performance optimization of high-voltage power supply for endurance in earth’s atmosphere.
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.
Software Engineering and Project Management - Introduction, Modeling Concepts...Prakhyath Rai
Introduction, Modeling Concepts and Class Modeling: What is Object orientation? What is OO development? OO Themes; Evidence for usefulness of OO development; OO modeling history. Modeling
as Design technique: Modeling, abstraction, The Three models. Class Modeling: Object and Class Concept, Link and associations concepts, Generalization and Inheritance, A sample class model, Navigation of class models, and UML diagrams
Building the Analysis Models: Requirement Analysis, Analysis Model Approaches, Data modeling Concepts, Object Oriented Analysis, Scenario-Based Modeling, Flow-Oriented Modeling, class Based Modeling, Creating a Behavioral Model.
Rainfall intensity duration frequency curve statistical analysis and modeling...bijceesjournal
Using data from 41 years in Patna’ India’ the study’s goal is to analyze the trends of how often it rains on a weekly, seasonal, and annual basis (1981−2020). First, utilizing the intensity-duration-frequency (IDF) curve and the relationship by statistically analyzing rainfall’ the historical rainfall data set for Patna’ India’ during a 41 year period (1981−2020), was evaluated for its quality. Changes in the hydrologic cycle as a result of increased greenhouse gas emissions are expected to induce variations in the intensity, length, and frequency of precipitation events. One strategy to lessen vulnerability is to quantify probable changes and adapt to them. Techniques such as log-normal, normal, and Gumbel are used (EV-I). Distributions were created with durations of 1, 2, 3, 6, and 24 h and return times of 2, 5, 10, 25, and 100 years. There were also mathematical correlations discovered between rainfall and recurrence interval.
Findings: Based on findings, the Gumbel approach produced the highest intensity values, whereas the other approaches produced values that were close to each other. The data indicates that 461.9 mm of rain fell during the monsoon season’s 301st week. However, it was found that the 29th week had the greatest average rainfall, 92.6 mm. With 952.6 mm on average, the monsoon season saw the highest rainfall. Calculations revealed that the yearly rainfall averaged 1171.1 mm. Using Weibull’s method, the study was subsequently expanded to examine rainfall distribution at different recurrence intervals of 2, 5, 10, and 25 years. Rainfall and recurrence interval mathematical correlations were also developed. Further regression analysis revealed that short wave irrigation, wind direction, wind speed, pressure, relative humidity, and temperature all had a substantial influence on rainfall.
Originality and value: The results of the rainfall IDF curves can provide useful information to policymakers in making appropriate decisions in managing and minimizing floods in the study area.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
Introduction to Channel Coding.pdf
1. Course Coordinator:-
Dr. Mulugeta Atlabachew (Ass. Professor)
HARAMAYA UNIVERSITY
HARAMAYA INSTITUTE OF TECHNOLOGY
SCHOOL OF ELECTRICAL AND COMPUTER
ENGINEERING
Course Coordinator:-
Dr. Mulugeta Atlabachew (Ass. Professor),
Guest Lecturer
Introduction to Channel Coding
2. Channel Coding
Types of Coding
Source Coding (Data Compression)- Code data to more efficiently
represent the information
Reduces ―size‖ of data
Analog - Encode analog source data into a binary format
Digital - Reduce the ―size‖ of digital source data
Channel Coding ( Error Control) - Code data for transmission
over a noisy communication channel
Increases ―size‖ of data
Digital - add redundancy to identify and correct errors
Analog - represent digital values by analog signals
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3. Channel Coding
Types of Coding
Source Coding (Data Compression)- Code data to more efficiently
represent the information
Reduces ―size‖ of data
Analog - Encode analog source data into a binary format
Digital - Reduce the ―size‖ of digital source data
Channel Coding ( Error Control) - Code data for transmission over
a noisy communication channel
Increases ―size‖ of data
Digital - add redundancy to identify and correct errors
Analog - represent digital values by analog signals
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4. Channel Coding
Types of Coding
Cryptographic Coding - Cryptography or cryptographic coding is the practice
and study of techniques for secure communication in the presence of third
parties (called adversaries).
Cryptography makes sure that messages remain unreadable — except to the intended recipient.
More generally, it is about constructing and analyzing protocols that block adversaries.
Line Coding - A line code (also called digital baseband modulation or digital
baseband transmission method) is a code chosen for use within a communication
system for baseband transmission purposes.
Line coding is often used for digital data transport.
Line coding consists of representing the digital signal to be transported by an amplitude- and time-
discrete signal that is optimally tuned for the specific properties of the physical channel (and of the
receiving equipment).
The common types of line encoding are unipolar, polar, bipolar, and Manchester encoding.
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5. Channel Coding
Why Channel Coding?
To increase the resistance of digital communication systems to
channel noise via error control coding.
How Channel Coding Works?
By mapping the incoming data sequence into a channel input
sequence and inverse mapping the channel output sequence into
an output data sequence in such a way that the overall effect of
channel noise on the system is minimized
Redundancy is introduced in the channel encoder so as to
reconstruct the original source sequence as accurately as
possible.
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6. Channel Coding
The implication of Error Control Coding (Channel Coding)
Addition of redundancy implies the need for increased
transmission bandwidth.
It also adds complexity in the decoding operation.
Therefore, there is a design trade-off in the use of
error-control coding.
achieving acceptable error performance shall be traded for
bandwidth and system complexity.
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7. Channel Coding
Channel Coding Taxonomy
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8. Channel Coding
Generally
Coding is used for error detection and/or error correction.
Coding is a compromise between reliability, efficiency, equipment
complexity.
Channel Coding is mapping of binary source (usually) output sequences
of length k into binary channel input sequences n (>k).
Binary coding produces 2k codewords of length n.
Extra bits in codewords are used for error detection/correction.
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9. Channel Coding
The most popular channel coding techniques which are realized
by binary numbers are block codes and convolutional codes.
Block codes: mapping of information source into channel
inputs is done independently: Encoder output depends only on
the current block of input sequence.
Convolutional codes: each source bit influences n(L+1)
channel input bits. n(L+1) is the constraint length and L is the
memory depth. These codes are denoted by (n,k,L).
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10. Block Codes
It is in the form of (n,k) block code where n is the number of bits of the codeword
and k is the number of bits for the binary message (Dataword).
To generate an (n,k) block code, the channel encoder accepts information in
successive k-bit blocks.
For each block add (n-k) redundant bits to produce an encoded block of n-bits called
a codeword.
The (n-k) redundant bits are algebraically related to the k message bits.
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11. Block Codes
The channel encoder produces bits at a rate called the channel
data rate, R0
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s
R
k
n
R
0
Where Rs is the bit rate of the information
source and n/k is the code rate
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12. Block Codes
Forward Error-Correction (FEC)
The channel encoder accepts information in successive k-bit blocks and for
each block it adds (n-k) redundant bits to produce an encoded block of n-bits
called a codeword.
The channel decoder uses the redundancy to decide which message bits
were actually transmitted.
The central idea is the sender encodes the message with redundant
information in the form of an ECC (Error Correction Code).
The redundancy allows the receiver
to detect a limited number of errors that may occur anywhere in the message, and
to correct these errors without retransmission.
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13. Block Codes
Forward Error-Correction (FEC)
In this case, whether the decoding of the received code
word is successful or not, the receiver does not perform
further processing for retransmission.
i.e, if an error is detected in a transmitted code word, the
receiver does not request for retransmission of the
corrupted code word.
Appropriate for delay sensitive and one-way transmission
(e.g., broadcast TV) of data
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14. Block Codes
Forward Error-Correction (FEC)
ECC is accomplished by adding redundancy to the transmitted
information using an algorithm.
A redundant bit may be a complex function of many original
information bits.
The original information may or may not appear literally in the
encoded output;
codes that include the unmodified input in the output are systematic,
while those that do not are non-systematic.
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15. Block Codes
Backward Error-Correction (BEC)-
BEC can be realized by Using Automatic-Repeat Request Scheme (ARQ)
In this scheme, upon detection of error, the receiver requests a repeat
transmission of the corrupted codeword
The major advantage of ARQ over Forward Error Correction (FEC)
schemes is that
error detection requires much simpler decoding mechanisms and much less
redundancy than error correction.
There are 3 types of ARQ scheme
• Stop-and-Wait
• Continuous ARQ with pullback
• Continuous ARQ with selective repeat
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16. Block Codes
Backward Error-Correction (BEC)-Types
Stop-and-wait
A block of message is encoded into a code word and transmitted
The transmitter stops and waits for feedback from the receiver
either an acknowledgement of a correct receipt of the codeword
or a retransmission request due to error in decoding.
The transmitter resends the codeword before moving onto the
next block of message.
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17. Block Codes
Backward Error-Correction (BEC)-Types
Continuous ARQ with pullback (Go-back-N)
Allows the receiver to send a feedback signal while the
transmitter is sending another codeword
The transmitter continues to send a succession of code words
until it receives a retransmission request.
It then stops and pulls back to the particular code word that was
not correctly decoded and retransmits the complete sequence of
code words starting with the corrupted one.
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18. Block Codes
Backward Error-Correction (BEC)-Types
Continuous ARQ with selective repeat
Retransmits the code word that was incorrectly decoded only.
Thus, eliminates the need for retransmitting the successfully
decoded code words.
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19. Important Terminologies
Modular Arithmetic- In modulo-N arithmetic, we use only the integers in the range
0 to N −1, inclusive. We define an upper limit, called a Modulus N. We then use only
the integers 0 to N −1, inclusive.
Modulo-2 Arithmetic-The encoding and decoding functions involve the binary
arithmetic operation (XOR).
Rules for modulo-2 operations are:
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20. Important Terminologies
Hamming Distance- The Hamming distance between two words d(x,y)
over the same alphabet is the number of places where the symbols
differ. It measures
the minimum number of substitutions required to change one word into the other,
the minimum number of errors that could have transformed one word into the
other.
The Hamming distance can easily be found if we apply the XOR operation
( ) on the two words and count the number of 1s in the result.
Minimum Hamming Distance- The minimum Hamming distance, dmin, is
the smallest Hamming distance between all possible pairs in a set of
words.
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21. Important Terminologies
Example- Find the minimum Hamming distance of the coding scheme
presented in table below.
Solution- We first find all Hamming distances.
Then, dmin in this case becomes 3.
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22. Important Terminologies
Therefore,
The Hamming distance between the received cordword and the sent codeword
is the number of bits that are corrupted during transmission.
To guarantee the detection of up to s errors in all cases, the minimum
Hamming distance in a block code must be
dmin = s + 1.
Then, the received codeword does not match a valid codeword.
Code strength is measured by Hamming distance that tells how
different codewords are:
Codes are more powerful when their minimum Hamming distance dmin (over all
codes in the code family) is large.
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23. Important Terminologies
To guarantee the detection of up to s errors in all cases, the minimum
Hamming distance in a block code must be
dmin = s + 1.
Geometrical concept for dmin in error detection
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24. Important Terminologies
To guarantee correction of up to t errors in all cases, the minimum
Hamming distance in a block code must be
dmin = 2t + 1.
Geometrical concept for finding dmin for error correction
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25. Important Terminologies
Hamming distance: The decision sphere interpretation
It can be seen that we can detect s=dmin-1 errors in the codewords.
This is because the only way to NOT to detect the error is that the
error completely transforms the code into another codeword. This
requires the change of at least dmin code bits. Therefore the error
detection upper bound is dmin-1.
Also, we can see that we can correct t=(dmin-1)/2 errors. If more
errors occur, the received word may fall into the decoding sphere of
another code word (see the above figure).
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26. Important Terminologies
Hamming distance: The decision sphere interpretation
Consider two block code (n,k) words c1 and c2 at the Hamming
distance in the n-dimensional code space:
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,
min ( , )
i j
i j
d d c c
1
c 2
c
/ 2
d
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27. Important Terminologies
Hamming distance: Example
0100→1001 has distance 3;
0110→1110 has distance 1
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28. Important Terminologies
Example
Look the previous example, this code has dmin=3, this code detects up to two errors.
Again, we see that when any of the valid codewords is sent, two errors create a
codeword which is not in the table of valid codewords.
However, some combinations of three errors change a valid codeword to another
valid codeword. The receiver accepts the received codeword and the errors are
undetected.
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29. Properties of Hamming Distance
Take away
Hamming Distance-The Hamming distance between two
words over the same alphabet is the number of places
where the symbols differ.
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30. Properties of Hamming Distance
The binomial distribution with parameters n and p is the
number of successes in a sequence of n independent
experiments, each asking a yes–no question, and each with its
own Boolean-valued outcome:
Success (with probability p)
Failure (with probability q = 1 − p).
A single success/failure experiment is also called a Bernoulli
trial or Bernoulli experiment, and
A sequence of outcomes is called a Bernoulli process; for a
single trial, i.e., n = 1, the binomial distribution is a Bernoulli
distribution.
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31. Binomial Distribution
If the random variable X follows the binomial distribution with parameters
n ∈ ℕ and p ∈ [0,1], The probability of getting exactly k successes in n
independent Bernoulli trials is given by the probability mass function:
The formula can be understood as follows: k successes occur with
probability pk and n − k failures occur with probability (1 − p)n − k.
However, the k successes can occur anywhere among the n trials, and
there are different ways of distributing k successes in a sequence of
n trials.
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32. Properties of Hamming Distance
Def: The weight of a codeword ci , denoted by w(ci),
is the number of nonzero elements in the codeword.
Def: The minimum weight of a code, wmin, is the
smallest weight of the nonzero codewords in the
code.
Theorem: In any linear code, dmin = wmin
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33. Linear Block Codes
A code is said to be linear if any two valid codewords in the
code can be added in modulo-2 arithmetic to produce a
third valid codeword in the code.
i.e, if m and m’ have respective codewords c(m) and c(m’),
then c(m + m’)=c(m) + c(m’) is a codeword for message (m
+ m’)
Examples
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34. Linear Block Codes
Types of Linear Block Codes
The Repetition Code
Parity-check Codes
Systematic Block Codes
Hamming Code
Cyclic Codes
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35. Linear Block Codes-The Repetition Code
The repetition code is one of the most basic error-correcting codes.
The idea of the repetition code is to just repeat the message several
times.
The hope is that the channel corrupts only a minority of these
repetitions.
This way the receiver will notice that a transmission error occurred
since the received data stream is not the repetition of a single
message,
The receiver can recover the original message by looking at the
received message in the data stream that occurs most often.
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36. Linear Block Codes-The Repetition Code
It has bad error correcting performance and low code rate.
The advantages of the repetition code is the ease of implementation,
and reliability.
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37. Linear Block Codes-The Repetition Code
In the case of a binary repetition code, there exist two codewords - all
ones and all zeros - which have a length of n.
Therefore, the minimum Hamming distance of the code equals its
length n.
This gives the repetition code an error correcting capacity of (n−1)/ 2.
If the length of a binary repetition code is odd, then it's a perfect
code.
The binary repetition code of length n is equivalent to the (n,1)-Hamming
code.
It uses the Maximum Likelihood Decoding-it decides on the most
probable
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38. Linear Block Codes-The Repetition Code
Consider for instance (3,1) repetition code, yielding the code rate
Encoded word is formed by the simple coding rule:
Code is decoded by majority voting, e.g. for instance:
the probability that a group of three repeated bits decoded correctly
is given by
pr (no error) + pr(one error)=p3+3p2(1-p)
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/ 1/3
C
R k n
1 111 0 000
001 0, 101 1
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39. Linear Block Codes-The Repetition Code
Assuming binomial error distribution, the bit error is given
by :
From our example, Error in decoding is introduced if all the
bits are inverted or two bits are inverted (by noise or
interference), e.g. majority of bits are in-error
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( , ) (1 ) , 1
i n i i
n n
P i n
i i
2 3
(2,3) (3,3) 3 2
we
P P P
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40. Linear Block Codes-The Repetition Code
In a three bit codeword
Always one error can be corrected, because majority voting can
detect and correct one codeword bit error.
Always two errors can be detected, because all codewords must
be all zeros or all ones (but now the encoded bit can not be
recovered).
Decoding error occurs if at least (n+1)/2 of the transmitted symbols
are received in error. Therefore the error probability can be
expressed as
or
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( 1)/ 2
(1 )
n
k n k
e
k n
n
p
k
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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41. Points for Discussion
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42
For a transmitted message of length n there are n +1
situations the receiver has to distinguish between:
no errors and a single error in a specified position along the string
of n received bits.
Any linear code can be transformed into an equivalent
systematic code.
A systematic code is one where every n-bit codeword can
be represented as the original k-bit message followed by
the n -k parity bits.
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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42. Points for Discussion
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43
Given a systematic code, how many parity bits do we absolutely need in
Single Error Correction Code?
We need to choose n so that single error correction is possible and the
error occurs in any position.
Since there are n -k parity bits, each combination of these bits must
represent some error condition.
For (n,k) codes, there are 2n-k possible distinct parity bit combinations.
Therefore, we can distinguish at most that many error conditions. We
therefore arrive at the constraint
Taking the log (to base 2) of both sides, we can see that the number of parity
bits must grow at least logarithmically with the number of message bits
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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43. Linear Block Codes-Parity-check Codes
Codes are based on the notion of parity.
The parity of a binary word is said to be even when the word
contains an even number of 1s and odd parity when it has
odd number of 1s.
A group of n-bits codewords are constructed from a group
of n-1 message bits.
One check bit is added to the n-1 message bits such that all
the codewords have the same parity
When the received codeword has different parity, we know
that an error has occurred
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44. Linear Block Codes-Parity-check Codes
Advantages of Parity check codes- its simplicity and low
overhead.
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45. Linear Block Codes-Parity-check Codes
Example : n=3 and even parity
The binary message are 00,01,10,11
The check bit is added such that all the code words have even
parity
So, the resulting code words are 000,011,101 and 110
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46 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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46. Linear Block Codes-Parity-check Codes
A simple parity-check code is a single-bit error-detecting
code in which n = k + 1 with dmin = 2.
Single Parity check has
Code Rate R = k/n = k/(k+1)
Error detecting capability = 1
Error correcting capability = 0
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47 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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47. Linear Block Codes-Parity-check Codes
Encoder and decoder for simple parity-check code
syndrome bit helps the receiver diagnose the ―illness‖ (errors) in the received data
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48. Linear Block Codes-Parity-check Codes
Example
Let us look at some transmission scenarios. Assume the sender sends
the dataword 1011. The codeword created from this dataword is 10111,
which is sent to the receiver. We examine five senarios:
1. No error occurs; the received codeword is 10111. The syndrome is 0.
The dataword 1011 is created.
2. One single-bit (error changes a1 ). The received codeword is 10011.
The syndrome is 1. No dataword is created.
3. One single-bit ( error changes r0 ). The received codeword is 10110.
The syndrome is 1. No dataword is created.
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49. Linear Block Codes-Parity-check Codes
Example-Continued
4. Two bits ( An error changes r0 and a second error changes a3). The
received codeword is 00110. The syndrome is 0. The dataword 0011 is
created at the receiver. Note that here the dataword is wrongly created
due to the syndrome value.
5. Three bits—a3, a2, and a1—are changed by errors. The received
codeword is 01011. The syndrome is 1. The dataword is not created. This
shows that the simple parity check, guaranteed to detect one single error,
can also find any odd number of errors.
Therefore,
A simple parity-check code can detect an odd number of errors.
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50 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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50. Linear Block Codes-Parity-check Codes (2-D)
In Two-dimensional parity-check code, the data code is organized in a
table (rows and columns) form.
The data to be sent are arranged in rows.
For each row and each column, 1 parity-check bit is calculated.
The whole table is then sent to the receiver, which finds the syndrome for each
row and each column.
The two-dimensional parity check can detect up to three errors that occur
anywhere in the table.
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51. Linear Block Codes-Parity-check Codes (2-D)
Two-dimensional parity-check code
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52. Linear Block Codes-Systematic Block Codes
In (n,k) block codes each sequence of k information bits is mapped into a
sequence of n channel inputs in a fixed way regardless of previous
information bits.
The formed code family should be selected such that the code minimum
distance is as large as possible -> high error correction or detection
capability
Definition: A systematic block code:
– the first k elements are the same as the message bits
– the following r = n - k bits are the check bits
Therefore, the encoded word is
As partitioned representation
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1 2 1 2
message
check
( .... ... ),
r k
b b b m m m r n k
X
( | )
B
X M
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53. Linear Block Codes-Systematic Block Codes
Given the message vector M, the respective linear, systematic block
code X can be obtained by the matrix multiplication
The matrix G is the generator matrix with the general structure
where Ik is kxk identity matrix and
P is called hamming code (or called parity check matrix), it is a kxr binary
submatrix ultimately determining the generated codes
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54
X MG
( | )
k
G P I
11 12 1
21 22 2
1 2
r
r
k k kr
p p p
p p p
p p p
P
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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54. Linear Block Codes-Systematic Block Codes
For u message vectors M (each consisting of k bits) the respective n-bit block codes
X are therefore determined by
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55. Linear Block Codes-Systematic Block Codes
The check vector B that is appended to the message in the encoded
word is thus determined by the multiplication
The jth element of B on the uth row is therefore encoded by
For the Hamming code (parity matrix), P matrix of k rows consists of
all r-bit words with two or more "1― is arranged in all orders! Hence P
can be (for instance)
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B MP Note: X=(B|M)=MG = M(P|Ik)
Therefore: B = MP
, ,1 1, ,2 2, , , , 1...
u j u j u j u k k j
b m p m p m p j r
1 0 1
1 1 1
1 1 0
0 1 1
P
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
11/24/2022
56. Linear Block Codes-Hamming Code
HAMMING CODES are types of linear block codes of (n, k) with the
following parameters
• Number of parity bits, m=n-k
• Codeword length, n = 2m - 1
• Dataword length, k =n-m= 2m – m -1
• Minimum distance dmin=3,
• m >= 3
i.e. Code with m=2 is Repetition Code.
Therefore, the HAMMING CODE will have this general form of
expression
c(n, k)=(2m - 1, 2m – m -1)
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57. Linear Block Codes-Hamming Code
For each integer m ≥ 2 there is a code with block length n = 2m - 1 and
message length k = 2m− m− 1.
Hence the rate of Hamming codes is R = k / n = 1 − {m / (2m − 1)},
Hamming codes are perfect codes, that is, they achieve the highest
possible rate for codes with their block length and minimum distance
of three.
Hamming Codes were originally designed with dmin =3, so they can be
used for single error correction (SEC) or dual error detection (DED).
Therefore, Hamming codes are distance-3 linear block codes.
The first four Hamming codes, for example, are (3,1), (7,4), (15,11), and
(31,26) codes.
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58. Linear Block Codes-Hamming Code
Drawbacks- it is used for single error correction and up to two errors detection
only.
This is due to the limited redundancy that Hamming codes add to the data, they can only detect and
correct errors when the error rate is low.
Advantages-it is easy and cost effective for single error detection and correction
applications and it is popular in computer memory because in computer memory
(usually RAM) the bit errors are extremely rare and Hamming codes are widely
used.
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59. Linear Block Codes-Hamming Code
Hamming bound
There is an inequality called the Hamming bound, which states that if there is an (n,k)
code with an alphabet of q elements and dmin = 2t + 1 then
For each of the qk codewords there are exactly words that are exactly
distance i from it.
Therefore, the number on the right of the inequality is the total number of words
that are at most a distance of t from a codeword.
Since the total number of words cannot exceed qn , the inequality follows
immediately.
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60. Linear Block Codes-Hamming Bound
For a binary code becomes
Codes that attain equality in the Hamming bound are called perfect codes.
A perfect t –error correcting code has the property that every word in the Hamming
space lies within a distance of t from exactly one codeword.
A Hamming space is usually the set of all 2 N binary strings of length N.
More generally, a Hamming space can be defined over any alphabet (set) Q as the
set of words of a fixed length N with letters from Q.
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61. Linear Block Codes-Hamming Code
Assignment 3- Show How to generate/calculate Hamming
Codes? Develop Algorithm for Hamming Code.
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62. Linear Block Codes-Hamming Code
Example-Generate the Hamming Codes for parity bits m=3;
C(n, k)=(2m - 1, 2m – m -1)=C(7,4)
let’s assume m be the message to be encoded , m=(m0, m 1 ,m2 ,m3) ,
and let x be the corresponding codedword, x=(x0, x 1 ,x2 ,x3 ,x4, x 5 ,x6)
then we know that and
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63
X MG ( | )
k
G P I
k
I
|
P
G
k
k
k
n
k
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
1
1
1
0
0
1
1
)
(
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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63. Linear Block Codes-Hamming Code
for m=(m0, m 1 ,m2 ,m3) , codeword x=(x0, x 1 ,x2 ,x3 ,x4, x 5 ,x6)
becomes
x0= m0 + m2 +m3
x1 =m0 + m1 +m2
x 2=m1 + m2 +m3
x3 = m0
x4 = m1
x 5= m2
x6= m3
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64. Linear Block Codes-Hamming Code
Hamming Codes for C(7,4)
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65. Linear Block Codes-Hamming Code
The structure of the encoder and decoder for a Hamming code C(7,4)
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66. Linear Block Codes-Hamming Code
Generator creates 3 parity-check bit (r0 ,r1 , and r2)
r0 = a2 + a1 + a0 modulo-2
r1 = a3+ a2 + a1 modulo-2
r2 = a1 + a0 + a3 modulo-2
The checker in the decoder creates a 3bit syndrome bit
s0 = b2 + b1 + b0 + q0 modulo-2
s1 = b3 + b2 + b1 + q1 modulo-2
s2 = b1 + b0 + b3 + q2 modulo-2
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67 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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67. Linear Block Codes-Hamming Code
For the Hamming code (parity matrix), P matrix of k rows
consists of all r-bit words with two or more "1― is
arranged in all orders! Hence P can be (for instance)
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1 0 1
1 1 1
1 1 0
0 1 1
P
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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68. Linear Block Codes-Hamming Code
.
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69. Linear Block Codes-Hamming Code-Single Error Correction,
Double Error Detection
Can achieve this by adding an overall parity bit.
If parity checks are correct and overall parity bit are
correct, then no single or double errors occurred.
If overall parity bit is incorrect, then single error has
occurred, can use previous to correct.
If one or more of parity checks incorrect but overall
parity bit is correct, then two errors are detected.
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70. Linear Block Codes-Extended Hamming Code (Reading
Assignment)
Extended Hamming codes
achieve a Hamming distance of four,
allows the decoder to distinguish between when at most one one-bit
error occurs and when any two-bit errors occur.
since it cannot distinguish a double bit error of some codeword
from a single bit error of a different codeword.
Thus, some double-bit errors will be incorrectly decoded as if they
were single bit errors and therefore go undetected, unless no
correction is attempted.
In this sense, extended Hamming codes are single-error correcting
and double-error detecting, abbreviated as SECDED.
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71. Linear Block Codes-Cyclic Codes
Cyclic code is a block code, where the circular shifts of each
codeword gives another word that belongs to the code.
They are error-correcting codes that have algebraic properties that
are convenient for efficient error detection and correction.
Definition:- A code C is cyclic if
C is a linear code;
Any cyclic shift of a codeword is also a codeword,
A cyclic shift of a vector [v0 v1 … vn-2 vn-1] is the vector
[vn-1 v1 … vn-2 ].
Cyclically shifting v, i places to the right is equivalent to
cyclically shifting v, n − i places to the left.
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72. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Polynomial representation of vectors
For every vector v=[v0 v1 … vn-2 vn-1] there is a polynomial
Let v(i) be the vector resulting from i cyclic shifts on v
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73. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Consider vector v(X) andv(1) (X) and using Modulo 2 arithmetic
v(X) andv(i) (X) are related by
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74. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Proof
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75. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Property 1- The nonzero code polynomial of minimum
degree in a linear block code (Cyclic code, C) is unique.
Let be the
nonzero code polynomial of minimum degree in an (n, k)
cyclic code C. Then the constant term g0 must be equal to 1.
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76 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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76. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Property 2- Consider the polynomial
Clearly, they are cyclic shifts of g(x) and hence code
polynomials in C. Since C is linear, a linear combination of
is also a code polynomial
where ui ∈ {0, 1}.
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77. Linear Block Codes-Cyclic Codes-Polynomial
Representation
.
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78. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Let be the
nonzero code polynomial of minimum degree in an (n, k)
cyclic code C.
Property 3- A binary polynomial of degree n-1 or less is a code
polynomial if and only if it is a multiple of g(x).
Proof: Let v(x) be a binary polynomial of degree n − 1 or less. Suppose
that v(x) is a multiple of g(x). Then
Since v(x) is a linear combination of the code polynomials, it
is a code polynomial in C.
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79. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Now let v(x) be a code polynomial in C. Dividing v(x) by g(x), we obtain
Where the degree of b(x) is less than the degree of g(x).
Since v(x) and a(x)g(x) are code polynomials, b(x) is also a code
polynomial.
Suppose b(x) not = 0. Then b(x) is a code polynomial with less degree
than that of g(x). Contradiction.
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80 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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80. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Property 4- The number of binary polynomials of degree n − 1 or less
that are multiples of g(x) is 2n−r.
Property 5- There are total of 2k = 2n−r code polynomials in C, i.e.,
r = n − k.
Property 6- The polynomial g(x) is called the generator polynomial
of the code C. If
The degree of g(x) is equal to the number of parity-check digits of the code.
The generator polynomial g(x) of an (n, k) cyclic code is a factor of xn + 1.
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81 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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81. Linear Block Codes-Cyclic Codes-Polynomial
Representation
Property 7- If g(x) is a polynomial of degree n − k and is a factor of xn + 1, then g(x)
generates an (n, k) cyclic code.
v(x) is a polynomial of degree n − 1 or less and is a multiple of g(x).
There are a total of 2k such polynomial and they form an (n, k) linear code.
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82 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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82. Linear Block Codes-Cyclic Codes-Systematic
Encoding of Cyclic Codes
Since both xv(x) and xn + 1 are divisible by g(x), v(1)(x) must be divisible by g(x).
Hence, v(1)(x) is a code polynomial and the code generated by g(x) is a cyclic code.
Systematic Encoding of Cyclic Codes
Suppose we have the message u = (u0, u1, . . . , uk−1) to be encoded, Then
Since the degree of g(x) is n − k, the degree of b(x) must be n − k − 1 or less. Then
is a multiple of g(x) and therefore it is a code polynomial.
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83 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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83. Linear Block Codes-Cyclic Codes-Systematic
Encoding of Cyclic Codes
Then, the coded polynomial can be written as follows
Therefore, a systematic encoding of the message can be obtained as follows
First- Divide xn-ku(x) by g(x) to obtain remainder b(x), and then
The code polynomial is given by b(x) + xn-ku(x)
Given message bits, (mk-1…m1m0 ), the code is generated simply as:
In other words, C(x) can be considered as the product of m(x) and g(x).
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84. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
Shift Register Circuit
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85. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
If the initial state polynomial is zero and the input is a sequence of bits am-1, am-2, …. a1, a0, the
final state polynomial is
For systematic encoding we need Xn-ku(X) mod g(X) which corresponds to input bit sequence
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86 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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86. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
Is there a way to avoid the delay of n - k clock ticks?
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87. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
If the initial state polynomial is zero and the input is a sequence of bits am-1, am-2, …. A1, a0, the
final state polynomial is
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88. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
Turn on the gate. Shift the message bits uk-1, uk-2, …, u0 into the circuit and channel
simultaneously. Only Output1 is fed to the channel.
Turn off the gate and shift the contents of the shift register into the channel. Only Output2 is
fed to the channel.
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89 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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89. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
Encoding circuit for an (n, k) cyclic code with generator polynomial
g(X) = 1 + g1X + g2X2 + · · · + gn−k−1Xn−k−1 + Xn−k
The operation of the encoding circuit is described as follows:
1) Initially, the gate is turned on. The, k information digits, message polynomial u(X) = u0+u1X+
・・・+uk−1Xk−1 is fed to the circuit as well as transmitted into the channel. Feeding the k
information digits into the circuit is equivalent to pre-multiplying u(X) by Xn−k. When all k
information digits are shifted into the circuit, the (n − k) digits in the register form the
remainder.
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90 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
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90. Linear Block Codes-Cyclic Codes-Shift Register
Circuit
Encoding circuit for an (n, k) cyclic code with generator polynomial
g(X) = 1 + g1X + g2X2 + · · · + gn−k−1Xn−k−1 + Xn−k
2) The gate is then turned off, since the register now contains the desired (n − k) parity
check digits.
3) Selector is changed to the left position to send parity check digits into the channel. These
(n−k) parity check digits along with k information digits form the cyclic codeword in
systematic form.
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91. Linear Block Codes-Cyclic Codes-Error Detection
Errors are detected when the received vector is not a codeword
For linear block codes, r is a codeword iff rHT = 0
s = rHT is called the syndrome vector
For cyclic codes, the received polynomial r(X) is a code polynomial iff
r(X) mod g(X) = 0
s(X) = r(X) mod g(X) is called the syndrome polynomial, or
r(X) = a(x) g(X) + s(X) , n-k cofficient of s(X) makes the syndrome
The following circuit computes the syndrome polynomial
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92. Linear Block Codes-Cyclic Codes-Error Detection
Property-10- Let s(x) be the syndrome of a received polynomial r(x).
Then the remainder s(1)(x) resulting from dividing xs(x) by the
generator polynomial g(x) is the syndrome of r(1)(x), which is a cyclic
shift of r(x).
Property-11-The remainder s(i)(x) resulting from dividing xis(x) by the
generator polynomial g(x) is the syndrome of r(i)(x), which is the ith
cyclic shift of r(x).
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93. Linear Block Codes-Cyclic Codes
Example
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94. Linear Block Codes-Cyclic Codes-Error Detection
Example
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95. Linear Block Codes-Cyclic Codes-Error Detection
.
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96. Linear Block Codes-Cyclic Codes-Error Detection
.
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97. Linear Block Codes-Cyclic Codes-Error Detection
.
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98. Linear Block Codes-Cyclic Codes-Error Detection
Decoding of Cyclic Codes
Decoding of linear codes consists of three steps:
1) Syndrome computation;
2) association of the syndrome to an error pattern;
3) error correction.
The cyclic structure of a cyclic code allows us to decode a received
vector r(x) in serial manner.
The decoding circuit checks whether the syndrome s(x) corresponds
to a correctable error pattern e(x) with an error at the highest-order
position xn−1 (i.e., en−1 = 1).
ERROR
CONTROL
CODING
99 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
11/24/2022
99. Linear Block Codes-Cyclic Codes-Error Detection
If s(x) does not correspond to an error pattern with en−1 = 1,
the received polynomial and the syndrome register are cyclically
shifted once simultaneously.
By doing this, we have r(1)(x) and s(1)(x).
The second digit rn−2 of r(x) becomes the first digit of r(1)(x).
The same decoding processes.
If the syndrome s(x) of r(x) does correspond to an error pattern with
an error at the location xn−1, the first received digit rn−1 is an
erroneous digit and it must be corrected by taking the sum rn−1 ⊕
en−1.
ERROR
CONTROL
CODING
100 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
11/24/2022
100. Linear Block Codes-Cyclic Codes-Error Detection
This correction results in a modified received polynomial, denoted by
r1(x) = r0 + r1x + ・ ・ ・ + rn−2xn−2 + (rn−1 ⊕ en−1)xn−1.
The effect of the error digit en−1 on the syndrome can be achieved by
adding the syndrome of e(x) = xn−1 to s(x).
The syndrome s(1)
1 of r(1)
1 (x) is the remainder resulting from dividing
x[s(x) + xn−1] by the generator polynomial g(x).
ERROR
CONTROL
CODING
101 HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
11/24/2022
101. Performance Analysis of Linear Block Codes: The Repetition Code,Parity-
check Codes, Systematic Block Codes, Hamming Code, Cyclic Codes.
Use MATLAB simulator to show the performance.
Due Date 24/11/2022
102
Assignment 2
HU, Haramaya Institute of Technology, School of Electrical and Computer Engineering
11/24/2022
11/24/2022 ERROR CONTROL CODING