This presentation discusses the support for interrupts in 8051. The interrupt types, interrupts versus polling etc are discussed. The register formats of IE, IP register are discussed. The concept of priority among the interrupts is discussed.
This presentation discusses the support for interrupts in 8051. The interrupt types, interrupts versus polling etc are discussed. The register formats of IE, IP register are discussed. The concept of priority among the interrupts is discussed.
This presentation is about ,
Frame pointers and backtrace structures,
Normal program flow vs. exceptions,
Exceptions vs. interrupts,
Software Interrupts,
What is an SWI?,
What happens on an SWI?,
Vectoring SWIs,
What happens on SWI completion?,
What do SWIs do?,
A Complete SWI Handler,
A C_SWI_Handler (written in C),
Loading the Software Interrupt Vector Table,
interrupt is a concept of solution of better cpu utilization. when the more routine is happening inside the processor then how it should technically share the resource without interruption.
Attendance plays a major role in educational institutions. The most common
means of taking attendance during the exam is by passing attendance sheet with each
student and roll numbers of students or asking the students to manually sign the
attendance sheet, which is passed around during the Exam. The process of manually
taking and maintaining the attendance records becomes highly cumbersome.
In the World of Technology, Biometrics plays an effective role in identifying
Human beings. Through this project, you will develop a unique system that can identify
students for attendance purpose using their fingerprints. In this project, we are going to
design a Fingerprint Sensor Based Biometric Exam Attendance System using ESP8266.
Simply we will be interfacing fingerprint sensor with ESP8266, OLED Display to design
the desired project. In this project, we used the fingerprint Module and ESP8266 to take
and keep attendance data and records. Biometric Attendance systems are commonly used
systems to mark the presence in offices and schools.
This project has a wide application in school, college where marking of
attendance is required accurately with time. By using the fingerprint sensor, the system
will become more secure for the users. You will need an ESP8266 board for interfacing
microcontroller with the Finger Print Scanner R307. So with the help of Finger Print
Scanner R307, we will store the finger prints of all the students and once they are stored,
the Fingerprint Scanner will compare the present finger print on the scanner and
previously stored finger prints. If any finger print is matched, the microcontroller will
print the concern data stored for the particular finger print on the OLED Display. In
addition to this, we have inbuilt Wi-Fi module, to upload the data into remote cloud, so as
to access the entire unit from the sole system of it from anywhere in the world.
Fingerprint Based Examination Attendance SystemVrushabhDhote2
Introducing a revolutionary solution, the "Fingerprint-Based Examination Attendance
System," redefines attendance management for academic exams. By using advanced biometric
technology, this system ensures precise and secure attendance, eliminating the risks of proxy
attendance. Students only need to authenticate their identity through a quick and seamless
fingerprint scan and Easily fetch Students profile that matches to the Registered Fingerprint
Databases.
Educational institutions can smoothly Utilize their Academic tasks, Its user-friendly
interface reduces the administrative burden of paperwork and manual record-keeping. Time Saving
in Exams verifications and uphold academic trust, all while creating a seamless experience for both
students and staff, This System easier for students to attend exams to verify their identity. This can
help to reduce stress and anxiety to improve student satisfaction toward attendance, also promoting
efficiency and accuracy.
Enhanced Accuracy, Efficiency, Avoid proxy, User-Friendly, Paperless Work, Time
Saving, Future-Proof, Real-time Updates, Portable, Academic Integrity: Upholds the trust of exams
by preventing fraudulent attendance practices.
This presentation is about ,
Frame pointers and backtrace structures,
Normal program flow vs. exceptions,
Exceptions vs. interrupts,
Software Interrupts,
What is an SWI?,
What happens on an SWI?,
Vectoring SWIs,
What happens on SWI completion?,
What do SWIs do?,
A Complete SWI Handler,
A C_SWI_Handler (written in C),
Loading the Software Interrupt Vector Table,
interrupt is a concept of solution of better cpu utilization. when the more routine is happening inside the processor then how it should technically share the resource without interruption.
Attendance plays a major role in educational institutions. The most common
means of taking attendance during the exam is by passing attendance sheet with each
student and roll numbers of students or asking the students to manually sign the
attendance sheet, which is passed around during the Exam. The process of manually
taking and maintaining the attendance records becomes highly cumbersome.
In the World of Technology, Biometrics plays an effective role in identifying
Human beings. Through this project, you will develop a unique system that can identify
students for attendance purpose using their fingerprints. In this project, we are going to
design a Fingerprint Sensor Based Biometric Exam Attendance System using ESP8266.
Simply we will be interfacing fingerprint sensor with ESP8266, OLED Display to design
the desired project. In this project, we used the fingerprint Module and ESP8266 to take
and keep attendance data and records. Biometric Attendance systems are commonly used
systems to mark the presence in offices and schools.
This project has a wide application in school, college where marking of
attendance is required accurately with time. By using the fingerprint sensor, the system
will become more secure for the users. You will need an ESP8266 board for interfacing
microcontroller with the Finger Print Scanner R307. So with the help of Finger Print
Scanner R307, we will store the finger prints of all the students and once they are stored,
the Fingerprint Scanner will compare the present finger print on the scanner and
previously stored finger prints. If any finger print is matched, the microcontroller will
print the concern data stored for the particular finger print on the OLED Display. In
addition to this, we have inbuilt Wi-Fi module, to upload the data into remote cloud, so as
to access the entire unit from the sole system of it from anywhere in the world.
Fingerprint Based Examination Attendance SystemVrushabhDhote2
Introducing a revolutionary solution, the "Fingerprint-Based Examination Attendance
System," redefines attendance management for academic exams. By using advanced biometric
technology, this system ensures precise and secure attendance, eliminating the risks of proxy
attendance. Students only need to authenticate their identity through a quick and seamless
fingerprint scan and Easily fetch Students profile that matches to the Registered Fingerprint
Databases.
Educational institutions can smoothly Utilize their Academic tasks, Its user-friendly
interface reduces the administrative burden of paperwork and manual record-keeping. Time Saving
in Exams verifications and uphold academic trust, all while creating a seamless experience for both
students and staff, This System easier for students to attend exams to verify their identity. This can
help to reduce stress and anxiety to improve student satisfaction toward attendance, also promoting
efficiency and accuracy.
Enhanced Accuracy, Efficiency, Avoid proxy, User-Friendly, Paperless Work, Time
Saving, Future-Proof, Real-time Updates, Portable, Academic Integrity: Upholds the trust of exams
by preventing fraudulent attendance practices.
Problems of Academic staff and Students Attendance
Result in inaccuracies and security risks like proxy attendance.
Manual processes burden institutions with administrative tasks and paperwork.
Attendance Marking Taken on Paper
Records on Paper
Time Consuming
Examiner gets problem while getting attendance
Need for an Efficient and Secure Solution:
Demand for a system that prevents proxy attendance and reduces admin workload.
Accurate attendance records.
Paperless workflow
Less Time to mark Attendance
Advanced Biometric Technology as a Solution:
Uses biometrics to authenticate students seamlessly.
Ensures precise attendance records and eliminates proxy attendance.
Promotes a relaxed exam environment, enhancing overall experience.
Focus on Fingerprint Technology: The title aligns with the core concept by emphasizing the utilization of advanced biometric technology (fingerprint scans) as a key feature of the attendance system.
Enhanced Accuracy and Future-Proof: The title indirectly supports the content's focus on enhanced accuracy and the system's ability to adapt to future advancements, as suggested by the "future-proof" aspect.
Precise and Secure Attendance: The content emphasizes the system's ability to ensure accurate and secure attendance verification, directly connecting to the title's mention of "precise and secure attendance."
Stress Reduction and Student Satisfaction: The title corresponds to the content's mention of stress reduction, improved student satisfaction, and efficiency enhancement, all of which contribute to the positive impact of the system.
Seamless Identity Authentication: Enable students to authenticate their identities through a quick and seamless fingerprint scan, connecting their profiles with registered fingerprint databases.
Enhance Educational Efficiency: Enable educational institutions to effectively manage their academic tasks by reducing administrative burdens related to paperwork and manual record-keeping.
Save Time in Verification: Streamline the process of attendance verification during exams, saving time for both students and administrative staff.
Improve Student Experience: Create a user-friendly system that reduces stress and anxiety among students by simplifying attendance verification, ultimately enhancing student satisfaction.
Future-Proof and Real-Time Updates: Develop a system that is adaptable to future technological advancements and capable of providing real-time updates for attendance records.
Here are some advantages of a fingerprint-based exam attendance system:
Accuracy: Fingerprint recognition is highly accurate and difficult to fake, reducing the risk of attendance fraud.
Non-intrusive: It is a non-invasive method that does not require students to carry cards or remember PINs.
Time Efficiency: The process of capturing and verifying attendance is quick, saving time for both instructors and students.
Security: Fingerprint data is unique to each individual and is typically enc
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Water billing management system project report.pdfKamal Acharya
Our project entitled “Water Billing Management System” aims is to generate Water bill with all the charges and penalty. Manual system that is employed is extremely laborious and quite inadequate. It only makes the process more difficult and hard.
The aim of our project is to develop a system that is meant to partially computerize the work performed in the Water Board like generating monthly Water bill, record of consuming unit of water, store record of the customer and previous unpaid record.
We used HTML/PHP as front end and MYSQL as back end for developing our project. HTML is primarily a visual design environment. We can create a android application by designing the form and that make up the user interface. Adding android application code to the form and the objects such as buttons and text boxes on them and adding any required support code in additional modular.
MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software. It is a stable ,reliable and the powerful solution with the advanced features and advantages which are as follows: Data Security.MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
2. Interrupts , IRQs , ISRs
• Interrupt : “An interrupt is a signal sent to the CPU which indicates
that a system event has a occurred which needs immediate
attention“.
• Interrupt ReQuest (IRQ) can be thought of as a special request to
the CPU to execute a function(small piece of code) when an
interrupt occurs.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
interrupt occurs.
• ISR : This function or ‘small piece of code’ is technically called an
‘Interrupt Service Routine‘ or ‘ISR‘.
• So when an IRQ arrives to the CPU , it stops executing the code
current code and start executing the ISR. After the ISR execution
has finished the CPU gets back to where it had stopped.
3. How We classify them ?
We Classify them as 2 types :
• Fast IRQs or FIQs
• Normal IRQs or IRQs which can be further
classified as :
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
– Vectored IRQ
– Non-Vectored IRQ.
FIQ
Normal IRQ
Vectored IRQ
Non Vectored IRQ
Interrupts
4. Types of Interrupts in LPC2148
Interrupts are Handled by Vectored Interrupt Controller(VIC)
Types of Interrupts in LPC2148
• Fast Interrupt Request i.e FIQ : which has highest priority
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• Fast Interrupt Request i.e FIQ : which has highest priority
• Vectored Interrupt Request i.e Vectored IRQ : which has
‘middle’ or priority between FIQ and Non-Vectored IRQ.
• Non-Vectored IRQ : which has the lowest priority.
5. What does Vectored mean ?
• ‘Vectored‘ means that the CPU is aware of the address of
the ISR when the interrupt occurs
• Non-Vectored means that CPU doesn’t know the address
of the ISR (nor) the source of the IRQ when the interrupt
occurs.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• For Non – Vectored interrupts , CPU needs to be supplied
by the ISR address.
• For the Vectored interrupts , the System internally
maintains a table called IVT or Interrupt Vector Table which
contains the information about Interrupts sources and their
corresponding ISR address.
6. How Non-Vectored Interrupts are
handled?
• Non-Vectored ISRs doesn’t point to a unique ISR
• The CPU needs to be supplied with the address of the
‘default’ or a ‘common’ ISR that needs to be executed
when the interrupt occurs.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
when the interrupt occurs.
• In LPC2148 this is facilitated by a register called
‘VICDefVectAddr‘.
• The user must assign the address of the default ISR to
this register for handling Non-Vectored IRQs.
7. In a Nut Shell
• Vectored IRQ(VIRQ) has dedicated IRQ service
routine for each interrupt source
• Non-Vectored IRQ(NVIRQ) has the same IRQ
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• Non-Vectored IRQ(NVIRQ) has the same IRQ
service routine for all Non-Vectored
Interrupts.
8. How Many Possible Interrupt Sources are there ?
• There are 22 Interrupt Sources in LPC2148
• But there are only 16 Slots in in the Vectored
Interrupt Controller (VIC)
0 to 15.
• These 22 possible sources have to be shared by using
Slots 0 to 15 of VIC
• Slot 0
Highest Priority
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
Slot 0 Highest Priority
• Slot 15
Lowest Priority
9. SFRs Involved
• VICIntSelect (R/W) 0 = IRQ, 1 = FIQ
• VICIntEnable (R/W) Enable Selective Interrupt Source
• VICIntEnClr (R/W) Disable Selective Interrupt Source
• VICIRQStatus (R) to know the status of enabled interrupt
• VICFIQStatus (R) to know the status of enabled FIQ
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• VICFIQStatus (R) to know the status of enabled FIQ
• VICSoftInt to trigger a software interrupt
• VICSoftIntClear to clear software interrupt
• VICVectCntl0 to VICVectCntl15 Assign interrupt source
• VICVectAddr0 to VICVectAddr15 Assign interrupt address
• VICVectAddr Holds the address of currently active interrupt
• VICDefVectAddr Holds the addressof Non-Vectored ISR
10. VICIntSelect (R/W)
• This register is used to select an interrupt as IRQ or as
FIQ.
• Writing a 0 at a given bit location will make the
corresponding interrupt as IRQ
• Writing a 1 will make it FIQ.
• For e.g if you make Bit 4 as 0 then the corresponding
interrupt source i.e TIMER0 will be IRQ else if you make
Bit 4 as 1 it will be FIQ instead.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
Bit 4 as 1 it will be FIQ instead.
• By default all interrupts are selected as IRQ. Note that
here IRQ applies for both Vectored and Non-Vectored
IRQs.
11. VICIntEnable (R/W)
• This is used to enable interrupts.
• Writing a 1 at a given bit location will make
the corresponding interrupt Enabled.
• If this register is read then 1′s will indicated
enabled interrupts and 0′s as disabled
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
enabled interrupts and 0′s as disabled
interrupts.
• Writing 0′s has no effect.
12. VICIntEnClr (R/W)
• This register is used to disable interrupts.
• This is similar to VICIntEnable expect writing a
1 here will disabled the corresponding
Interrupt.
• This has an effect on VICIntEnable since
writing at bit given location will clear the
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
writing at bit given location will clear the
corresponding bit in the VICIntEnable Register.
• Writing 0′s has no effect
13. VICIRQStatus (R)
• This register is used for reading the current
status of the enabled IRQ interrupts.
• If a bit location is read as 1 then it means that
the corresponding interrupt is enabled and
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
the corresponding interrupt is enabled and
active.
14. VICFIQStatus (R)
• This register is used for reading the current
status of the enabled FIQ interrupts.
• If a bit location is read as 1 then it means that
the corresponding interrupt is enabled and
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
the corresponding interrupt is enabled and
active.
15. VICSoftInt
• This register is used to generate interrupts
using software i.e manually generating
interrupts using code
• If you write a 1 at any bit location then the
correspoding interrupt is triggered i.e. it forces
the interrupt to occur.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
the interrupt to occur.
• Writing 0 here has no effect.
16. VICSoftIntClear
• This register is used to clear the interrupt
request that was triggered(forced) using
VICSoftInt.
• Writing a 1 will release(or clear) the forcing of
the corresponding interrupt.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
17. VICVectCntl0 to VICVectCntl15
• These are the Vector Control registers.
• These are used to assign a particular interrupt source
to a particular slot.
• As mentioned before slot 0 i.e VICVectCntl0 has highest
priority and VICVectCntl15 has the lowest.
• Each of this registers can be divided into 3 parts : {Bit0
to bit4} , {Bit 5} , {and rest of the bits}.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
to bit4} , {Bit 5} , {and rest of the bits}.
• The first 5 bits i.e Bit 0 to Bit 4 contain the number of
the interrupt request which is assigned to this slot. The
interrupt source numbers are given in the table below :
• The 5th bit is used to enable the vectored IRQ slot by
writing a 1 31 . . . 6 EN N4 N3 N2 N1 N0
18. Important Note
• Note that if the vectored IRQ slot is disabled it will not disable
the interrupt but will change the corresponding interrupt to
Non-Vectored IRQ.
• Enabling the slot here means that it can generate the address
of the ‘dedicated Interrupt handling function (ISR)’
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• Disabling it will generate the address of the ‘common/default
Interrupt handling function (ISR)’ which is for Non-Vectored
ISR.
• In simple words if the slot is enabled it points to ‘specific and
dedicated interrupt handling function’ and if its disable it will
point to the ‘default function’.
19. VICVectAddr0 to VICVectAddr15
(16 registers in all)
• For Vectored IRQs these register store the
address of the function that must be called
when an interrupt occurs.
• Note – If you assign slot 3 for TIMER0 IRQ then
care must be taken that you assign the
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
care must be taken that you assign the
address of the interrupt function to
corresponding address register .. i.e
VICVectAddr3 in this example.
20. VICVectAddr
• This must not be confused with the above set of
16 VICVecAddrX registers.
• When an interrupt is Triggered this register holds
the address of the associated ISR i.e the one
which is currently active.
• Writing a value i.e dummy write to this register
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• Writing a value i.e dummy write to this register
indicates to the VIC that current Interrupt has
finished execution.
• The only place we’ll use this register .. is at
the end of the ISR to signal end of ISR execution.
21. VICDefVectAddr
• This register stores the address of the
“default/common” ISR that must be called
when a Non-Vectored IRQ occurs.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
22. How to Write an ISR
Method – 1
__irq void myISR (void)
{
...
}
Method – 2
void myISR (void) __irq
{
...
}
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
For 8051
void myISR (void) interrupt 1
{
...
}
23. A Simple 3 Step Process to Enable a
Vectored IRQ
• Step – 1 : Enable the IRQ by setting the
appropriate bit of VICIntEnable to ’1′.
• Step-2 : Identify the interrupt source number
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
• Step-2 : Identify the interrupt source number
and assign it to VICVectCntlX.
• Step-3 : Assign the address of the related ISR
to VICVectAddrX.
24. Example – Enabling Timer0 Interrupt
• First we need to enable the TIMER0 IRQ itself!
Hence , from Table we get the bit number
to Enable TIMER0 Interrupt which is Bit number
4. Hence we must make bit 4 in VICIntEnable to
’1′.
• Next , from Table we get the interrupt source
number for TIMER0 which is decimal 4 and OR it
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
number for TIMER0 which is decimal 4 and OR it
with (15) [i.e 5th bit=1 which enables the slot]
and assign it to VICVectCntlX.
• Next assign the address of the related ISR to
VICVectAddrX.
25. Template Code
VICIntEnable |= (1Y) ;
VICVectCntlX = (15) | Y ;
VICVectAddrX = (unsigned) myISR;
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
26. Assigning TIMER0 Interrupt to Slot0
VICIntEnable |= (14) ; // Enable TIMER0 IRQ
VICVectCntl0 = (15) | 4 ; //5th bit must 1 to
enable the slot
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
enable the slot
VICVectAddr0 = (unsigned) myISR;
//Vectored-IRQ for TIMER0 has been configured
27. ISR
• First when we have only one ‘internal’ source of interrupt in
TIMER0 i.e an MR0 match event which raises an IRQ.
__irq void myISR(void)
{
long int regVal;
regVal = T0IR; // read the current value in T0's Interrupt
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
regVal = T0IR; // read the current value in T0's Interrupt
Register
//... MR0 match event has occured .. do something here
T0IR = regval; // write back to clear the interrupt flag
VICVectAddr = 0x0; // The ISR has finished!
}
28. Important Note
• Each Peripheral in lpc2148 has only 1 IRQ associated with it.
• But inside each device there may be different sources which can raise
an interrupt
• Like the TIMER0 peripheral has 4 match + 4 capture registers and any
one or more of them can be configured to trigger an interrupt.
• Hence such devices have a dedicated interrupt register which contains
a flag bit for each of these source(For Timer block its ‘T0IR‘).
• So , when the ISR is called first we need to identify the actual source of
the interrupt using the Interrupt Register and then proceed
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
the interrupt using the Interrupt Register and then proceed
accordingly.
• Also just before , when the main ISR code is finished we also need to
acknowledge or signal that the ISR has finished executing for the
current IRQ which triggered it.
• This is done by clearing the flag(i.e the particular bit) in the device’s
interrupt register and then by writing a zero to VICVectAddr register
which signifies that interrupt has ISR has finished execution
successfully.
35. Problem-1
• Design a LPC2148 based system to perform
the following tasks.
• Task1 Blink an LED at P1.31 using software
delay.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
delay.
• Task2 Generate a square wave at 1KHz @
P1.25 using Timer0 Match Interrupt
37. void initInterrupt(void)
{
VICVectCntl0 = (0x01 5) | 4 ;
//(i.e bit5 = 1) - to enable Vectored
IRQ slot
VICVectAddr0 = (unsigned) T0ISR;
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
VICVectAddr0 = (unsigned) T0ISR;
//Pointer Interrupt Function (ISR)
VICIntEnable = 0x01 4; //Enable
timer0 int
}
38. void initTimer0(void)
{
T0PR = 60-1;
// Pclk = 60MHz, ft = 1MHz ,
// Div = 60x10^6/1x10^6 = 60
T0CTCR = 0x00; // Configure as Timer
T0TCR = 0x02; // Clear TC and PC
T0MR0 = 500-1; // 500us
Method -1
Reset Timer after Match
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
T0MR0 = 500-1; // 500us
T0MCR |= 0x03 ; // Reset after Match
//Set bit0 Bit1 to High which is
//Interrupt on MR0, RESET ON MR0
T0TCR = 0x01; // Enable TC
}
39. void T0ISR(void) __irq
{
long int temp;
temp = T0IR ;
if (temp 0x01) // MR0 Interrupt
{
Squarewave = ~( Squarewave);
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
Squarewave = ~( Squarewave);
writepin(25, Squarewave);
}
T0IR = temp; // Clear T0IR
VICVectAddr = 0x00; // Dummy Write
}
40. void initTimer0(void)
{
T0PR = 60-1;
// Pclk = 60MHz, ft = 1MHz ,
// Div = 60x10^6/1x10^6 = 60
T0CTCR = 0x00; // Configure as Timer
T0TCR = 0x02; // Clear TC and PC
T0MR0 = 500-1; // 500us
Method -2
Don’t Reset Timer after Match
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
T0MR0 = 500-1; // 500us
T0MCR |= 0x01 ; //No Reset.
//Set bit0 Bit1 to High which is
//Interrupt on MR0,
T0TCR = 0x01; // Enable TC
}
41. void T0ISR(void) __irq
{
long int temp;
temp = T0IR ;
if (temp 0x01) // MR0 Interrupt
{
T0MR0 = T0MR0 + 500;// Increment!
Squarewave = ~( Squarewave);
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
Squarewave = ~( Squarewave);
writepin(25, Squarewave);
}
T0IR = temp; // Clear T0IR
VICVectAddr = 0x00; // Dummy Write
}
42. #includelpc214x.h
#include GPIO.h
#include timer.h
#include UART.h
#include timerinterrupt.h
int main(void)
{
initPLL(); // 60 MHz Pclk
initInterrupt();
initTimer0();
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
while(1)
{
writepin(31,1); // Background Task
delay();
writepin(31,0);
delay();
}
}
43. Problem-2
• Design a LPC2148 based system to perform the
following tasks.
• Task1 Blink an LED at P1.31 using software delay.
• Task2 Generate a square wave at 500Hz @ P1.25
using Timer0 Match Interrupt
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
using Timer0 Match Interrupt
• Task3 Generate a square wave at 1KHz @ P1.26
using Timer0 Match Interrupt
• Task4 Generate a square wave at 2KHz @ P1.27
using Timer0 Match Interrupt
• Task5 Generate a square wave at 4KHz @ P1.28
using Timer0 Match Interrupt
49. External Interrupt Mode register
(EXTMODE)
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
50. External Interrupt Polarity register
(EXTPOLAR)
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
51. External Interrupt Flag register
(EXTINT)
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
52. Pin function Select register 1
(PINSEL1)
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
53. Problem-3
• Design a LPC2148 based system to perform
the following tasks.
• Task1 Blink an LED at P1.31 using software
delay.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
delay.
• Task2 Read a switch @ EINT0 and Turn a
Load @ P1.25 when count exceeds 10.
56. void INT0ISR(void) __irq
{
long int temp;
temp = EXTINT ;
if (temp 0x01) // EINT0
{
if (mycount 10)
writepin(25,1); // Load ON
else
{
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
{
mycount ++;
writepin(25,0); // Load OFF
}
}
EXTINT = temp; // clear interrupt
VICVectAddr = 0x00;
}
57. #includelpc214x.h
#include GPIO.h
#include timer.h
#include UART.h
#include extinterrupt.h
int main(void)
{
initPLL(); // 60 MHz Pclk
initInterrupt();
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
while(1)
{
writepin(31,1);
delay();
writepin(31,0);
delay();
}
}
58. Problem-4
• Design a LPC2148 based system to perform
the following tasks.
• Task1 Blink an LED at P1.31 using software
delay.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
delay.
• Task2 Read a switch @ EINT0 and Turn a
Load @ P1.25 when count exceeds 10.
• Task3 Read a switch @ EINT1 and Toggle a
Load @ P1.26
65. Problem-5
• Design a LPC2148 based system to perform the
following tasks.
• Task1 Blink an LED at P1.31 using software delay.
• Task2 Receive commands from PC at 9600 Baud and
control 2 Loads for the following commands.
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
control 2 Loads for the following commands.
• A Load1 ON
• B Load 1 Off
• C Load 2 ON
• D Load 2 OFF
66. Pin Function Select Register 0
(PINSEL0)
01
01
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
67. UART0 Line Control Register
(U0LCR)
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Department of EIE / PEC
68. UART0 Line Status Register (U0LSR)
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Department of EIE / PEC
69. UART0 Line Status Register (U0LSR)
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC
70. UART0 Interrupt Enable Register(U0IER)
Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
Department of EIE / PEC