Indiana Integrated Circuits is commercializing Quilt Packaging technology, which was invented at Notre Dame. Quilt Packaging allows for chips to be directly connected along their edges in a "quilt-like" assembly for improved performance, cost, size and functionality compared to traditional packaging. IIC licenses the Quilt Packaging process, supports early adopters in defense applications, and plans to transition to commercial applications. Quilt Packaging can integrate disparate materials like silicon and gallium arsenide and is implemented using standard fabrication processes.
Implementing the latest embedded component technology from concept-to-manufac...Zuken
This document discusses implementing embedded components in printed circuit boards from concept to manufacturing. It begins with an overview of embedded component technologies and their advantages like increased density and performance. Common challenges are then addressed such as meeting tolerance requirements for formed components and impact on thermal behavior. The document emphasizes the importance of considering manufacturability early in the design process and working closely with manufacturers to define dedicated design rules. It concludes that a true 3D design approach is necessary to effectively implement embedded component technologies.
Direct Bond Interconnect (DBI) Technology as an Alternative to Thermal Compre...Invensas
DBI® is a low temperature hybrid direct bonding technology that allows wafers or die to be bonded with exceptionally fine pitch 3D electrical interconnect.
This document provides an overview of the MIT course 2.830J/6.780J/ESD.63J Control of Manufacturing Processes offered in Spring 2008. The course covers topics related to statistical process control, designed experiments, process optimization, and feedback control. It aims to maximize quality and throughput while improving flexibility and reducing costs. Key concepts discussed include sources of process variation, statistical models, effects models, and techniques for process optimization and control.
Beam Services is a provider of capital equipment and engineering services for the semiconductor industry. It has over 80 years of combined experience in semiconductor services and engineering. Beam Services develops innovative electrostatic substrate handling technology to gently handle thin wafers and complex devices for applications such as lithography, deposition, and packaging. This technology provides a contamination-free solution for handling fragile and non-standard substrates.
Today, plastic packaged integrated circuits are ubiquitous even for high-reliability applications. Reliability testing and standards play a key role in reliability engineering to achieve the necessary reliability performance. Traditional stress-based standards are easy to use but often over- or under-stress units and don’t focus on key vulnerabilities, particularly moisture-related ones. Knowledge-based standards have evolved to fix this, but rely on knowledge of mechanisms, control of board manufacturing conditions, and understanding and specifying end use conditions. This motivates a survey of plastic package mechanisms and testing with particular focus on moisture-related mechanisms and testing. The moisture-related examples will cover HAST testing, and the “popcorn” mechanism.
Learning Objectives
1.Understand the philosophy and methods behind reliability testing of ICs as applied to plastic-packaged ICs.
2.Learn the historical development of the JEDEC temperature-humidity-bias (HAST) moisture reliability testing standard.
3.Get a practical overview of key thermal, thermo-mechanical, moisture (chemical), and moisture (“popcorn”) mechanisms.
4.Appreciate how transformation of environmental conditions to conditions at the site of failure in the package is used to “scale” reliability models.
AceCo Precision Manufacturing was founded in 1960 in Boise, Idaho and provides manufacturing solutions across several industries including semiconductor equipment, TFT-LCD, solar equipment, and medical devices. It has three manufacturing facilities and corporate headquarters in Boise. AceCo creates value for clients through a full suite of services including engineering, design, manufacturing, and repair while collaborating closely with clients. It is known for its commitment to quality and has received several customer quality awards.
Workshop - Voorkomen van faling door vibraties - introductie-vis-prosperita-imecSirris
This document provides an overview of the cEDM organization and its mission to support the electronics industry. It discusses cEDM's approach of using quantitative physical modeling and collaboration across the supply chain. The document outlines cEDM's industry partners and multidisciplinary team. It also describes cEDM's VIS-PROSPERITA project which aims to develop design guidelines for electronics realization and integration based on physical modeling. The status of various guidelines related to design-for-manufacturing, integration, and supporting quantification tools are summarized.
Implementing the latest embedded component technology from concept-to-manufac...Zuken
This document discusses implementing embedded components in printed circuit boards from concept to manufacturing. It begins with an overview of embedded component technologies and their advantages like increased density and performance. Common challenges are then addressed such as meeting tolerance requirements for formed components and impact on thermal behavior. The document emphasizes the importance of considering manufacturability early in the design process and working closely with manufacturers to define dedicated design rules. It concludes that a true 3D design approach is necessary to effectively implement embedded component technologies.
Direct Bond Interconnect (DBI) Technology as an Alternative to Thermal Compre...Invensas
DBI® is a low temperature hybrid direct bonding technology that allows wafers or die to be bonded with exceptionally fine pitch 3D electrical interconnect.
This document provides an overview of the MIT course 2.830J/6.780J/ESD.63J Control of Manufacturing Processes offered in Spring 2008. The course covers topics related to statistical process control, designed experiments, process optimization, and feedback control. It aims to maximize quality and throughput while improving flexibility and reducing costs. Key concepts discussed include sources of process variation, statistical models, effects models, and techniques for process optimization and control.
Beam Services is a provider of capital equipment and engineering services for the semiconductor industry. It has over 80 years of combined experience in semiconductor services and engineering. Beam Services develops innovative electrostatic substrate handling technology to gently handle thin wafers and complex devices for applications such as lithography, deposition, and packaging. This technology provides a contamination-free solution for handling fragile and non-standard substrates.
Today, plastic packaged integrated circuits are ubiquitous even for high-reliability applications. Reliability testing and standards play a key role in reliability engineering to achieve the necessary reliability performance. Traditional stress-based standards are easy to use but often over- or under-stress units and don’t focus on key vulnerabilities, particularly moisture-related ones. Knowledge-based standards have evolved to fix this, but rely on knowledge of mechanisms, control of board manufacturing conditions, and understanding and specifying end use conditions. This motivates a survey of plastic package mechanisms and testing with particular focus on moisture-related mechanisms and testing. The moisture-related examples will cover HAST testing, and the “popcorn” mechanism.
Learning Objectives
1.Understand the philosophy and methods behind reliability testing of ICs as applied to plastic-packaged ICs.
2.Learn the historical development of the JEDEC temperature-humidity-bias (HAST) moisture reliability testing standard.
3.Get a practical overview of key thermal, thermo-mechanical, moisture (chemical), and moisture (“popcorn”) mechanisms.
4.Appreciate how transformation of environmental conditions to conditions at the site of failure in the package is used to “scale” reliability models.
AceCo Precision Manufacturing was founded in 1960 in Boise, Idaho and provides manufacturing solutions across several industries including semiconductor equipment, TFT-LCD, solar equipment, and medical devices. It has three manufacturing facilities and corporate headquarters in Boise. AceCo creates value for clients through a full suite of services including engineering, design, manufacturing, and repair while collaborating closely with clients. It is known for its commitment to quality and has received several customer quality awards.
Workshop - Voorkomen van faling door vibraties - introductie-vis-prosperita-imecSirris
This document provides an overview of the cEDM organization and its mission to support the electronics industry. It discusses cEDM's approach of using quantitative physical modeling and collaboration across the supply chain. The document outlines cEDM's industry partners and multidisciplinary team. It also describes cEDM's VIS-PROSPERITA project which aims to develop design guidelines for electronics realization and integration based on physical modeling. The status of various guidelines related to design-for-manufacturing, integration, and supporting quantification tools are summarized.
Petro equipment suppliers association credit suisse presentationgiorgiogarrido6
Credit Suisse provides an overview of the oilfield services industry and investment opportunities. The document discusses the various segments of oilfield services including exploration/seismic, drilling, completion, and production. It analyzes industry trends like increasing use of pressure pumping and hydraulic fracturing. The appendix contains important disclosures for investors.
Cable Solutions and Hydro Solutions provide cables and cable systems for harsh and underwater environments. Some of their offerings include Amercable products, Norwegian and British specification cables, panel wiring, data and fiber optic cables, terminations and assemblies, ROV cables, umbilicals, tow cables, and custom designed composite cables built to specifications. They offer services like project management, material management, pre-terminated cables, repairs, and technical support.
Consult your board manufacturer at the outset of design to identify materials that would provide the optimum balance of price, manufacturability, and performance based on your construction. Find out why by viewing this presentation.
This document discusses Oxford Instruments' nanotechnology tools for synthesizing 2D materials. It summarizes their portfolio including MBE systems for wafer-scale graphene growth, cluster tools for combining growth and analysis, CVD and PECVD tools for applied research and pilot production, and ALD systems for dielectric deposition. Oxford Instruments has experience developing tools to meet emerging industry needs and providing long-term support for customers moving processes from lab to fabrication. Key challenges for 2D materials include scaling production while maintaining quality and reliability.
Metal bonding alternatives to frit and anodic technologies for wlpSUSS MicroTec
* Overview of frit and anodic bond processing
* Mechanics of metal bonding options
* Process requirement comparisons
* Hermetic capabilities
* Equipment requirements for metal bonding
More technical papers on www.suss.com
The RestFS is an experimental project to develop an open-source distributed filesystem for large environments. It is designed to scale up from a single server to thousand of nodes and delivering a high availability storage system with special features for high i/o performance and network optimization for work better in WAN environment. The Restfs is pure-python, but several of the libraries that it depends upon use C extensions (sometimes for speed, sometimes to interface to pre-existing C libraries). The Project is on the beginning stage, with some technology previews released.
Data Analysis for Semiconductor ManufacturingPuwen Ning
This document discusses semiconductor manufacturing and data analysis. It covers the key steps in manufacturing which are silicon, wafer fabrication, chip making, and final product. It also describes the main data sources used like WIP, equipment, and measurements. The goal of data analysis is yield improvement to reduce costs and increase revenue. Low yielding wafers are mapped and analyzed to identify issues.
Flip chip is an advanced packaging technique where bare semiconductor chips are flipped upside down and bonded directly to a printed circuit board using solder bumps. It was introduced by IBM in 1962 as Solid Logic Technology and later converted to Controlled Collapse Chip Connection. Flip chip packaging provides shorter interconnect lengths, lower inductance and higher density interconnects compared to wire bonding. It allows for area array interconnect layouts and has become the standard for high performance integrated circuits. Reliability can be improved through underfilling, which compensates for thermal expansion differences and protects the solder joints.
System on Chip (SoC) integrates processor, memory and other components onto a single chip. Advances in VLSI technology allow millions of transistors to be placed on a single die, enabling entire systems to be implemented as SoCs. This provides benefits like lower cost, power consumption and size compared to discrete components. However, designing highly complex SoCs presents challenges related to design time, verification and complexity. Reusing pre-designed and verified intellectual property (IP) cores is a solution that helps manage this complexity.
This document provides an overview of VLSI (Very Large Scale Integration) and its applications. It discusses the history of integrated circuits from their inception in the late 1940s to today's advanced nanoscale technologies. Key topics covered include Moore's law of transistor scaling, digital circuit design challenges, CMOS fabrication processes, and examples of how VLSI is used in various electronic systems and devices.
Faculty of engineering and life sciences (FELS) of Unisel arranged an industiral visit to MIMOS (Malaysian Institute of Microelectronic Systems) on 10th April 2018 with 40 students from Electrical division. The purpose of visit was to enhance the industry exposure of the pariticpants, get the practical insights into manufacturing and to get aware of the real life situations of semiconduictor manufacturing.
1. The document discusses Custom Interconnect Ltd (CIL), an electronics manufacturing company that specializes in power electronics and has expanded its capabilities for GaN and SiC devices.
2. CIL has been successful in projects like GaNSiC that developed new silver sintering techniques for attaching GaN and SiC dies.
3. CIL continues to work with customers on non-funded power electronics projects and has two new funded projects starting in early 2022.
This document discusses trends in the IC packaging industry and technology. It provides an overview of the market growth in IC packaging units and revenues. Key challenges for the industry are declining ASPs and increasing materials costs. Emerging technologies discussed include wafer-level packaging, 2.5D/3D IC with TSV, and integrated passives. The document outlines SPIL's packaging portfolio and roadmaps for 3D IC and TSV development over the next few years. It also summarizes SPIL's testing and certification capabilities.
The document summarizes the goals and outcomes of the university's last network refresh project from 2012-2017 and outlines plans for an upcoming new network refresh. Key points include: the last refresh addressed aging network switches and wireless access points across campus and residences and upgraded bandwidth capacity; lessons learned were around underestimating wireless needs and change management; the new refresh will focus on lifecycle management, automation, user experience, security, and supporting new technologies over 10 years.
This document provides an introduction to integrated circuits. It discusses the historical development of integrated circuits from transistors to modern chips containing billions of transistors. It explains different types of integrated circuits including SSI, MSI, LSI, VLSI, and ULSI. The document also covers important concepts in digital IC design such as noise margins, propagation delay, power consumption, and design metrics like functionality, cost, reliability, and performance.
The document discusses input/output (I/O) circuits and packaging for integrated circuits. It begins by describing how chips are connected to the outside world via I/O circuits, bonding wires, and packages. It then discusses the main properties and requirements of packages, including electrical characteristics, number of I/O pins, and thermal properties. The document outlines different packaging technologies like wire bonding and flip chip packaging. It also discusses I/O circuit requirements and different types of I/O cells like digital I/O buffers and analog I/O cells. Finally, it briefly introduces system-in-package technologies that integrate multiple silicon chips or dies into a single package using techniques like multi-chip modules, silicon interposers,
3D Embedded Substrate Technologies Increase Density and Performance of Power ...Design World
This webinar discussed significant developments and trends in 3D packaging with a focus on embedded substrate technologies. A technology report commissioned by PSMA found that embedded substrate technology can increase power density by embedding active components and passives directly into substrate layers. The webinar covered various embedded substrate manufacturing technologies from companies like AT&S, TDK, Infineon, and Semikron. It discussed the benefits of embedded substrates including improved performance, reliability, thermal management and reduced size. Standards for embedded components and a variety of embedded passive and active components were also reviewed.
The document discusses memory construction and CMOS fabrication processes. It defines memory as the electronic holding place for data and instructions in a computer. The basic building block of memory is the memory cell, which stores a single bit. It then describes the key steps in CMOS fabrication, including well formation, isolation, transistor making, interconnection, and packaging. The CMOS process involves photolithography, etching, oxidation, implantation and deposition to construct memory cells on a silicon wafer.
Power point presentation on Intergrated Circuits.
A good presentation cover all topics.
For any other type of ppt's or pdf's to be created on demand contact -dhawalm8@gmail.com
mob. no-7023419969
This document provides an agenda and overview for a Tech 2 Tech webinar on network refreshes. The webinar will include presentations on Jisc frameworks, the STFC RAL Data Centre network, and the University of Southampton network. Typical considerations for a network refresh are discussed, such as tender processes, technical capabilities, resilience, and integrating networks with data centers and clouds. Other topics that will be covered include monitoring network performance, IPv6, handling large data transfers, power usage, and sustainability best practices. Presenters will provide real-world examples from their network refreshes.
Petro equipment suppliers association credit suisse presentationgiorgiogarrido6
Credit Suisse provides an overview of the oilfield services industry and investment opportunities. The document discusses the various segments of oilfield services including exploration/seismic, drilling, completion, and production. It analyzes industry trends like increasing use of pressure pumping and hydraulic fracturing. The appendix contains important disclosures for investors.
Cable Solutions and Hydro Solutions provide cables and cable systems for harsh and underwater environments. Some of their offerings include Amercable products, Norwegian and British specification cables, panel wiring, data and fiber optic cables, terminations and assemblies, ROV cables, umbilicals, tow cables, and custom designed composite cables built to specifications. They offer services like project management, material management, pre-terminated cables, repairs, and technical support.
Consult your board manufacturer at the outset of design to identify materials that would provide the optimum balance of price, manufacturability, and performance based on your construction. Find out why by viewing this presentation.
This document discusses Oxford Instruments' nanotechnology tools for synthesizing 2D materials. It summarizes their portfolio including MBE systems for wafer-scale graphene growth, cluster tools for combining growth and analysis, CVD and PECVD tools for applied research and pilot production, and ALD systems for dielectric deposition. Oxford Instruments has experience developing tools to meet emerging industry needs and providing long-term support for customers moving processes from lab to fabrication. Key challenges for 2D materials include scaling production while maintaining quality and reliability.
Metal bonding alternatives to frit and anodic technologies for wlpSUSS MicroTec
* Overview of frit and anodic bond processing
* Mechanics of metal bonding options
* Process requirement comparisons
* Hermetic capabilities
* Equipment requirements for metal bonding
More technical papers on www.suss.com
The RestFS is an experimental project to develop an open-source distributed filesystem for large environments. It is designed to scale up from a single server to thousand of nodes and delivering a high availability storage system with special features for high i/o performance and network optimization for work better in WAN environment. The Restfs is pure-python, but several of the libraries that it depends upon use C extensions (sometimes for speed, sometimes to interface to pre-existing C libraries). The Project is on the beginning stage, with some technology previews released.
Data Analysis for Semiconductor ManufacturingPuwen Ning
This document discusses semiconductor manufacturing and data analysis. It covers the key steps in manufacturing which are silicon, wafer fabrication, chip making, and final product. It also describes the main data sources used like WIP, equipment, and measurements. The goal of data analysis is yield improvement to reduce costs and increase revenue. Low yielding wafers are mapped and analyzed to identify issues.
Flip chip is an advanced packaging technique where bare semiconductor chips are flipped upside down and bonded directly to a printed circuit board using solder bumps. It was introduced by IBM in 1962 as Solid Logic Technology and later converted to Controlled Collapse Chip Connection. Flip chip packaging provides shorter interconnect lengths, lower inductance and higher density interconnects compared to wire bonding. It allows for area array interconnect layouts and has become the standard for high performance integrated circuits. Reliability can be improved through underfilling, which compensates for thermal expansion differences and protects the solder joints.
System on Chip (SoC) integrates processor, memory and other components onto a single chip. Advances in VLSI technology allow millions of transistors to be placed on a single die, enabling entire systems to be implemented as SoCs. This provides benefits like lower cost, power consumption and size compared to discrete components. However, designing highly complex SoCs presents challenges related to design time, verification and complexity. Reusing pre-designed and verified intellectual property (IP) cores is a solution that helps manage this complexity.
This document provides an overview of VLSI (Very Large Scale Integration) and its applications. It discusses the history of integrated circuits from their inception in the late 1940s to today's advanced nanoscale technologies. Key topics covered include Moore's law of transistor scaling, digital circuit design challenges, CMOS fabrication processes, and examples of how VLSI is used in various electronic systems and devices.
Faculty of engineering and life sciences (FELS) of Unisel arranged an industiral visit to MIMOS (Malaysian Institute of Microelectronic Systems) on 10th April 2018 with 40 students from Electrical division. The purpose of visit was to enhance the industry exposure of the pariticpants, get the practical insights into manufacturing and to get aware of the real life situations of semiconduictor manufacturing.
1. The document discusses Custom Interconnect Ltd (CIL), an electronics manufacturing company that specializes in power electronics and has expanded its capabilities for GaN and SiC devices.
2. CIL has been successful in projects like GaNSiC that developed new silver sintering techniques for attaching GaN and SiC dies.
3. CIL continues to work with customers on non-funded power electronics projects and has two new funded projects starting in early 2022.
This document discusses trends in the IC packaging industry and technology. It provides an overview of the market growth in IC packaging units and revenues. Key challenges for the industry are declining ASPs and increasing materials costs. Emerging technologies discussed include wafer-level packaging, 2.5D/3D IC with TSV, and integrated passives. The document outlines SPIL's packaging portfolio and roadmaps for 3D IC and TSV development over the next few years. It also summarizes SPIL's testing and certification capabilities.
The document summarizes the goals and outcomes of the university's last network refresh project from 2012-2017 and outlines plans for an upcoming new network refresh. Key points include: the last refresh addressed aging network switches and wireless access points across campus and residences and upgraded bandwidth capacity; lessons learned were around underestimating wireless needs and change management; the new refresh will focus on lifecycle management, automation, user experience, security, and supporting new technologies over 10 years.
This document provides an introduction to integrated circuits. It discusses the historical development of integrated circuits from transistors to modern chips containing billions of transistors. It explains different types of integrated circuits including SSI, MSI, LSI, VLSI, and ULSI. The document also covers important concepts in digital IC design such as noise margins, propagation delay, power consumption, and design metrics like functionality, cost, reliability, and performance.
The document discusses input/output (I/O) circuits and packaging for integrated circuits. It begins by describing how chips are connected to the outside world via I/O circuits, bonding wires, and packages. It then discusses the main properties and requirements of packages, including electrical characteristics, number of I/O pins, and thermal properties. The document outlines different packaging technologies like wire bonding and flip chip packaging. It also discusses I/O circuit requirements and different types of I/O cells like digital I/O buffers and analog I/O cells. Finally, it briefly introduces system-in-package technologies that integrate multiple silicon chips or dies into a single package using techniques like multi-chip modules, silicon interposers,
3D Embedded Substrate Technologies Increase Density and Performance of Power ...Design World
This webinar discussed significant developments and trends in 3D packaging with a focus on embedded substrate technologies. A technology report commissioned by PSMA found that embedded substrate technology can increase power density by embedding active components and passives directly into substrate layers. The webinar covered various embedded substrate manufacturing technologies from companies like AT&S, TDK, Infineon, and Semikron. It discussed the benefits of embedded substrates including improved performance, reliability, thermal management and reduced size. Standards for embedded components and a variety of embedded passive and active components were also reviewed.
The document discusses memory construction and CMOS fabrication processes. It defines memory as the electronic holding place for data and instructions in a computer. The basic building block of memory is the memory cell, which stores a single bit. It then describes the key steps in CMOS fabrication, including well formation, isolation, transistor making, interconnection, and packaging. The CMOS process involves photolithography, etching, oxidation, implantation and deposition to construct memory cells on a silicon wafer.
Power point presentation on Intergrated Circuits.
A good presentation cover all topics.
For any other type of ppt's or pdf's to be created on demand contact -dhawalm8@gmail.com
mob. no-7023419969
This document provides an agenda and overview for a Tech 2 Tech webinar on network refreshes. The webinar will include presentations on Jisc frameworks, the STFC RAL Data Centre network, and the University of Southampton network. Typical considerations for a network refresh are discussed, such as tender processes, technical capabilities, resilience, and integrating networks with data centers and clouds. Other topics that will be covered include monitoring network performance, IPv6, handling large data transfers, power usage, and sustainability best practices. Presenters will provide real-world examples from their network refreshes.
M-Solv is a company that designs and sells manufacturing equipment combining high-precision motion control with laser patterning, inkjet printing, and spray deposition technologies. They presented on using these technologies for large-area electronics manufacturing. Specifically, they discussed using inkjet printing and laser processing to digitally manufacture capacitive touch sensors and for a new "one step interconnect" process for thin-film photovoltaics that deposits all layers and connections in a single pass, reducing costs. Funding from Innovate UK and the EU is acknowledged.
This document outlines the key concepts and units for the course EC6009 - Advanced Computer Architecture. It covers five main units: (1) fundamentals of computer design, instruction level parallelism, (2) data level parallelism, (3) thread level parallelism, (4) memory and I/O, and (5) performance evaluation. The goals of the course are for students to understand performance of different architectures with respect to various parameters and techniques for improving performance like instruction level parallelism and exploiting data level parallelism.
Linx Consulting provides insights into the electronic materials supply chain and helps clients succeed through experience in industries such as semiconductors, LCDs, packaging, photovoltaics, and nanotechnology. They analyze challenges for the future including 3D packaging, 450mm wafers, new memory technologies, EUV lithography, and changes in the global market drivers as mobile devices surpass desktop and laptop computers. Process complexity is driving higher materials demand growth than wafer start growth, with segments such as photoresist and ancillaries showing over 15% growth.
Linx Consulting provides insights into the electronic materials supply chain and helps clients succeed through experience in industries such as semiconductors, LCDs, packaging, photovoltaics, and nanotechnology. They analyze challenges for the future including 3D packaging, 450mm wafers, new memory technologies, EUV lithography, and changes in the global market drivers as mobile devices surpass desktop and laptop computers. Process complexity is driving higher materials demand growth than wafer start growth, with segments such as photoresist and ancillaries showing stronger increases than overall wafer production.
Summary presentation from a white paper delivered to PCIC Middle East February 2014, introducing engineering design methods for cable transit devices (MCT's), best practices for use of these solutions and engineering work process.
The CMOS VLSI DESIGN PPT had the complete vision on VLSI Design styles in chip fabrication. It can give a good amount of knowledge to the students who needs VLSI Design
Similar to IIC_QuiltPackaging_TechBriefing_February2016 (20)
1. Indiana Integrated Circuits, LLC and
Quilt Packaging® Technology: An Overview
Jason Kulick, President & Co-Founder
jason.kulick@indianaic.com
574-217-4612 (South Bend, IN)
Alan Isaacson, VP Business Development
alan.isaacson@indianaic.com
719-442-0194 (Colorado Springs, CO)
February 2016
2. Indiana Integrated Circuits, LLC (IIC)
Formed to commercialize Quilt Packaging (QP) – a ground
breaking packaging technology invented at Notre Dame.
•Founded by Kulick & Bernstein (2009)
•Main office South Bend, IN at Innovation Park (also CO & NC)
•IIC has experienced steady growth with customers & partners
across multiple industry sectors since early in it’s inception.
•Operations funded directly through revenue growth and
through equity investment (Series A closed late 2015).
•The QP process is commercially available at RTI International.
•Process development for medium volume requirements is
ongoing at Rogue Valley Microdevices in Medford, OR.2
3. IIC Business Model--Licensing
(supported by prototyping)
• IIC partners with
customers to integrate
QP into their systems.
• First-adopters for QP are
DOD high-performance
applications.
• Transition from DOD to
commercial applications
are planned as the
technology matures and
risks are reduced.
3…and more proprietary.
4. Segment Penetration & Selected
Customers / Partners
Microwave & RF
Large Format Array
Power Electronics
MEMs/Internet of Things
Optical Integration
Biomedical/Biosensors
4
Confidential Customer
Confidential Customer
5. Existing Supply Chain—Wafer Processing
• RTI International, Inc.
– ITAR compliant BEOL facility
located in Durham/RTP, NC
– Wafer post-processing for
deep etch, plating, CMP,
singulation
– Si & SiC substrates from
pieces up o 8” wafers
– IIC partner since 2012
– Offering QP MPW service
– Can support up to 100 wafer
starts per month
• Rogue Valley Microdevices, Inc.
– Pure-play MEMS foundry located
in Medford, OR
– Wafer post-processing for thin
film, etching, litho (deep etch
coming)
– Multiple substrates, up to 8”
wafers
– IIC partner since January 2015
(MIG Tech. Pitch win award)
– Can support several hundred
wafer starts per month
5
6. Existing Supply Chain—Assembly
• Automated Tooling Partner:
MRSI Systems, Inc.
– Global supplier of fully-
automated solutions for
assembly of microelectronic
devices
– High precision die attach &
dispensing systems
– Demonstrated automated
Quilt Package assembly on
MRSI 705 system
– Working with since 2012
– Based in Billerica, MA
• North American-based Low
to Medium Volume
Assembler
– Public announcement coming
soon (March 2016)
– Leader in electronics design,
manufacturing and
aftermarket services
– Can support DOD applications
6
7. The Problem:
Existing Microchip Packaging
7
A
B
Electrical Signal
Existing technologies waste:
•Power
•Time
•Money
•Space
Now a system constraint!
ch
ip
packa
ge
PC board
Chip A Chip B
Package Package
“…Overall performance, cost,
size and functionality of a
system will be limited by….the
off-chip interconnects.”
-International Technology Roadmap For Semiconductors
8. 8
Quilt Packaging enables
10x to 100X improvement!
•Power--- 10x lower parasitic losses
•Time---10x faster
•Money---Order of magnitude total
system cost savings
•Space---Dramatic form factor reduction
Quilt Packaging is a patented, direct edge-
to-edge chip interconnect technology that
can be implemented in disparate materials
and technologies.
The Solution:
Quilt Packaging Interconnect Technology
Electrical
Signal
Chip A Chip B
Package
Chip A Chip B
Quilt Packaging
interconnect
Solder
Quilt Packaging enables new
system designs
Quilt Packaged chipsets and interconnects
9. Quilt Packaging (QP) Technology
• Edge-connections joined to
create multi-chip “quilt,”
developed at Notre Dame
• “Monolithic” assemblies
from same or disparate
materials & process
technologies
• Extremely low impedances
• Enables optimization for
cost and functionality
• Industry-standard tools and
fabrication processes
(available in Si at RTI)
9
CHIP 1 CHIP 2
10. QP-Interconnect Structures
• Edge connection
structures called
“nodules”
• Solid metal, typically
Cu, 5-500 um wide,
20-50 um thick
• 10 um pitch possible
• Customizable shapes-
including interlocking-
enables sub-micron
chip alignment
10
14. Why use Quilt Packaging?
• Optimized integration of disparate materials and process
technologies (Si, GaAs, GaN, SiGe, AlN, more)
• Chip partitioning for optimal yield/functionality
• Sub-micron chip-to-chip alignment (FPAs, IRSPs, Optical)
• Better thermal management due to all chips on heatsink
• Reduced power dissipation, die size, design cycle time
• Variety of interconnect geometries & sizes available
simultaneously
• Increased IP flexibility, security & design re-use
• Complementary with existing packaging approaches---can be
combined w/TSV, WB, bumping, etc.
14
15. Quilt Packaging: Processing &
Implementation
• Based on standard
process flows in Si, III-Vs
– Dry etch, plating, CMP,
wafer thinning
• No exotic processes or
materials required
• Demonstrated: Si, GaAs, InP
Etch Nodules Seed & Plate
Interconnect ICP-RIE Streets
Thin & Dice Assembly
16. Quilt Packaging Process
The Quilt Packaging fabrication process is also described in the figure below. To fabricate QP in Si or III-
V substrates, conventional photolithography is used to define the nodule features, which are then
etched to a depth of ~ 25 microns into the wafer using Bosch deep reactive ion etching (for Si) or a
chlorine-based inductively coupled plasma etching (for III-Vs). After the nodules shapes are defined, a
seed layer, Ti/Cu is deposited and the nodules are filled using a Cu electroplating step. Electroplating
overburden is removed with a chemical mechanical polishing (CMP) step. Wafers are singulated by a
combination of deep etching and backside grinding.
QP Fabrication Process (starting at top left and following arrows to
bottom: 1)Front end finished; 2) Nodules etched; 3) Dielectric
insulating layer; 4) Nodule metallization; 5) Metal 1 deposition; 6)
Singulation etch; 7) separation grinding; 8) Die connection; 9) Final
quilt assembly.
17. Quilt Packaging Process
Quilt Packaging can be implemented at the IDM, Foundry or OSAT
In order to get the full benefit from Quilt Packaging, chips and packaging are designed with
QP in mind from the beginning. QP can be implemented in a variety of substrates, including
Si, GaAs, InP, SiGe, SiC, GaN, and more. Wafer fabrication on the front end is exactly like that
of any other process, and QP is implemented during the Back-End-of-Line processing.
1. Finish Front-End-Of-Line
The Quilt Packaging fabrication process begins as the front end work finishes, very similar to
a "via-middle" approach for fabricating TSVs. Quilt Packaging can occur at the foundry or at
an assembly house capable of the etching, metallization, and other Back-End-of-Line
process (just like via-middle).
2. Nodule Definition Etch, Metallization & CMP
An etch mask is used to define the nodule features, and the "mold" for nodules is created
by removing material through an etch process. Following nodule definition etch, the wafer
undergoes seed layer deposition, electroplating build-up of the nodule metal, and CMP
removal of the overburden.
18. Quilt Packaging Process
3. Finish Global Chip Interconnects
After the CMP step, the wafer now has metal nodules "embedded" in what would usually
be the dicing streets and the wafer looks otherwise as it did prior to nodule definition
etch. At this point the rest of the back end of line is completed, with signal connections
made across the chip and to nodules as needed.
4. Singulate QP Die, Assemble & Reflow
Once global interconnects are made, a final separation etch mask is used to protect the
die surface during the separation step. Wafer singulation is implemented by dry etching or
a combination of dry etching and grinding or sawing. Chips are then assembled into
"Quilts" and reflowed to form one large "Metachip." This quilt is then treated as if it were
one large chip, and ends up in a package, on a board, on ceramic, etc.
19. Quilt Packaging: Electrical Performance
(Performs as if it were an on-chip interconnect)
• Homogeneous (e.g. Si-Si, GaAs-GaAs) and
heterogeneous (Si-GaAs, Si-InP)
interconnects demonstrated
• Excellent RF/millimeter-wave, high-speed
digital performance:
– S21 ≤ 0.75 dB to 220 GHz
– 43 Gb/s eyes with no impairment
• Ultra-low parasitics
• Dense I/O pitch at chip edge (10 um pitch)
• Extremely high current-handling capacity
> 10 A through 30 µm x 20 µm nodules
without damage
Si-GaAs CPW
20. Quilt Packaging: Mechanical Performance
• Interconnects are
mechanically robust
• Interconnected modules can
be handled like larger chip
(e.g. pick & place, etc.)
• Preliminary pull testing
requires large force before
failure; resistant to thermal
shock
Pull test:
50 µm x 20 µm nodules,
40 nodules per edge
Four die connected;
mechanical handling as if
single chip
21. Preliminary Thermal Cycling Results
• Probe testing & optical
inspection before and after
cycling
• Cycled from -40 C to 125 C
• 22 minute dwell times
• Removed for inspection at
350 cycles & 1,000 cycles.
• No failures
• No increases in resistance
or opens
• No visible damage/defects
21
22. Summary of Quilt Packaging Advantages
• Optimized heterogeneous integration
of disparate materials and/or process
technologies (Si, GaAs, GaN, SiGe, SiC &
more
• Chip partitioning for optimal
yield/functionality
• Scalable technology using standard
fabrication & assembly tools
• Design re-use & reduced design cycle
time and reduced time-to-market
• Provides precise mechanical alignment
accuracy, better than 1 um
• Significant size, weight, power, and
cost reductions for systems
• Compatible with other packaging
approaches: flip-chip, TSV, wirebonds
Three ICs connected
by Quilt Packaging
Cutaway view
of
nodules
24. Silicon QP Microwave Performance
Less than 0.1 dB insertion loss from 50 MHz past 100 GHz, with no
resonances. Recent results under 1 dB at 220 GHz
24
(D. Kopp, C. Liang, J. Kulick, M. Khan, G. H. Bernstein, and P. Fay, “Quilt Packaging of RF Systems with Ultrawide
Bandwidth,” Proc. of the IMAPS - Advanced Technology Workshop on RF and Microwave Packaging, San Diego (2009).
25. Silicon QP Eye diagrams
• Measurement of 12 Gb/s eye
pattern (Anritsu MP1763B)
– Horiz. 100 mV/div
– Vert. 20 ps/div
• Data stream: 231-1 pseudo-
random bit sequence
• Nearly ideal interconnect
performance; indistinguishable
from PG.
• Error-free operation
– SNR (Q) = 12.9 for pattern
generator alone, 12.4 after
chip-to-chip interconnect
Raw pattern
generator
50 µm
GSG eye
25
(D. Kopp, C. Liang, J. Kulick, M. Khan, G. H. Bernstein, and P. Fay, “Quilt Packaging of RF Systems with Ultrawide
Bandwidth,” Proc. of the IMAPS - Advanced Technology Workshop on RF and Microwave Packaging, San Diego (2009).
26. Silicon QP Time-Domain Performance
• Single-ended GSG CPW
configuration
• Picosecond Pulse Labs
4022 TDR pulse
enhancement module:
< 9 ps risetime
• Total delay including
probe pads, launcher: 7
ps (820 μm length)
• Delay due to QP
nodules: 2.7 ps
100 µm nodule compared with
pads/launcher, GSG
26
(D. Kopp, C. Liang, J. Kulick, M. Khan, G. H. Bernstein, and P. Fay,
“Quilt Packaging of RF Systems with Ultrawide
Bandwidth,” Proc. of the IMAPS - Advanced Technology
Workshop on RF and Microwave Packaging, San Diego (2009).
27. GaAs Measurement Data Sample
Raw S-parameters De-embedded S-parameters
*Less than 3 dB (2.2 dB) insertion loss at 220 GHz
(Fay, P.; Kopp, D. ; Lu, T. ;, Neal, D. ; Bernstein, G.H., ; Kulick, J.M.; “Ultrawide Bandwidth Chip-to-Chip Interconnects For III-V
MMICs,” IEEE Microwave and Wireless Component Letters,, Volume: PP, Issue 99, 2013
29. Large Format Array Example: 2x2 Quilted
Chipset for IRSP/FPA
• Large format arrays suffer
from poorly- yielding ROIC
and RIIC chip sizes (Si CMOS)
• Tiling approach requires
small chip gap (<10 um) and
sub-micron alignment
accuracy
• QP delivers gap, alignment,
and dense edge I/O, enabling
tiling of arbitrarily large
arrays
• This approach can be utilized
for other larger Si chips
29
30. Optical Integration Example:
Multispectral Laser Concept
30
III-V Laser Diode Chips
(10’s of lasers per chip)
Silicon Waveguide Combiner
w/single facet for emission
QP interconnects for sub-micron
Chip-to-chip waveguide alignment
accuracy
31. Optoelectronics and Photonics Example
• Precision integration:
– High-density, low-loss silica planar
optical waveguides
– High-performance III-V emitters &
detectors
• Sub-wavelength passive chip-to-
chip alignment
• Experimentally demonstrated:
– Lateral alignment: << 1 µm
– Axial positional tolerance: < 5 µm
– Insertion loss ≤ 2 dB in mid-IR
(Courtesy S. Howard & S. Hoffman, Notre Dame)
32. Optoelectronic Sources & Sensors Example:
Lab-On-A-Chip
• Tunable, high-power THz sources
– Independently optimize mid-IR pump lasers and
difference frequency generator (DFG) nonlinearity
– High power (~mW), room-temperature, CW
• Sensitive and specific stand-off
material detection
• Integration with microfluidics for on-chip liquid,
gas analysis and sensing
Optical QP
A.G. Davies et al., Materials Today 11, 18 (2008).
Frequency (THz)
Absorption(103cm-1)
(Courtesy S. Howard & S. Hoffman, Notre Dame)
33. Millimeter-Wave/THz Electronics Example
• Ultra-wideband, low-loss interconnects with mechanical self-alignment
– Integration for advanced functionality; quartz filters, feeds with InP electronics
– Loss reduction enables lower power budget
– Compact “single block” realization, no change to active device technologies
• mm-Wave/THz sensing and imaging, communication
• Example: 340 GHz transceiver: Around 10”x10” to a 1” single block; applicable
to many mm-wave/THz systems
Conventional Split-Block
QP Single-Block Integration
QP interconnects
(Courtesy P.Fay & L. Liu, Notre Dame)