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Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35
www.ijera.com 30 | P a g e
A New Model of H-Bridge Multilevel Inverter for Reduced
Harmonics Distortion
Vipul Kumar*, Dr. Arvind Mittal**, Mr. Abid Husain Saifee***
*Assistant Professor and Head of EE Department, Uttaranchal University, Dehradun-248001 (India),
**Associate Professor, Energy Department, NIT-Bhopal-462051(India),
***
Principal, All Saint College, Bhopal-462003 (India) +919826740386,
Abstract
In this paper the cascaded H Bridge multilevel inverter (CHB-MLI) is discussed and mainly focuses on the
modified H-Bridge multilevel inverter in which the number of power devices is reduced. The analysis of five-
level, seven-level and nine-level MLI are also done. The various control strategies are also introduced which
effectively reduce the harmonics. The THD of five-level multilevel inverter is reduced to 16.91% which is much
lower than the nine-level MLI.
Keywords: Multilevel inverter, five-level, seven-level, nine-level MLI, THD, control strategies.
I. Introduction
The preliminary studies on multilevel inverter
(MLI) have been discussed using three level inverter
that has been proposed by Nabae [15]. Multilevel
inverters have more attention in the field of high
voltage and medium power applications due to their
many advantages, such as low voltage stress on
power semiconductor devices, low harmonic
distortions, good electromagnetic compatibility,
reduced switching losses and improved reliability on
fault tolerance. Comparing with the two or three level
inverter multilevel inverter has the more harmonics
reduction capability. Therefore, the multilevel
inverters also have lower dv/dt ratios to prevent
induction or discharge failures on the loads. The
multilevel inverter topologies are classified into three
categories up to now: Diode Clamped inverters,
Flying Capacitor inverters, and Cascaded H Bridge
inverters. Among three types of multi-level topology
the cascaded H Bridge inverter has the least
component for a given number of levels. A new
model of H-Bridge MLI is introduced in which the
number of switches is lower than the cascaded H-
Bridge multilevel inverter which helps to reduce the
overall cost of the inverter and circuit become less
complicated.
This paper presents the model of H-Bridge for
different levels and analysis of the THD with the
resistive load with hardware waveform results. The
THD of five-level MLI can be reduced up to 16.91%
by using the various control strategies which is
introduced in this paper.
II. General Cascaded H-Bridge Five-
level MLI
This is the topology in which the two H-Bridges
is connected in series by which the five-level output
voltage is obtained. The circuit diagram of the three-
phase CHB-MLI is shown in the fig 1 and the
corresponding output waveform is shown in fig 2.
Vdc
M1
M3 M4
M2
Vdc
M3'
M2'
Vdc
M5
M7 M8
M6
Vdc
M6'
Vdc
M9
Vdc
M10
M11
M12
M12'
M10'
M11'
M9'
M8'M7'
M5'
M4'
M1'
Va Vb Vc
Fig.1 Three-phase five-level CHB-MLI
Fig. 2 Output Waveform of three-phase five-level
CHB-MLI
The voltage THD with resistive load is calculated as
0.3192.
III. New model of H-Bridge MLI
In this proposed topology the CHB-MLI is
modified with the objective to reduce the numbers of
RESEARCH ARTICLE OPEN ACCESS
Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35
www.ijera.com 31 | P a g e
power devices. As the number of power devices is
reduced the cost of the circuit also reduces. As the
levels of MLI are increased then in modified circuit
only two power devices are to be added for
increasing one level. Similarly for increasing the two-
level just add four power devices. For example for
five-level MLI six power devices are required, where
as for seven-level eight power devices are required
and for nine-level ten power devices are required.
The power consumption of the circuit is also reduced
and circuit become simple and less complicated as
compared as conventional topology. The power
circuit of five-level modified H-Bridge MLI is shown
in fig 3.
Vdc
M 1
M3 M 4
M 2
Vdc
M 7
M 9
M10
M 8
Vdc
M12
Vdc
M13 M 14
M 15
M 16
M 11
Va Vb Vc
Vdc
M18M17
Vdc
M 6
M5
Fig. 3 Three-phase five level circuit of modified H-
Bridge MLI
The percentage reduction in switching devices is
shown in table 1.
Inverter type 5-level 7-level 9-level
Cascaded H-
Bridge
8 12 16
Proposed
topology
6 8 10
% Reduction 25% 33.33% 37.5%
Table1. The percentage reduction in switching
devices
i. Five-level of new model H-Bridge MLI
In the five-level H-Bridge MLI six power
devices are required for single phase and eighteen
power devices for three-phase power circuit. The
circuit diagram of single phase five-level modified H-
Bridge MLI is shown in the fig 4.
M1
M2
M5
M6
M3
M4
Vdc
Vdc
LOAD
Fig. 4 Single phase five-level H-Bridge MLI
The voltage output waveforms are shown in fig
5. The control strategy which is used in this topology
is termed as δ-δ-2δ-δ-δ where the value of δ is
30°.The circuit diagram of three-phase five-level new
model H-Bridge MLI is shown in fig 6 and voltage
output waveforms are shown in fig 7 respectively.
Fig. 5 Output voltage waveform for single phase five-
level new model H-Bridge MLI
Fig. 6 Three-phase circuit for five-level
New model H-Bridge MLI
Fig. 7 The output voltage waveforms for three-phase
five-level new model H-Bridge MLI
ii. Seven-level of new model H Bridge MLI
Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35
www.ijera.com 32 | P a g e
For the seven-level new model H-Bridge MLI
eight power devices are required and for three-phase
twenty four power devices are required. The power
circuit is shown in fig 8. The three-phase power
circuit is same as the power circuit of three-phase
five-level modified H-Bridge MLI and the voltage
output waveforms are shown in fig 9.
M1
M2
M5
M6
M3
M4
Vdc
Vdc
Vdc
M7
M8
LOAD
Fig. 8 Single phase seven-level H-Bridge MLI
Fig. 9 The output voltage waveforms for three-phase
seven-level new model H-Bridge MLI
iii. Nine-level modified H Bridge MLI
Similarly to the five-level and seven-level new
model of H-bridge MLI the nine–level has required
ten power devices for single-phase and thirty power
devices for three-phase. The power circuit of nine-
level modified H-Bridge MLI is shown in fig10. And
the power circuit for three-phase is same as the five-
level modified H Bridge MLI. The output voltage
waveforms of nine-level three-phase modified H-
Bridge MLI are shown in fig 11.
M1
M2
M5
M6
M3
M4
Vdc
Vdc
Vdc
M7
M8
Vdc
M10M9
LOAD
Fig. 10 Single phase nine-level H-Bridge MLI
Fig. 11 The output waveform three-phase nine-level
modified H Bridge MLI
IV. THD of new model H-Bridge MLI
The THD of five-level, seven-level and nine-
level of mew model H-Bridge MLI is shown in the
table 2.
Levels THD
Five-level 0.3192
Seven-level 0.2546
Nine-level 0.2203
Table 2. Comparing THD of new model H-Bridge
MLI for different levels.
V. Control strategies
By properly controlling the switching of the
MOSFETs, the THD of output voltage waveforms
can be reduced to substantial level. The various
control schemes for five-level new model H-Bridge
MLI are discussed in detail below.
Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35
www.ijera.com 33 | P a g e
i. δ-δ-4δ-δ-δ scheme
In this scheme the switching of the MOSFETs is
done in the pattern δ-δ-4δ-δ-δ, where the value of δ is
22.5°. The output voltage waveform for three-phase
is shown in fig 12. It is observed that the THD is
reduced to 0.286.
Fig 12.Output waveform of δ-δ-4δ-δ-δ
ii. δ-2δ-4δ-2δ-δscheme
In this scheme the switching of MOSFETs has
changed as δ-2δ-4δ- 2δ- δ, where the value of δ is
18°. It is analyzed the THD is reduced 0.2049. The
output waveform of three-phase is shown in fig 13.
Fig 13.Output waveform of δ-2δ-4δ-2δ-δ
iii. δ-2δ-6δ-2δ-δscheme
In this scheme the switching of the MOSFETs is
done in the pattern of δ-2δ-6δ-2δ-δ, where the value
of δ is 15°. The output voltage waveform for three-
phase is shown in fig 14. It is observed that the THD
is reduced to 0.1697.
Fig 14.Output waveform of δ-2δ-6δ-2δ-δ
The comparison of THD of five-level modified
H-Bridge MLI for various control strategies is shown
in table 3.
Schemes THD
δ, δ, 2δ 0.3192
δ, δ, 4δ 0.2086
δ, 2δ, 4δ 0.2049
δ, 2δ, 6δ 0.1697
Table 3 Comparison of THD for various control
strategies
VI. Hardware results
The hardware result of a new model H-Bridge
five-level Multilevel inverter is shown in the
following figures.
The waveforms of the switch M1
The waveform of switch M2
The waveform of switch M3
The waveform of switch M4 is
Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35
www.ijera.com 34 | P a g e
The waveform of switch M5 is
The waveform of switch M6
And the complete waveform of five-level MLI is
VII. Conclusions
In this paper modified H-Bridge MLI topology
has been presented using reduced number of devices
as compared to conventional H-Bridge cascaded
MLI. The reduction in the number of devices goes on
increasing as we increase the number of levels. A
suitable and simple control strategy is proposed for
three phase five-level MLI in which the THD is
reduced to 16.97%, which is much lower than
conventional nine-level MLI.
VIII. Acknowledgements
The author is very grateful and would
acknowledge the energy department, Maulana Azad
National Institute of Technology for providing all
possible facilities for carrying out this research paper.
References
Journal Papers:
[1] Colak _I, Kabalci E. The control methods of
multi-level inverter. TUBAV Sci2009;1:45–
54.
[2] Leon JI, Portillo R, Vazquez S, Padilla JJ,
Franquelo LG, Carrasco JM. Simple unified
approach to develop a time-domain
modulation strategy for singlephase
multilevel converters. IEEE Trans Ind
Electron 2008;55:3239–48.
[3] Nandhakumar S, Jeevananthan S. Inverted
sine carrier pulse width modulation for
fundamental fortification in DC–AC
converters. In: Proceedings of IEEE power
electronics and drive-systems; 2007. p.
1028–34.
[4] Kuhn H, Ruger NE, Mertens A. Control
strategy for multilevel inverter with non-
ideal dc sources. In: Proceedings of IEEE
power electronics specialists conf. Orlando
(USA); 2007.
[5] Zhong Du1, Leon M. Tolbert2,3, John N.
Chiasson2, and Burak Özpineci3,” A
Cascade Multilevel Inverter Using a Single
DC Source”, Applied Power Electronics
Conference and Exposition, 2006. APEC
'06. Twenty-First Annual IEEE,PP-426-430.
[6] Gupta AK, Khambadkone AM. A space
vector pwm scheme to reduce common mode
voltage for a cascaded multilevel inverter.
In: Proceedings of 37th IEEE PESC „06,
Jeju (Korea); 2006.
[7] IAEA, "Model for Analysis of Energy
Demand" (MAED-2), User Guide,
International Atomic Energy Agency,
Vienna, Austria, 2006.
[8] Juan Quintanilla Martinez, "Energy and
Emissions Long Term Outlook - A Detailed
Simulation of Energy Supply-Demand,"
Mexican-US Economic and Environmental
Modeling Workshop, Mexico City, July 11-
12, 2005.
[9] Rodriguez J, Hammond P, Pont J, Musalem
R. Method to increase reliability in 5-level
inverter. Electron Lett 2003;39:1343–5.
[10] Chiasson J, Tolbert L, McKenzie K, Du Z.
Real-time computer control of a multilevel
converter using the mathematical theory of
Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35
www.ijera.com 35 | P a g e
resultants. Elsevier Math Comp Simul
2003;63:197–208.
[11] ETSAP, "MARKAL", “Energy Technology
Systems Analysis Programme,” Energy
Research Centre of the Netherlands (ECN),
Petten, The Netherlands, December 2001.
[12] Rashid MH. Power electronics handbook.
Florida, USA: Academic Press; 2001.
[13] Lin BR. A novel control scheme for the
multilevel rectifier/inverter. Taylor and
Francis Int J Electron 2001;88:225–47.
[14] Kincic S, Chandra A, Babic S. Multilevel
inverter and its limitations when applied as
statcom. In: Proceedings of 9th
Mediterranean conference on control and
automation, Dubrovnik (Croatia); 2001.
[15] Nabae A, Takashi I, Akagi H. A new
neutral-point clamped PWM inverter.
IEEETransIndAppl 1981; 17:518–23.

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A New Model of H-Bridge Multilevel Inverter for Reduced Harmonics Distortion

  • 1. Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35 www.ijera.com 30 | P a g e A New Model of H-Bridge Multilevel Inverter for Reduced Harmonics Distortion Vipul Kumar*, Dr. Arvind Mittal**, Mr. Abid Husain Saifee*** *Assistant Professor and Head of EE Department, Uttaranchal University, Dehradun-248001 (India), **Associate Professor, Energy Department, NIT-Bhopal-462051(India), *** Principal, All Saint College, Bhopal-462003 (India) +919826740386, Abstract In this paper the cascaded H Bridge multilevel inverter (CHB-MLI) is discussed and mainly focuses on the modified H-Bridge multilevel inverter in which the number of power devices is reduced. The analysis of five- level, seven-level and nine-level MLI are also done. The various control strategies are also introduced which effectively reduce the harmonics. The THD of five-level multilevel inverter is reduced to 16.91% which is much lower than the nine-level MLI. Keywords: Multilevel inverter, five-level, seven-level, nine-level MLI, THD, control strategies. I. Introduction The preliminary studies on multilevel inverter (MLI) have been discussed using three level inverter that has been proposed by Nabae [15]. Multilevel inverters have more attention in the field of high voltage and medium power applications due to their many advantages, such as low voltage stress on power semiconductor devices, low harmonic distortions, good electromagnetic compatibility, reduced switching losses and improved reliability on fault tolerance. Comparing with the two or three level inverter multilevel inverter has the more harmonics reduction capability. Therefore, the multilevel inverters also have lower dv/dt ratios to prevent induction or discharge failures on the loads. The multilevel inverter topologies are classified into three categories up to now: Diode Clamped inverters, Flying Capacitor inverters, and Cascaded H Bridge inverters. Among three types of multi-level topology the cascaded H Bridge inverter has the least component for a given number of levels. A new model of H-Bridge MLI is introduced in which the number of switches is lower than the cascaded H- Bridge multilevel inverter which helps to reduce the overall cost of the inverter and circuit become less complicated. This paper presents the model of H-Bridge for different levels and analysis of the THD with the resistive load with hardware waveform results. The THD of five-level MLI can be reduced up to 16.91% by using the various control strategies which is introduced in this paper. II. General Cascaded H-Bridge Five- level MLI This is the topology in which the two H-Bridges is connected in series by which the five-level output voltage is obtained. The circuit diagram of the three- phase CHB-MLI is shown in the fig 1 and the corresponding output waveform is shown in fig 2. Vdc M1 M3 M4 M2 Vdc M3' M2' Vdc M5 M7 M8 M6 Vdc M6' Vdc M9 Vdc M10 M11 M12 M12' M10' M11' M9' M8'M7' M5' M4' M1' Va Vb Vc Fig.1 Three-phase five-level CHB-MLI Fig. 2 Output Waveform of three-phase five-level CHB-MLI The voltage THD with resistive load is calculated as 0.3192. III. New model of H-Bridge MLI In this proposed topology the CHB-MLI is modified with the objective to reduce the numbers of RESEARCH ARTICLE OPEN ACCESS
  • 2. Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35 www.ijera.com 31 | P a g e power devices. As the number of power devices is reduced the cost of the circuit also reduces. As the levels of MLI are increased then in modified circuit only two power devices are to be added for increasing one level. Similarly for increasing the two- level just add four power devices. For example for five-level MLI six power devices are required, where as for seven-level eight power devices are required and for nine-level ten power devices are required. The power consumption of the circuit is also reduced and circuit become simple and less complicated as compared as conventional topology. The power circuit of five-level modified H-Bridge MLI is shown in fig 3. Vdc M 1 M3 M 4 M 2 Vdc M 7 M 9 M10 M 8 Vdc M12 Vdc M13 M 14 M 15 M 16 M 11 Va Vb Vc Vdc M18M17 Vdc M 6 M5 Fig. 3 Three-phase five level circuit of modified H- Bridge MLI The percentage reduction in switching devices is shown in table 1. Inverter type 5-level 7-level 9-level Cascaded H- Bridge 8 12 16 Proposed topology 6 8 10 % Reduction 25% 33.33% 37.5% Table1. The percentage reduction in switching devices i. Five-level of new model H-Bridge MLI In the five-level H-Bridge MLI six power devices are required for single phase and eighteen power devices for three-phase power circuit. The circuit diagram of single phase five-level modified H- Bridge MLI is shown in the fig 4. M1 M2 M5 M6 M3 M4 Vdc Vdc LOAD Fig. 4 Single phase five-level H-Bridge MLI The voltage output waveforms are shown in fig 5. The control strategy which is used in this topology is termed as δ-δ-2δ-δ-δ where the value of δ is 30°.The circuit diagram of three-phase five-level new model H-Bridge MLI is shown in fig 6 and voltage output waveforms are shown in fig 7 respectively. Fig. 5 Output voltage waveform for single phase five- level new model H-Bridge MLI Fig. 6 Three-phase circuit for five-level New model H-Bridge MLI Fig. 7 The output voltage waveforms for three-phase five-level new model H-Bridge MLI ii. Seven-level of new model H Bridge MLI
  • 3. Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35 www.ijera.com 32 | P a g e For the seven-level new model H-Bridge MLI eight power devices are required and for three-phase twenty four power devices are required. The power circuit is shown in fig 8. The three-phase power circuit is same as the power circuit of three-phase five-level modified H-Bridge MLI and the voltage output waveforms are shown in fig 9. M1 M2 M5 M6 M3 M4 Vdc Vdc Vdc M7 M8 LOAD Fig. 8 Single phase seven-level H-Bridge MLI Fig. 9 The output voltage waveforms for three-phase seven-level new model H-Bridge MLI iii. Nine-level modified H Bridge MLI Similarly to the five-level and seven-level new model of H-bridge MLI the nine–level has required ten power devices for single-phase and thirty power devices for three-phase. The power circuit of nine- level modified H-Bridge MLI is shown in fig10. And the power circuit for three-phase is same as the five- level modified H Bridge MLI. The output voltage waveforms of nine-level three-phase modified H- Bridge MLI are shown in fig 11. M1 M2 M5 M6 M3 M4 Vdc Vdc Vdc M7 M8 Vdc M10M9 LOAD Fig. 10 Single phase nine-level H-Bridge MLI Fig. 11 The output waveform three-phase nine-level modified H Bridge MLI IV. THD of new model H-Bridge MLI The THD of five-level, seven-level and nine- level of mew model H-Bridge MLI is shown in the table 2. Levels THD Five-level 0.3192 Seven-level 0.2546 Nine-level 0.2203 Table 2. Comparing THD of new model H-Bridge MLI for different levels. V. Control strategies By properly controlling the switching of the MOSFETs, the THD of output voltage waveforms can be reduced to substantial level. The various control schemes for five-level new model H-Bridge MLI are discussed in detail below.
  • 4. Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35 www.ijera.com 33 | P a g e i. δ-δ-4δ-δ-δ scheme In this scheme the switching of the MOSFETs is done in the pattern δ-δ-4δ-δ-δ, where the value of δ is 22.5°. The output voltage waveform for three-phase is shown in fig 12. It is observed that the THD is reduced to 0.286. Fig 12.Output waveform of δ-δ-4δ-δ-δ ii. δ-2δ-4δ-2δ-δscheme In this scheme the switching of MOSFETs has changed as δ-2δ-4δ- 2δ- δ, where the value of δ is 18°. It is analyzed the THD is reduced 0.2049. The output waveform of three-phase is shown in fig 13. Fig 13.Output waveform of δ-2δ-4δ-2δ-δ iii. δ-2δ-6δ-2δ-δscheme In this scheme the switching of the MOSFETs is done in the pattern of δ-2δ-6δ-2δ-δ, where the value of δ is 15°. The output voltage waveform for three- phase is shown in fig 14. It is observed that the THD is reduced to 0.1697. Fig 14.Output waveform of δ-2δ-6δ-2δ-δ The comparison of THD of five-level modified H-Bridge MLI for various control strategies is shown in table 3. Schemes THD δ, δ, 2δ 0.3192 δ, δ, 4δ 0.2086 δ, 2δ, 4δ 0.2049 δ, 2δ, 6δ 0.1697 Table 3 Comparison of THD for various control strategies VI. Hardware results The hardware result of a new model H-Bridge five-level Multilevel inverter is shown in the following figures. The waveforms of the switch M1 The waveform of switch M2 The waveform of switch M3 The waveform of switch M4 is
  • 5. Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35 www.ijera.com 34 | P a g e The waveform of switch M5 is The waveform of switch M6 And the complete waveform of five-level MLI is VII. Conclusions In this paper modified H-Bridge MLI topology has been presented using reduced number of devices as compared to conventional H-Bridge cascaded MLI. The reduction in the number of devices goes on increasing as we increase the number of levels. A suitable and simple control strategy is proposed for three phase five-level MLI in which the THD is reduced to 16.97%, which is much lower than conventional nine-level MLI. VIII. Acknowledgements The author is very grateful and would acknowledge the energy department, Maulana Azad National Institute of Technology for providing all possible facilities for carrying out this research paper. References Journal Papers: [1] Colak _I, Kabalci E. The control methods of multi-level inverter. TUBAV Sci2009;1:45– 54. [2] Leon JI, Portillo R, Vazquez S, Padilla JJ, Franquelo LG, Carrasco JM. Simple unified approach to develop a time-domain modulation strategy for singlephase multilevel converters. IEEE Trans Ind Electron 2008;55:3239–48. [3] Nandhakumar S, Jeevananthan S. Inverted sine carrier pulse width modulation for fundamental fortification in DC–AC converters. In: Proceedings of IEEE power electronics and drive-systems; 2007. p. 1028–34. [4] Kuhn H, Ruger NE, Mertens A. Control strategy for multilevel inverter with non- ideal dc sources. In: Proceedings of IEEE power electronics specialists conf. Orlando (USA); 2007. [5] Zhong Du1, Leon M. Tolbert2,3, John N. Chiasson2, and Burak Özpineci3,” A Cascade Multilevel Inverter Using a Single DC Source”, Applied Power Electronics Conference and Exposition, 2006. APEC '06. Twenty-First Annual IEEE,PP-426-430. [6] Gupta AK, Khambadkone AM. A space vector pwm scheme to reduce common mode voltage for a cascaded multilevel inverter. In: Proceedings of 37th IEEE PESC „06, Jeju (Korea); 2006. [7] IAEA, "Model for Analysis of Energy Demand" (MAED-2), User Guide, International Atomic Energy Agency, Vienna, Austria, 2006. [8] Juan Quintanilla Martinez, "Energy and Emissions Long Term Outlook - A Detailed Simulation of Energy Supply-Demand," Mexican-US Economic and Environmental Modeling Workshop, Mexico City, July 11- 12, 2005. [9] Rodriguez J, Hammond P, Pont J, Musalem R. Method to increase reliability in 5-level inverter. Electron Lett 2003;39:1343–5. [10] Chiasson J, Tolbert L, McKenzie K, Du Z. Real-time computer control of a multilevel converter using the mathematical theory of
  • 6. Vipul Kumar Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 11( Part 5), December 2014, pp.30-35 www.ijera.com 35 | P a g e resultants. Elsevier Math Comp Simul 2003;63:197–208. [11] ETSAP, "MARKAL", “Energy Technology Systems Analysis Programme,” Energy Research Centre of the Netherlands (ECN), Petten, The Netherlands, December 2001. [12] Rashid MH. Power electronics handbook. Florida, USA: Academic Press; 2001. [13] Lin BR. A novel control scheme for the multilevel rectifier/inverter. Taylor and Francis Int J Electron 2001;88:225–47. [14] Kincic S, Chandra A, Babic S. Multilevel inverter and its limitations when applied as statcom. In: Proceedings of 9th Mediterranean conference on control and automation, Dubrovnik (Croatia); 2001. [15] Nabae A, Takashi I, Akagi H. A new neutral-point clamped PWM inverter. IEEETransIndAppl 1981; 17:518–23.