On the Impact of Timer Resolution in the Efficiency Optimization of Synchrono...IJPEDS-IAES
Excessive dead time in complementary switches causes significant energy losses in DC-DC
power conversion. The optimization of dead time prevents the degradation of overall efficiency
by minimizing the body diode conduction of power switches and, as a consequence,
also reduces reverse recovery losses. The present work aims at analyzing the influence of
one of the most important characteristics of a digital controller, the timer resolution, in the
context of dead-time optimization for synchronous buck converters. In specific, the analysis
quantifies the efficiency dependency on the timer resolution, in a parameter set that comprises
duty-cycle and dead-time, and also converter frequency and analog-to-digital converter
accuracy. Based on a sensorless optimization strategy, the relationship between all
these limiting factors is described, such as the number of bits of timer and analog-to-digital
converter. To validate our approach experimental results are provided using a 12-to-1.8V
DC-DC converter, controlled by low- and high-resolution pulse-width modulation signals
generated with an XMC4200 microcontroller from Infineon Technologies. The measured
results are consistent with our analysis, which predicts the power efficiency improvements
not only with a fixed dead time approach, but also with the increment of timer resolution.
PDF SubmissionDigital Marketing Institute in NoidaPoojaSaini954651
https://www.safalta.com/online-digital-marketing/advance-digital-marketing-training-in-noidaTop Digital Marketing Institute in Noida: Boost Your Career Fast
[3:29 am, 30/05/2024] +91 83818 43552: Safalta Digital Marketing Institute in Noida also provides advanced classes for individuals seeking to develop their expertise and skills in this field. These classes, led by industry experts with vast experience, focus on specific aspects of digital marketing such as advanced SEO strategies, sophisticated content creation techniques, and data-driven analytics.
On the Impact of Timer Resolution in the Efficiency Optimization of Synchrono...IJPEDS-IAES
Excessive dead time in complementary switches causes significant energy losses in DC-DC
power conversion. The optimization of dead time prevents the degradation of overall efficiency
by minimizing the body diode conduction of power switches and, as a consequence,
also reduces reverse recovery losses. The present work aims at analyzing the influence of
one of the most important characteristics of a digital controller, the timer resolution, in the
context of dead-time optimization for synchronous buck converters. In specific, the analysis
quantifies the efficiency dependency on the timer resolution, in a parameter set that comprises
duty-cycle and dead-time, and also converter frequency and analog-to-digital converter
accuracy. Based on a sensorless optimization strategy, the relationship between all
these limiting factors is described, such as the number of bits of timer and analog-to-digital
converter. To validate our approach experimental results are provided using a 12-to-1.8V
DC-DC converter, controlled by low- and high-resolution pulse-width modulation signals
generated with an XMC4200 microcontroller from Infineon Technologies. The measured
results are consistent with our analysis, which predicts the power efficiency improvements
not only with a fixed dead time approach, but also with the increment of timer resolution.
PDF SubmissionDigital Marketing Institute in NoidaPoojaSaini954651
https://www.safalta.com/online-digital-marketing/advance-digital-marketing-training-in-noidaTop Digital Marketing Institute in Noida: Boost Your Career Fast
[3:29 am, 30/05/2024] +91 83818 43552: Safalta Digital Marketing Institute in Noida also provides advanced classes for individuals seeking to develop their expertise and skills in this field. These classes, led by industry experts with vast experience, focus on specific aspects of digital marketing such as advanced SEO strategies, sophisticated content creation techniques, and data-driven analytics.
Storytelling For The Web: Integrate Storytelling in your Design ProcessChiara Aliotta
In this slides I explain how I have used storytelling techniques to elevate websites and brands and create memorable user experiences. You can discover practical tips as I showcase the elements of good storytelling and its applied to some examples of diverse brands/projects..
ARENA - Young adults in the workplace (Knight Moves).pdfKnight Moves
Presentations of Bavo Raeymaekers (Project lead youth unemployment at the City of Antwerp), Suzan Martens (Service designer at Knight Moves) and Adriaan De Keersmaeker (Community manager at Talk to C)
during the 'Arena • Young adults in the workplace' conference hosted by Knight Moves.
Visual Style and Aesthetics: Basics of Visual Design
Visual Design for Enterprise Applications
Range of Visual Styles.
Mobile Interfaces:
Challenges and Opportunities of Mobile Design
Approach to Mobile Design
Patterns
Between Filth and Fortune- Urban Cattle Foraging Realities by Devi S Nair, An...Mansi Shah
This study examines cattle rearing in urban and rural settings, focusing on milk production and consumption. By exploring a case in Ahmedabad, it highlights the challenges and processes in dairy farming across different environments, emphasising the need for sustainable practices and the essential role of milk in daily consumption.
Connect Conference 2022: Passive House - Economic and Environmental Solution...TE Studio
Passive House: The Economic and Environmental Solution for Sustainable Real Estate. Lecture by Tim Eian of TE Studio Passive House Design in November 2022 in Minneapolis.
- The Built Environment
- Let's imagine the perfect building
- The Passive House standard
- Why Passive House targets
- Clean Energy Plans?!
- How does Passive House compare and fit in?
- The business case for Passive House real estate
- Tools to quantify the value of Passive House
- What can I do?
- Resources
1. Elec 326 Sequential Circuit Timing
13.1
13. Sequential Circuit Timing
Objectives
This section covers several timing considerations encountered
in the design of synchronous sequential circuits. It has the
following objectives:
Define the following global timing parameters and show
how they can be derived from the basic timing parameters
of flip-flops and gates.
Maximum Clock Frequency
Maximum allowable clock skew
Global Setup and Hold Times
Discuss ways to control the loading of data into registers
and show why gating the clock signal to do this is a poor
design practice.
2. Elec 326 Sequential Circuit Timing
13.2
Reading Assignment
Much of the information in this section is not in the Brown
& Vranesic text. There is material on clock skew in section
10.3. That section also discusses the effects of gating the
clock.
3. Elec 326 Sequential Circuit Timing
13.3
13.1. Maximum Clock Frequency
The clock frequency for a synchronous sequential
circuit is limited by the timing parameters of its flip-
flops and gates. This limit is called the maximum
clock frequency for the circuit. The minimum clock
period is the reciprocal of this frequency.
Relevant timing parameters
Gates:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Flip-Flops:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Setup time: tsu
Hold time: th
4. Elec 326 Sequential Circuit Timing
13.4
Example
D Q
Q
CK
Q
TW ≥ max tPFF + tsu
For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns
TW ≥ max (max tPLH + tsu, max tPHL + tsu)
TW ≥ max (25+20, 40+20) = 60
5. Elec 326 Sequential Circuit Timing
13.5
Example
D Q
CK
Q
TW ≥ max tPFF + max tPINV + tsu
6. Elec 326 Sequential Circuit Timing
13.6
Example
D Q
Q
D Q
Q
MUX
0
1
Q0 Q1
CK
TW ≥ max tPFF + max tPMUX + tsu
7. Elec 326 Sequential Circuit Timing
13.7
Example
Paths from Q1 to Q1:
Paths from Q1 to Q2:
Paths from Q2 to Q1:
Paths from Q2 to Q2:
None
TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns
TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns
TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns
TW ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns
TW ≥ 47 ns
8. Elec 326 Sequential Circuit Timing
13.8
Clock Skew
If a clock edge does not arrive at different flip-flops at
exactly the same time, then the clock is said to be skewed
between these flip-flops. The difference between the times
of arrival at the flip-flops is said to be the amount of clock
skew.
Clock skew is due to different delays on different paths
from the clock generator to the various flip-flops.
Different length wires (wires have delay)
Gates (buffers) on the paths
Flip-Flops that clock on different edges (need to invert clock for
some flip-flops)
Gating the clock to control loading of registers (a very bad idea)
9. Elec 326 Sequential Circuit Timing
13.9
Example (Effect of clock skew on clock rate)
Clock C2 skewed after C1
Q1
Q2
D Q
Q
D Q
Q
CK
C1
C2
D2
TW ≥ max TPFF + max tOR + tsu
(if clock not skewed, i.e., tINV = 0)
TW ≥ max TPFF + max tOR + tsu - min tINV
(if clock skewed, i.e., tINV > 0)
10. Elec 326 Sequential Circuit Timing
13.10
Clock C1 skewed after C2
Q1
Q2
D Q
Q
D Q
Q
CK
C1
C2
D2
TW ≥ max TPFF + max tOR + tsu
(if clock not skewed, i.e., tINV = 0)
TW ≥ max TPFF + max tOR + tsu + max tINV
(if clock skewed, i.e., tINV > 0)
11. Elec 326 Sequential Circuit Timing
13.11
Summary of maximum clock frequency calculations
D Q
Logic
Network
D Q
C1 C2
Q1 D2
C1
Q1
D2
C2
TW
tPFF tOR tsu
tSK = tINV
C1
Q1
D2
C2
TW
tPFF tOR
tsu
tSK = tINV
C2 skewed after C1: TW ≥ max TPFF + max tNET + tsu - min tINV
C2 skewed before C1: TW ≥ max TPFF + max tNET + tsu + max tINV
12. Elec 326 Sequential Circuit Timing
13.12
Example
For each of the following two connections find
The minimum clock period
The maximum and minimum delay from CLK to YOUT
tXY = Network delay from X to Y
tXD = Network delay from X to D
tQY = Network delay from Q to Y
tQD = Network delay from Q to D
13. Elec 326 Sequential Circuit Timing
13.13
Circuit 1:
max tPFF + max tQY + (n-2) max tXY +max tXD + tsu
max tPFF + max tQD + tsu
n ≥ 2
Tw ≥
Tw ≥
≥ TW
Minimum Clock Period:
Maximum Delay:
Minimum Delay:
TCY ≤
TCY ≥
max tPFF + max tQY + (n-1) max tXY
min tPFF + min tQY
tXY= Network delay fromX to Y
tXD = Network delay fromX to D
tQY= Network delay fromQ to Y
tQD = Network delay fromQ to D
14. Elec 326 Sequential Circuit Timing
13.14
Circuit 2:
n ≥ 2
max tPFF + max tXD + tsu
max tPFF + max tQD + tsu
Tw ≥
Tw ≥
Minimum Clock Period:
Maximum Delay:
Minimum Delay:
TCY ≤
TCY ≥
max tPFF + max (max tXY, max tQY)
min tPFF + min (min tXY, min tQY)
tXY= Network delay fromX to Y
tXD = Network delay fromX to D
tQY= Network delay fromQ to Y
tQD = Network delay fromQ to D
15. Elec 326 Sequential Circuit Timing
13.15
13.2. Maximum Allowable Clock Skew
How much skew between C1 and C2 can be tolerated
in the following circuit?
Case 1: C2 delayed after C1
D Q
Q
D Q
Q
C2
Q1 D2
C1
tPFF > th + tSK
tSK < min tPFF - th
16. Elec 326 Sequential Circuit Timing
13.16
Case 2: C1 delayed from C2
D Q
Q
D Q
Q
C2
Q1 D2
C1
17. Elec 326 Sequential Circuit Timing
13.17
How does additional delay between the flip-flops
affect the skew calculations?
tSK ≤ min tPFF - th
tsk ≤ min tPFF + min tMUX - th
18. Elec 326 Sequential Circuit Timing
13.18
Summary of allowable clock skew calculations
tSK + th ≤ tPFF + tNET
tSK ≤ min tPFF + min tNET - th
19. Elec 326 Sequential Circuit Timing
13.19
Example: What is the minimum clock period for the
following circuit under the assumption that the clock
C2 is skewed after C1 (i.e., C2 is delayed from C1)?
N1
N2
C1 C2
Q1 D2 Q2
D1
D Q
Q
D Q
Q
20. Elec 326 Sequential Circuit Timing
13.20
First calculate the maximum allowable clock skew.
Next calculate the minimum clock period due to the path
from Q1 to D2.
Finally calculate the minimum clock period due to the path
from Q2 to D1
N1
N2
C1 C2
Q1 D2 Q2
D1
D Q
Q
D Q
Q
tSK < min tPFF + min tN1 - th
TW > max tPFF + max tN1 + tsu - min tSK
TW > max tPFF + max tN1 + tsu + max tSK
TW > max tPFF + max tN2 + tsu + (min tPFF + min tN1 - th)
TW > max tPFF + min tPFF + max tN2 + min tN1 + tsu - th
21. Elec 326 Sequential Circuit Timing
13.21
13.3. Global Setup Time, Hold Time and
Propagation Delay
Global setup and hold times (data delayed)
TSU = tsu + max tNET TH = th - min tNET
D Q
Q
X
CK
NET D
CLK
22. Elec 326 Sequential Circuit Timing
13.22
Global setup & hold time (clock delayed)
D Q
Q
CK
D
CLK
TSU = tsu - min tC TH = th + max tC
23. Elec 326 Sequential Circuit Timing
13.23
Global setup & hold time (data & clock delayed)
D Q
Q
X
CK
NET D
CLK
TSU = tsu + max tNET - min tC TH = th - min tNET + max tC
24. Elec 326 Sequential Circuit Timing
13.24
Global propagation delay
D Q
Q
CK
NET
CLK
Y
Q
TP = tC + tFF + tNET
25. Elec 326 Sequential Circuit Timing
13.25
Summary of global timing parameters
TSU = tsu + max tPN - min tPC ≤ tsu + max tPN
TH = th + max tPC - min tPN ≤ th + max tPC
TP = tPFF + tPN + tPC
26. Elec 326 Sequential Circuit Timing
13.26
Example
Find TSU and TH for input signal LD relative to CLK.
LD
D
CLK
CK
Q
D Q
Q
TSU = tsu +max tNET - min tC
TH = th - min tNET + max tC
= tsu + max tINV + max tNAND + max tNAND - min tINV
= th - min tNAND - min tNAND + max TINV
27. Elec 326 Sequential Circuit Timing
13.27
13.4. Register load control (gating the clock)
A very bad way to add a load control signal LD to a
register that does not have one is shown below
The reason this is such a bad idea is illustrated by the
following timing diagram.
The flip-flop sees two rising edges and will trigger
twice. The only one we want is the second one.
D
LD
CLK
CK
D Q
Q
28. Elec 326 Sequential Circuit Timing
13.28
If LD was constrained to only change when the clock was low,
then the only problem would be the clock skew.
29. Elec 326 Sequential Circuit Timing
13.29
If gating the clock is the only way to control the
loading of registers, then use the following approach:
There is still clock skew, but at least we only have one
triggering edge.
D
LD
CLK
D Q
Q
30. Elec 326 Sequential Circuit Timing
13.30
The best way to add a LD control signal is as follows:
LD
D
CLK
D Q
Q
31. Elec 326 Sequential Circuit Timing
13.31
13.5. Synchronous System Structure and Timing
32. Elec 326 Sequential Circuit Timing
13.32
13.6. Tips & Tricks
Use timing diagrams to determine the timing properties of
sequential circuits
13.7. Pitfalls
Using typical timing values from the data sheet (use
only max and/or min values)
Gating the clock
33. Elec 326 Sequential Circuit Timing
13.33
13.8 Review
How the flip-flop and gate timing parameters affect
the maximum possible clock frequency.
How clock skew affect maximum possible clock frequency.
How the delay of logic between flip-flops affects the
maximum allowable clock skew.
How flip-flop setup and hold times are translated by
the combinational logic delays to get global setup and
hold times.
The detrimental effect of gating the clock signal.