This document provides an overview of electronic packaging fundamentals related to automotive MEMS and sensor technologies. It discusses key challenges in miniaturizing MEMS devices, high costs of component testing, and integrating MEMS with CMOS. Solutions proposed include standardized MEMS packaging to reduce costs and wafer-level testing to identify faulty devices earlier. Both approaches aim to improve reliability while lowering manufacturing expenses. Overall, the document analyzes ongoing issues in MEMS technology and packaging methods that could help advance automotive and consumer product applications of MEMS sensors.

1. Electronic Packaging FundamentalsCourse Project Report
Automotive MEMS and Sensors Technology
INTRODUCTION
Micro-electromechanical systems (MEMS) are developed as a
result of technological advancement in integrated circuits and
micromanufacturing, and its technology has become the
backbone of many sensor technologies in automobiles. Although
faced with many challenges such as device miniaturization,
quality, and reliability testing, and high cost from packaging
and testing, emerging solutions such as MEMS packaging
standardization and wafer level testing can be adopted to
overcome these setbacks.
LITERATURE REVIEW
Device Miniaturization [1]
Device miniaturization has been the ongoing trend in the
electronic industry, and the demand for advancement in MEMS
technology reflects the drive as well. The recent development in
autonomous vehicles and portable devices are calling for higher
integration of MEMS sensors to support its increasing
capabilities. As these devices increase in function and
complexity, the available footprint within the device is
continuously limited by the ever-decreasing device size. The
manufacturing technique that enables the production of MEMS
technology is bulk surface machining, where layers of
mechanical structures and features are created through a
combination of etching and layer deposition. As the demand for
smaller and more intricate features rises, the industry must
provide an answer in terms of improved and more advanced
manufacturing techniques to address the miniaturization trend.
Component Testing [2]
Many MEMS devices serve as accelerometers, gyroscopes, and
sensors for critical data acquisition applications; therefore, the

2. reliability and quality of these devices must be ensured.
Extensive reliability testing is performed at the device or
package level to ensure that the product meets requirements and
specifications. When it comes to testing MEMS products, both
electrical and mechanical analysis is required for a thorough
examination of the product performance. The coupling
relationship of the mechanical parts with electrical circuitry
results in a complex system that requires unique testing
equipment. The cost of testing equipment and setups such as
testing stations can easily exceed millions of dollars in capital
investment from the device manufacturer. The Challenge of
high testing cost poses a roadblock in the MEMS market and
innovative solutions are needed for a cost-saving solution.
MEMS and CMOS Integration [3]
As shown in Fig. 1, MEMS structure is often coupled with
integrated circuitry to perform sensing and analysis of the
acquired data. The industry's drive to lower the production cost
and device size calls for the tackling of the challenge in MEMS
and CMOS process integration. The current method for system
integration involves the manufacturing of the MEMS and
electrical circuitry on different substrates, and interconnects or
direct bonding of the two chips are performed for device
integration. This approached is forced by the high cost
associated with monolithic integration. Challenges foreseen
within the industry would be to lower the cost associated with
the integration of MEMS with IC fabrication.
Figure 1 Acceleration sensor internal layout and MEMS
structure [4]
MEMS Packaging [5]
Packaging serves a crucial function in providing the proper
mechanical protection and environmental control for the MEMS
device. Given the role of packaging and its value in ensuring
the reliability and function of the device, packaging and testing

3. can often take up to 90% of the total production cost. The key
challenge in the area of MEMS packaging falls in the design of
the enclosure to provide the proper protection against
temperature, shock, moisture, and stress while allowing data of
interest to be collected through a specified medium. In the case
of pressure sensors used in pressure monitoring and control,
package engineers must ensure that a sufficient and controlled
amount of desired inputs can be registered by the MEMS
device. This process proves to be difficult in that many of the
elements the sensor is designed for monitoring can easily cause
device malfunction if the input is let uncontrolled (ex: pressure,
temperature).
Co-design Requirement [6]
The name "micro-electromechanical system" clearly indicates
the need for the collaboration of mechanical and electrical
engineering disciplines when developing MEMS technologies.
Although the development of MEMS did not revolutionize the
world of engineering and design, it does, however, pose the
challenge and requirement for a higher level of co-design
initiative and execution. In the past, mechanical and electrical
engineers each have simulation and design software dedicated to
their area of interest and expertise. The gap between these
software (ex: FEA and EDA) pose many issues when designing
MEMS devices. The lack of communication between the
software and engineering groups means that critical design
considerations and simulation results were not being shared
efficiently. To successfully develop a product to ensure that
quality and reliability performance are meeting requirements,
there is a growing challenge for software developers and
designers to come up with a solution and initiative for co-
designs.
DESCRIPTION
Standardized Package

4. Solution
s
As previously mentioned, packaging and testing can often take
up to 90% of the total production cost of MEMS devices. Unlike
conventional IC packages, where package options have been
standardized and thoroughly tested by many manufacturers,
MEMS packaging still proves to be challenging due to the high
level of customization and variation in the package design [7].
The high cost associated with packaging can be resolved by
introducing a company or industry-wide package standard. To
establish a standardized package model for MEMS devices,
characteristics such as package dimension, I/O count,
connection type, and material sets must be defined. Key ideas to
keep in mind when defining such parameters should be designed
for manufacturability and for reliability, where these two
factors can greatly influence the resulting cost of the device if
left unconsidered. Each characteristic mentioned above warrants
extensive testing and review because the chosen package types
will replace many customized package designs and must be
capable of providing the package solution needed for a wide
range of products.
Wafer Level Testing

5. The general approach for MEMS device testing has been at the
component level, where the quality of the product is inspected
at the end of the fabrication process. This approach inherently
increases the cost of MEMS fabrication because faulty devices
are identified at the end of the manufacturing process, leading
to higher waste of resources and time since the products have
been processed and packaged. A recent approach taken by many
device manufacturers is the testing of the MEMS device at the
wafer level – wafer-level testing.
Wafer-level testing involves providing the device with required
electrical stimulation, as well as required testing input such as
sound, light, vibration, temperature, and pressure depending on
the sensor application [8]. Traditional IC testing often requires
input and output both in the form of an electrical signal. Wafer -
level testing of MEMS devices requires not only the electrical
input but also output as a result of the mechanical input to the
system (ex: sensor applications). To conduct tests at the wafer
level, testing devices such as test probes and controllable
testing chambers must be acquired. Depending on the
device/sensor application, the chamber needs to be capable of
creating an inert environment with controlled environmental
specifications targeting different types of MEMS sensors.
INFERENCES/ADVANTAGES-DISADVANTAGES
With the application of both package standardization and wafer

6. level testing in MEMS design and manufacturing, issues and
challenges such as high-reliability requirements, manufacturing
cost, and testing difficulty can be resolved.
In the case of MEMS package standardization, research and
testing effort can be focused and allocated for a selective
number of package solutions. This approach can allow
companies to develop reliable material sets, process control
parameters, and design guidelines for those specific packaging
solutions. By developing a mature design model and
manufacturing approach by standardizing the package types,
companies can increase the quality and reliability of the product
while driving costs down. A drawback to this approach is the
requirement of boundary and design limitations placed on
MEMS designers. No longer designers can utilize the versatility
of custom package design options for MEMS since the design of
the MEMS and electrical circuitry have to take into
consideration of the available package types available.
Wafer-level testing provides a significant advantage over
component level testing due to the prevention of resource and
time wasted on failed components identified at the wafer level.
By identifying the failed parts early on, additional processing
and packaging effort can be preserved, thus lowering the cost of
manufacturing (Fig. 2). The challenge associated with this
approach is the large investment needed for purchasing of
testing equipment and setup. The required equipment must be

7. capable of both delivering mechanical input while retrieving the
electrical signal and response; the test environment needs to
provide the ability for fine control of the testing environment to
ensure test accuracy and repeatability.
Figure 2 Cost comparison with and without wafer-level testing
[8]
CONCLUSIONS
As the demand for MEMS technology grows with the increasing
complexity of application areas, many challenges have and will
continue to pose design and application issues for MEMS
devices. It is paramount that the industry position the necessary
resources and effort in tackling those challenges mentioned in
this paper to improve the function and performance of MEMS
products. In the case of this review paper, package
standardization and wafer level testing are discussed and
analyzed to align focuses on the potential benefits capable of
receiving from these two approaches. The number of
automobiles produced and purchased is growing at an upward
trend, meaning MEMS are being incorporated in more and more
of our daily lives. This trend requires the continual
advancement of MEMS products through methods such as those
described in this paper.

8. REFERENCES
[1]Marek, J. “MEMS for Automotive and Consumer
Electronics.” 2010 IEEE International Solid-State Circuits
Conference - (ISSCC), vol. 53, IEEE, 2010, pp. 9–17,
doi:10.1109/ISSCC.2010.5434066.
[2]Muhammad, et al. “A Review on Key Issues and Challenges
in Devices Level MEMS Testing.” Journal of Sensors, Hindawi,
21 Feb. 2016, www.hindawi.com/journals/js/2016/1639805/.
[3]Villanueva, et al. “Grand Challenge in N/MEMS.” Frontiers,
Frontiers, 11 Nov. 2015,
www.frontiersin.org/articles/10.3389/fmech.2015.00015/full.
[4]Marek, J. “Automotive MEMS Sensors - Trends and
Applications.” Proceedings of 2011 International Symposium on
VLSI Technology, Systems and Applications, IEEE, 2011, pp.
1–2, doi:10.1109/VTSA.2011.5872208.
[5]Bhat, K N, and M M Nayak. MEMS Pressure Sensors- An
Overview of Challenges in Technology and Packaging.
pdfs.semanticscholar.org/b3ab/9fd4fcae88c557c7d7ccd7e26472
a50c4b60.pdf.
[6]Karam, J. M., et al. “MEMS: The New Challenge for the
Electronic Design Automation Vendors.” SpringerLink,
Springer, Berlin, Heidelberg, 1 Jan. 1998,
link.springer.com/chapter/10.1007/978-3-662-39696-4_11.

9. [7]Bauer, Charles E. Packaging MEMS, The Great Challenge of
the 21st Century. TechLead Corporation, 2000,
www.osti.gov/etdeweb/servlets/purl/20136250#page=40.
[8]Werner, Frank-Michael. “Wafer Level Test: Significant Time
and Cost Reduction of MEMS Production.” Electron-Mec, SUSS
MicroTec Test Systems GmbH, www.electron-mec.com/wp-
content/uploads/applications/Publication-
2003_Wafer_Level_Test_Significant_Time_and_Cost_Reductio
n_of_MEMS_Production.pdf.
Page 2 of 2
HSL 3831 Women in Contemporary Society
Final Exam
Provide a response according to the directions for each. For
each response, integrate at least one professional resource to
support your response. You may use your textbook and/or other
professional literature sources (i.e., textbooks,
local/state/national/international professional organization
websites, .gov sites, .edu sites). Cite sources in the body of your
response and provide a full reference citation at the end of the
exam. Refer to syllabus schedule for due date and time. 10
points each/100 points possible.

10. 1. WOMEN AND SEXUALITY
In your professional career position, envision that you work
with female adolescents ages 15-17. You have been invited to
give a talk on decision-making and sexual activity (e.g.,
entering a sexual relationship, engaging in sexual activity
without being in a relationship, having sexual intercourse for
the first time, etc.). Using the steps in the decision-making
model below, construct a detailed/paragraph-format outline on
the topics and sub-topics that you will discuss with your
audience. Minimum page length is 1 and maximum page length
is 3.
Decision-Making Model
I. Identify and briefly explain the decision-making situation
(choose an example from above or create your own example
related to adolescent women and sexuality)
II. List alternative choices related to the situation
III. Explain and compare the alternative choices and the
possible consequences (e.g., pregnancy, sexually transmitted
infections, social stigma, relationship changes, others)
of each alternative choice
IV. Explain the value of serious critical thinking and reflection
when it comes to making decisions about sexuality as a teen

11. 2. WOMEN AND HEALTH
Choose ONE of the following questions to answer related to
women and health.
A. Compare and contrast explanations of the following types of
gynecological cancers: cervical, ovarian, uterine, vaginal, and
vulvar.
B. Compare and contrast explanations of the mental and
physical symptom of anxiety and depression.
C. Compare and contrast explanations of the three stages of
menopause: perimenopause, menopause, and post-menopause.
1-2 pages in length
3. WOMEN AND VIOLENCE
Explain key points of the possible psychological, physical, and
emotional effects experienced by women after sexual assault.
1-2 pages in length
4. WOMEN AND FAMILIES
Identify and explain three possible challenges experienced by
women who are balancing careers and families (this could be
related to caring for/raising children, caring for aging parents,
or other family situations).
1-2 pages in length
5. WOMEN AND WORK
What is FMLA? Who is covered by FMLA? Who is eligible for

12. FMLA? What is the length of time for FMLA? What does
FMLA entitle people to?
1-2 pages in length
6. WOMEN IN POLITICS
Look up and provide the following. Number and percentage of
female:
a. U.S. Supreme Court Justices
b. U.S. Senators
c. U.S. House of Representatives
d. State Governors
e. State Senators
f. State House of Representatives
g. Mayors of U.S. Cities
7. WOMEN AND SUBSTANCE ABUSE
Identify and explain five ways that substance abuse (alcohol
and/or other drugs) impacts
women, specifically.
1-2 pages
8. WOMEN AND THE MILITARY
Female Service members (SMs) in the military face unique
challenges that contribute to relatively few joining the military
and not many staying in long enough to become officers.

13. Identify and explain three of these unique challenges.
1-2 pages
9. WOMEN AND GLOBAL ISSUES
The Peace Corps identify three broad issues impacting women
around the world. They are: education, health and safety, and
gender equality. Identify and explain one issue related to each
of those categories. You may choose to focus on a specific
country or an issue impacting women in multiple countries.
1-2 pages in length
10. WOMEN AND THE ENVIRONMENT
Select ONE of the following female environmentalists. Write a
biographical summary on her notable accomplishments.
1 page
· Erin Brockovich
· Rachel Carson
· Jane Goodall
· Wangari Maathai
· Greta Thunberg
Electronic Packaging Fundamentals EE/CE/Mech Eng 4v95

14. PROJECT TOPICS
1. NANO MATERIALS FOR ELECTRONIC PACKAGING
2. ADVANCED INETRCONNETCS FOR ELECTRONIC
PACKAGING
3. 3D PACKAGING
FANOUT WAFERSCALE PACKAGING
5. THERMAL MANAGEMENT FOR HIGH POWER
ELECTRONICS PACKAGING
6. ELECTRONIC PACKAGING FOR MEDICAL
IMPLANTABLE DEVICES
Project Topics ( Hints/Pointers)

15. Project#3 3D Packaging
Chip on Chip, Wafer on Wafer, Package on Package stacking,
interconnects like Though Silicon Vias, Through Package Vias,
Assembly/processes, advantages/disadvantages etc
Project (Expectations –Submission Details)
Project Report Expectations
Literature review summary (with at least 8 references)
Challenges foreseen connecting to technology demands and/or
Applications , at least one
new/emerging concept needs to be discussed at length.
Minimum Four pages ( max 6 pages) write-up - references need
to be on the additional page
Format: Introduction, Description of the technology,
Uniqueness, Advantages/Disadvantages, Discussion/Inference,
Conclusions & recommendations for future work, References.
Font size Times New Roman 12, Heading and subheadings in
bold.
Submission Details
Project Write-up must be submitted by 5pm Monday, May 3,
2021.

16. IC Assembly Technology – Wafer Chip Scale Packaging
Lecture 8
Wafer level packaging (WLP) / Wafer Chip Scale Packaging (
WCSP)
& Introduction to 3D Packaging
WLP/WCSP
Ultimate Down-Sizing
Wafer Level CSP
Dicing
Wafer

17. Wafer
Packaging
Dicing
QFP,BGA, CSP and other lead frame & substrate
based packages
Packaging
WLP/WCSP
Wafer Level Packaging / Wafer Chip Scale Packaging
Wafer Level
Processing
BGA/CSP
Flip Chip
WLP•Electrical Performance

18. •Low Profile
•Minimum materials
•Self Alignment
•Assembly
•Standardization
•High reliability
•Test
•Low Cost
•High yield
• Process Control
• Wafer level Inspection
P

19. a
c
k
a
g
e
S
iz
e
Miniaturization
Miniaturization
Miniaturization
PDIP
SOIC
TSSOP

20. SOT
TQFN
UTQFN
WCSP
Can
Tube
BGA
Packaging is enabling functional density increase:
What is WCSP & What is inside WCSP ? ( Fan -in WCSP)
• WCSP (Wafer Chip Scale Package) is a package type that is
• Completely processed in wafer and when the wafer is
singulated , the package is complete.
• The smallest form factor possible for a package with external

21. leads/balls
• A WCSP may include
• One or more dielectric layers, such as PI (polyimide) or PBO
(Polybenzoxazole) for insulation and stress buffering.
• A Cu routing layer.
• A UBM (Under Bump Metal) layer consisting of one or more
metals, such as Cu or Ni.
• A solder ball.
Slides 5 -21 Ref: Pat Thompson ( Texas Instruments) lecture at
UTD Feb 2020
5
Benefits of WCSP
• Batch processing to lower costs
• All steps prior to pick and place are performed at the wafer
level; this can result in an assembly

22. lot size of 10Ks to 100Ks;
• Lower assembly capital costs
• Handling and shipping logistics can be streamlined:
• Final test is done at the wafer level; savings in test and
logistics can be as, or more, important than the manufacturing
cost
• No need for Known Good Die - tested like other ICs
• ICs can be packaged in the fab and shipped directly to
customers for surface mounting with conventional SMT
• Reduced total cycle time can minimize inventory requirements
• Functionality can be packed into a form factor as small as the
die
6
2019 IEEE 69th ECTC │ Las Vegas, Nevada │ May 28 –
May 31,
2019

23. WCSP challenges
• Wafer bumping can be costly:
• Average bumping cost of ~US$200 for 200 mm wafer
• “Small die” at 1mm2 for ~30,000 die/wafer; unit cost is
$0.006
• “Medium die” at 9mm2 for ~3500 die/wafer; unit cost is
$0.057
• “Large die” at 50mm2 for ~625 die/wafer; unit cost is $0.32
• High cost for poor yielding wafers
• Die shrink requires a new package
• Board-level reliability
• High CTE mismatch between Si die and organic PCB
• Current carrying capacity
• Solder has ~1% capability of Cu
• Mechanical robustness
• Exposed Si

24. • SMT and PCB costs
• HVM SMT processes migrate to FC assembly processes and
tools at ~0.2mm spacing
• PCB design rules drive more expensive substrates below
~0.4mm pitch
7
2019 IEEE 69th ECTC │ Las Vegas, Nevada │ May 28 –
May 31,
2019
WCSP types
• Bump directly on the pad
• Simplest WCSP
• UBM directly on die metal pad w/solder ball on
UBM
• Bump on pad w/dielectric
• Adds a layer of dielectric for stress buffer

25. • BOPCOA (BOP on Copper Over Anything)
• Uses Cu layer for routing, redistribution
• Requires VIATOP/planar PO at wafer fab
• Most common WCSP in TI; TI unique
construction
• RDL (Redistribution Layer)
• Uses initial dielectric layer as stress buffer for Cu,
routing
• Enables use of standard PO at wafer fab
• Typical industry construction
8
Bump on pad BOP
BOPCOA RDL
High level WCSP manufacturing flow
9

26. Bump fab Package probe AssemblyWafer fab Wafer probe
Cu
uubm
Incoming Clean
TiW / Cu Seed Dep
Polyimide expose & develop
Polyimide Spin
Ash performed
TiW / Cu Seed Dep
UBM
Resist Pattern

27. Cu Plate
Resist Strip
Ball placement
Reflow
Completed BOPCOA wafer
1 um W Vias
PO
COA plate
Resist PatternResist Strip
Seed Etch
Seed Etch
COA = 6,10 um thick
PI = 6 um thick

28. UBM = 10, 18, 35 um thick
Polyimide Oven Cure
TiW
COA
Si
Al
BOPCOA process flow
BOPCOA bump flow
11
RDL Process Flow
12

29. Post-bump fabrication images
13
STANDARD FLOWWCSP assembly flow
BG Taping Back Grinding Detaping Backside Laminate Oven
Cure
Laser MarkWafer MountWafer SawTape and Reel
Animation created by M. Minoc,
Texas Instruments, Ref Pat Thompson (TI) Lecture at UTD Feb
2020
Mechanical saw
15

30. - Heat zone creates brittle poly silicon layer in scribe street near
center of wafer
- Weaker poly-silicon layer yields when stressed to separate die
from each other
- Metal layers split and tear during singulation
- Laser leaves no visible damage to wafer
- No material is removed
Laser singulation
WCSP package definition parameters
6
Nomenclature

31. • Y - indicates chipscale package (also used for picostar)
• 2nd Letter – indicates Pitch
• 3rd Letter – indicates Height
Pitch 2nd Letter
0.5 A
0.4 B
0.35 C
0.3 G
Height 3rd Letter
0.55 F
0.5 G
0.4 H
0.35 J

32. PKG
Bump
Pitch
Max Package
Height (mm)
UBM
Diameter
Ball Diameter
(pre-attach)
Bump Diameter
(post-reflow)
Bump
Height

33. BG Value
(mil)
Max Array
Size
YAF 500 0.55 230 250 265 200 10 11x11
YAH 500 0.4 230 200 230 140 7 7x7
YBG 400 0.5 230 225 250 170 10 9x9
YBH 400 0.4 200 180 205 130 7 6x6
YBJ 400 0.35 180 150 180 100 7 5x5
YCG 350 0.5 200 180 205 130 10 5x5
YCH 350 0.4 200 180 205 130 7 5x5
YCJ 350 0.35 180 150 180 100 7 4x4

34. YGJ 300 0.35 180 150 180 100 7 3x3
Post-assembly images
18
WCSP Assembly issues
19
Edge chipping
Subsurface chipping
Wafer cracking
What is Power WCSP ?
• Power WCSP is a new low-profile WCSP
platform with enhanced electrical and thermal
performance

35. • Benefits:
• Thin package profile (0.3mm package height max)
• Better current handling capacity and thermal
performance obtained through a combination of
larger cross-sectional area and a lower
electrical/thermal resistance interconnect structure
• Design flexibility
• Applications: Modules that prefer better
electrical and thermal as well as require thin
package
0.3mm max
Introduction to 3D packaging
3D Packaging Classifications

36. • Chip on Chip ( stacked chips/ bare dies- unencapsulated
chips)
• Package on Package ( including stacked multi chip modules)
• Wafer Level Stacking / 3D ICs
3D Packaging
3D packaging
3D- Stacking Category
• Staked wWafer level stacking
• Stacked Bare Die
• Stacked Packaged
• Stacked Multichip Modules
Source : Alpine Microsystems
Ref: Hynix

37. Bottom DieSpacer
Top Die
Bottom DieSpacer
Top Die
3D packaging
Through-silicon via (TSV) or through-chip via is
vertical electrical connection (via) that passes completely
through a silicon wafer or die. TSVs are high performance
interconnect techniques used as an alternative to wire-
bond and flip chips to create 3D packages and 3D integrated
circuits. Compared to alternatives such as package-on-
package, the interconnect and device density is substantially

38. higher, and the length of the connections becomes shorter.
https://en.wikipedia.org/wiki/Electrical_connection
https://en.wikipedia.org/wiki/Via_(electronics)
https://en.wikipedia.org/wiki/Silicon_wafer
https://en.wikipedia.org/wiki/Die_(integrated_circuit)
https://en.wikipedia.org/wiki/Wire_bond
https://en.wikipedia.org/wiki/Flip_chip
https://en.wikipedia.org/wiki/Three-
dimensional_integrated_circuit
https://en.wikipedia.org/wiki/Packa ge_on_package
3D Packaging
3D packaging with TSVs ( Through Silicon Vias)
3D packaging with TSV examples
3D with TSV : memory on top of logic with TSV 3D TSV :
Logic on top of memory with TSV

39. 3D packaging
Ref Intel
Foveros 3D
Dec 2018 announcement
A combination of Flip Chip
& Through Silicon Via
( TSV ) connections
Samsung Announces Availability of its Silicon-Proven 3D IC
Technology
for High-Performance Applications
August 13, 2020
Samsung 'X-Cube' enables industry-first 3D SRAM-logic
working silicon at 7nm and

40. beyond. Bandwidth and density can be scaled to suit diverse
design requirements in
emerging applications
Samsung Electronics, a world leader in advanced semiconductor
technology, today announced the immediate availability of
its silicon-proven 3D IC packaging technology, eXtended-Cube
(X-Cube), for today’s most advanced process nodes.
Leveraging Samsung’s through-silicon via (TSV) technology,
X-Cube enables significant leaps in speed and power efficiency
to help address the rigorous performance demands of next-
generation applications including 5G, artificial intelligence,
high-performance computing, as well as mobile and wearable.
“Samsung’s new 3D integration technology ensures reliable
TSV interconnections even at the cutting-edge
EUV process nodes,” said Moonsoo Kang, senior vice president
of Foundry Market Strategy at Samsung Electronics. “We are
committed to bringing more 3D IC innovation that can push the
boundaries of semiconductors.”
3D Packaging

41. 3D Packaging
*The image shown is for illustration purpose only.
With Samsung’s X-Cube, chip designers can enjoy greater
flexibility to build custom solutions that best suit their unique
requirements.
The X-Cube test chip built on 7nm uses TSV technology to
stack SRAM on top of a logic die, freeing up space to pack
more memory into a smaller
footprint.
Enabled by 3D integration, the ultra-thin package design
features significantly shorter signal paths between the dies for
maximized data transfer
speed and energy efficiency. Customers can also scale the
memory bandwidth and density to their desired specifications.
Samsung X-Cube’s silicon-proven design methodology and flow
are available now for advanced nodes including 7nm and 5nm.

42. Building on the initial
design, Samsung plans to continue collaborating with global
fabless customers to facilitate the deployment of 3D IC
solutions in next-generation high-
performance applications.
More details on Samsung X-Cube will be presented at Hot
Chips, an annual conference on high-performance computing,
livestreamed Aug. 16-18.
eXtended-CubeSamsung X-CubeX-Cube
https://www.hotchips.org/
https://news.samsung.com/global/tag/extended-cube
https://news.samsung.com/global/tag/samsung-x-cube
https://news.samsung.com/global/tag/x-cube
WLP/WCSP & 3D packaging summary
Fundamentals of Wafer chip scale packaging ( Fan -in WCSP)
are
discussed.

43. Wafers scale packaging classifications & processes are dealt
with.
A brief Introduction to 3D packaging is given.