![Electrical Characterization of Etch
Damage in GaN Trench MOSFETS
Junqian Liu, Chirag Gupta, Umesh Mishra
Department of Electrical and Computer Engineering,
University of California, Santa Barbara, CA 93106
Abstract:
As the demand for more energy efficient electronics rises, Galium
Nitride (GaN) is showing great promise for use in next generation
devices. However, bombardment of ions for etching GaN, introduces
detrimental lattice defects due to the energy transferred from the
ions to the GaN crystal structure. To examine the effects of these
defects on device performance, several samples were processed
under ion bombardments of varying power levels. These samples
were then characterized with capacitance-voltage and current-
voltage measurements. From these measurements, it can be
concluded that more powerful ion bombardments will reduce flat
band and threshold voltages of metal-oxide semiconductor (MOS)
devices. By reactive ion etching (RIE) at lower power levels,
transistors can experience less current leakage while operating at
higher voltages thereby reducing the energy consumed when
installed in commercial products.
Objective:
The goal of this research is to support the hypothesis that the
power of RIE used is detrimental to voltage characteristics of
GaN devices. This is accomplished by finding a trend that
correlates higher voltage characteristics of trench metal–oxide
semiconductor field-effect transistors (MOSFETs) when
decreasing etching power levels during its processing.
Methods:
• Samples processed with the same cleanroom techniques[2][3][4]
• Each one exposed to either a 15W, 20W, 25W, 30W ion beam
• Samples’ MOS capacitors measured with a capacitance-
voltage sweeping from -10V to 2V using a two point probe
• Collected data was converted into a 1/C2 curve and analyzed
with the Hilibrand and Gold capacitance-voltage equation (1)
for doping concentrations (ND)[4]
• Flatband capacitance solved by treating oxide capacitance
(Cox) to be in series with the depleted GaN capacitance (CD)
for the following equation (2) when using Debye’s length
• Flatband voltage found by intersecting the CV curve with
flatband capacitance
• Breakdown voltages characterized by sweeping from 0V to
200V and defined as when the capacitor starts conducting
larger amounts of current than usual
Equations:
1. ND=
𝟐
𝒒𝜺 𝒔 𝜺 𝟎 𝑨 𝟐
𝒅
𝟏
𝑪 𝟐
𝒅𝑽
Electron charge (q), GaN semiconductor relative permittivity ε 𝑠 , vacuum
permittivity (ε0), and designed device area (A) are all constants while d(1/C2)/dV
is extrapolated from the CV curves.
2. 𝑪 𝑭𝑩 =
𝟏
𝑪 𝒐𝒙
+
𝟏
𝑪 𝑫
−𝟏
where 𝑪 𝑫 = 𝑨
𝜺 𝒔 𝜺 𝟎 𝒒𝑵 𝑫
𝑽 𝑻
Thermal voltage (VT) at room temperature (300K) is constant while oxide
capacitance (Cox) is the highest capacitance measured in the CV sweep.
References:
[1] Young, Benjamin. “Research Interests - Ion Bombardment." Benjamin Young’s Homepage. N.p., n.d. Web. 31
July 2016. <http://bennyyoung.com/research-interests/ion-bombardment/>
[2] H. Otake, S. Egami, H. Ohta, Y. Nanishi and H. Takasu, “GaN-based trench gate metal oxide semiconductor field
effect transistors with over 100 cm2/(V-s) channel mobility,” Jpn. J. Appl. Phys., vol. 46, no. 25, pp. L599-L601, Jun.
2007. DOI: 10.1143/JJAP.46.L599
[3] H. Otake, K. Chikamatsu, A. Yamaguchi, T. Fujishima and H. Ohta, “Vertical GaN-based trench gate metal oxide
semiconductor field-effect transistors on GaN bulk substrates,” Appl. Phys. Exp., vol. 1, no. 1, pp. 011105-1-
011105-3, Jan. 2008. DOI: 10.1143/APEX.1.011105
[4] T. Oka, Y. Ueno, T. Ina and K. Hasegawa, “Vertical GaN-based trench metal oxide semiconductor field-effect
transistors on a freestanding GaN substrate with blocking voltage of 1.6 kV,” Appl. Phys. Exp., vol. 7, no. 2, pp.
021002-1-021002-3, Jan. 2014. DOI: 10.7567/APEX.7.021002
[5] Hilibrand, J. & Gold, R.D. Determination of impurity distribution in junction diodes from capacitance-voltage
measurements. RCA Review, 21, 245-52, RCA Laboratories, Princeton, NJ, June 1960, 0033-6831
T. Oka, T. Ina, Y. Ueno and J. Nishii, “1.8 mΩ.cm2 vertical GaN-based trench metal–oxide–semiconductor field-effect transistors on
a free-standing GaN substrate for 1.2-kV-class operation,” Appl. Phys. Exp., vol. 8, no. 5, pp. 054101
Acknowledgements:
This work was funded by UCSB’s Edision-McNair Summer Fellowship, SSLEEC, and ARPA-E. Lastly, I would like
to thank my student mentor, Chirag Gupta, and faculty advisor, Umesh Mishra, for their guidance .
Figure 2 Structures of MOSFETs (left) and MOS capacitors
(right) designed for the experiment where a swept voltage
potential is applied to gate (G) with drain (D) grounded. Note
that most of the dry etch damage will be in between the
aluminum oxide (Al2O3) and n--GaN layers.
Conclusions:
Overall the trend found in device testing corresponded with the
initial hypothesis that higher etch power will introduce lattice
defects and negative ions, thus decreasing device efficiency. This
is caused by a reduction in the energy barriers of the GaN
interfaces, resulting in lower breakdown and flatband voltages.
However, the 25W flatband voltage was the only outlier so larger
etch power increments will be used for later experiments to
negate the effects of extraneous variables.
Characterization Results:
Etch Power (W) 15 20 25 30
Breakdown Voltage (V) 113 103 96 88
Flatband Voltage (V) -2.29 -3.03 -2.29 -3.26
Doping ND (cm^-3) 3.38E+15 3.54E+15 3.37E+15 3.55E+15
Figure 1 Ion etching process (left) and resulting surface structure (right).[1]
Figure 3 Raw data for CV sweep with corresponding regions over
operation as controlled by the voltage (left) and its 1/C2 conversion with
line a of best fit on for the slope (right).
Example Graphs for 15W Sample
CFB
VFBVTh
AccumulationInversion Depletion
Cox](https://image.slidesharecdn.com/789ccaad-745b-476c-a115-4b2c83be4a96-161004220835/85/Edison-Poster-1-320.jpg)
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- 1. Electrical Characterization of Etch Damage in GaN Trench MOSFETS Junqian Liu, Chirag Gupta, Umesh Mishra Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 Abstract: As the demand for more energy efficient electronics rises, Galium Nitride (GaN) is showing great promise for use in next generation devices. However, bombardment of ions for etching GaN, introduces detrimental lattice defects due to the energy transferred from the ions to the GaN crystal structure. To examine the effects of these defects on device performance, several samples were processed under ion bombardments of varying power levels. These samples were then characterized with capacitance-voltage and current- voltage measurements. From these measurements, it can be concluded that more powerful ion bombardments will reduce flat band and threshold voltages of metal-oxide semiconductor (MOS) devices. By reactive ion etching (RIE) at lower power levels, transistors can experience less current leakage while operating at higher voltages thereby reducing the energy consumed when installed in commercial products. Objective: The goal of this research is to support the hypothesis that the power of RIE used is detrimental to voltage characteristics of GaN devices. This is accomplished by finding a trend that correlates higher voltage characteristics of trench metal–oxide semiconductor field-effect transistors (MOSFETs) when decreasing etching power levels during its processing. Methods: • Samples processed with the same cleanroom techniques[2][3][4] • Each one exposed to either a 15W, 20W, 25W, 30W ion beam • Samples’ MOS capacitors measured with a capacitance- voltage sweeping from -10V to 2V using a two point probe • Collected data was converted into a 1/C2 curve and analyzed with the Hilibrand and Gold capacitance-voltage equation (1) for doping concentrations (ND)[4] • Flatband capacitance solved by treating oxide capacitance (Cox) to be in series with the depleted GaN capacitance (CD) for the following equation (2) when using Debye’s length • Flatband voltage found by intersecting the CV curve with flatband capacitance • Breakdown voltages characterized by sweeping from 0V to 200V and defined as when the capacitor starts conducting larger amounts of current than usual Equations: 1. ND= 𝟐 𝒒𝜺 𝒔 𝜺 𝟎 𝑨 𝟐 𝒅 𝟏 𝑪 𝟐 𝒅𝑽 Electron charge (q), GaN semiconductor relative permittivity ε 𝑠 , vacuum permittivity (ε0), and designed device area (A) are all constants while d(1/C2)/dV is extrapolated from the CV curves. 2. 𝑪 𝑭𝑩 = 𝟏 𝑪 𝒐𝒙 + 𝟏 𝑪 𝑫 −𝟏 where 𝑪 𝑫 = 𝑨 𝜺 𝒔 𝜺 𝟎 𝒒𝑵 𝑫 𝑽 𝑻 Thermal voltage (VT) at room temperature (300K) is constant while oxide capacitance (Cox) is the highest capacitance measured in the CV sweep. References: [1] Young, Benjamin. “Research Interests - Ion Bombardment." Benjamin Young’s Homepage. N.p., n.d. Web. 31 July 2016. <http://bennyyoung.com/research-interests/ion-bombardment/> [2] H. Otake, S. Egami, H. Ohta, Y. Nanishi and H. Takasu, “GaN-based trench gate metal oxide semiconductor field effect transistors with over 100 cm2/(V-s) channel mobility,” Jpn. J. Appl. Phys., vol. 46, no. 25, pp. L599-L601, Jun. 2007. DOI: 10.1143/JJAP.46.L599 [3] H. Otake, K. Chikamatsu, A. Yamaguchi, T. Fujishima and H. Ohta, “Vertical GaN-based trench gate metal oxide semiconductor field-effect transistors on GaN bulk substrates,” Appl. Phys. Exp., vol. 1, no. 1, pp. 011105-1- 011105-3, Jan. 2008. DOI: 10.1143/APEX.1.011105 [4] T. Oka, Y. Ueno, T. Ina and K. Hasegawa, “Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a freestanding GaN substrate with blocking voltage of 1.6 kV,” Appl. Phys. Exp., vol. 7, no. 2, pp. 021002-1-021002-3, Jan. 2014. DOI: 10.7567/APEX.7.021002 [5] Hilibrand, J. & Gold, R.D. Determination of impurity distribution in junction diodes from capacitance-voltage measurements. RCA Review, 21, 245-52, RCA Laboratories, Princeton, NJ, June 1960, 0033-6831 T. Oka, T. Ina, Y. Ueno and J. Nishii, “1.8 mΩ.cm2 vertical GaN-based trench metal–oxide–semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation,” Appl. Phys. Exp., vol. 8, no. 5, pp. 054101 Acknowledgements: This work was funded by UCSB’s Edision-McNair Summer Fellowship, SSLEEC, and ARPA-E. Lastly, I would like to thank my student mentor, Chirag Gupta, and faculty advisor, Umesh Mishra, for their guidance . Figure 2 Structures of MOSFETs (left) and MOS capacitors (right) designed for the experiment where a swept voltage potential is applied to gate (G) with drain (D) grounded. Note that most of the dry etch damage will be in between the aluminum oxide (Al2O3) and n--GaN layers. Conclusions: Overall the trend found in device testing corresponded with the initial hypothesis that higher etch power will introduce lattice defects and negative ions, thus decreasing device efficiency. This is caused by a reduction in the energy barriers of the GaN interfaces, resulting in lower breakdown and flatband voltages. However, the 25W flatband voltage was the only outlier so larger etch power increments will be used for later experiments to negate the effects of extraneous variables. Characterization Results: Etch Power (W) 15 20 25 30 Breakdown Voltage (V) 113 103 96 88 Flatband Voltage (V) -2.29 -3.03 -2.29 -3.26 Doping ND (cm^-3) 3.38E+15 3.54E+15 3.37E+15 3.55E+15 Figure 1 Ion etching process (left) and resulting surface structure (right).[1] Figure 3 Raw data for CV sweep with corresponding regions over operation as controlled by the voltage (left) and its 1/C2 conversion with line a of best fit on for the slope (right). Example Graphs for 15W Sample CFB VFBVTh AccumulationInversion Depletion Cox
Editor's Notes
- Overall, the poster is organized and looks good. I do have a few comments The poster has a LOT of text on it – in general less is more on posters. For the methods – can you convert this to bullet points? This would make it easier on the person reading it. Maybe something like this… Samples processed using cleanroom technique During etching stage samples exposed to 1 of 4 different types of ion beams (15W, 20W, 25W, or 30W) MOS capacitors measured with capacitance-voltage (from -10v to 2v) Doping concentrations (Nd) measured with equation 1 Flatband Voltage measured with equations 2 and 3? Breakdown voltages measured by sweeping voltage from 0V to 200V. Defined as when the capacitor starts conducting larger amounts of current The equations in the methods section need to be numbered with the definitions in smaller text. I would put all the bullets in one area and the numbered equations at the bottom of the box Objectives How many objectives do you have? If you only have one I would switch the title to Objective. If you have more then 1, I would number them and describe each one in 1 sentence. Put the “By finding this trend…” sentence in the conclusions box Conclusions You never outline your hypotheses – you need to add a box that describes these. You could even combine it with the objective box where you have the main objective stated and the hypothesis/hypotheses under that with the H1, H2 symbols…. You should explicitly state whether you supported or rejected your hypothesis Figures need to be labeled as Figure1, Figure 2, etc… these should be referenced to in the boxes. So when you are describing the trend from Figure 1, you would say “As seen in Figure 1…” For your results table and graph you need to include a title on the table and a caption for the graph. I would make your boxes all circular or all square. It looks weird to have both. You need to leave at least ¼ of an inch at the edge of the poster.