VHDL (Very High-Speed Integrated Circuit Hardware Description Language) is an IEEE standard used to describe and simulate complex digital circuits, offering flexible modeling capabilities and supporting large designs. It has a history dating back to the 1980s, with significant milestones including its adoption as an IEEE standard in 1987 and subsequent updates. VHDL features multiple modeling styles, supports various data types, and is distinguished from Verilog by its ability to define data types and handle multi-dimensional arrays.

1. VHDL
MADE BY MS. MERLYN SYLVESTER,
FACULTY AT DEPARTMENT OF PHYSICS & ELECTRONICS,
INSTITUTE FOR EXCELLENCE IN HIGHER EDUCATION, BHOPAL

2. What is HDL?
• HDL stands for Hardware Description Language. It is a programming
language that is used to describe, simulate, and create hardware like
digital circuits (IC’S). HDL is mainly used to discover the faults in the
design before implementing it in the hardware.
• The main advantage of HDLs is that it provides flexible modeling
capabilities and can express the large complex designs (>107 gates).
• Today, there are many HDLs available in the market,
but VHDL and Verilog are the most popular HDLs.

3. What is VHDL?
VHDL stands for Very High-Speed Integration Circuit HDL (Hardware Description
Language).
It is an IEEE (Institute of Electrical and Electronics Engineers) standard hardware
description language that is used to describe and simulate the behavior of
complex digital circuits.

4. History of VHDL
•1980: The Department of Defense wanted to make circuit design self-documenting.
•1983: The development of VHDL began with a joint effort by IBM, Inter-metrics, and Texas
Instruments.
•1985 (VHDL Version 7.2): The final version of the language under the government contract was
released.
•1987: DOD permitted for commercial purpose, and VHDL became IEEE Standard 1076-1987.
•1993: VHDL was re-standardized to enhance the language
•1996: A VHDL package used with synthesis tools and became a part of the IEEE 1076 standard.
•1999: Analog Mixed Signal extension (VHDL-AMS)
•2008: IEEE Standard 1076-2008 (New features) was released.

5. Traditional vs. Hardware Description
Languages
Procedural programming languages provide the how or recipes
I. for computation
II. for data manipulation
III. for execution on a specific hardware model
Hardware description languages describe a system
Systems can be described from many different points of view
I. Behavior: what does it do?
II. Structure: what is it composed of?
III. Functional properties: how do I interface to it?
IV. Physical properties: how fast is it?

6. VHDL Features
VHDL supports the following features:
I. Design methodologies and their features.
II. Sequential and concurrent activities.
III. Design exchange
IV. Standardization
V. Documentation
VI. Large-scale design
VII. A wide range of descriptive capability

7. Difference between VHDL and Verilog
VHDL Verilog
It allows the user to define data types. It does not allow the user to define data
types.
It supports the Multi-Dimensional array. It does not support the Multi-Dimensional
array.
It allows concurrent procedure calls. It does not allow concurrent calls.
A mod operator is present. A mod operator is not present.
Unary reduction operator is not present. Unary reduction operator is present.
It is more difficult to learn. It is easy to learn.

8. Why VHDL?
VHDL is used for the following purposes:
I. For Describing hardware
II. As a modelling language
III. For a simulation of hardware
IV. For early performance estimation of system architecture
V. For the synthesis of hardware

9. Advantages of VHDL
•It supports various design methodologies like Top-down approach and Bottom-up
approach.
•It provides a flexible design language.
•It allows better design management.
•It allows detailed implementations.
•It supports a multi-level abstraction.
•It provides tight coupling to lower levels of design.
•It supports all CAD tools.
•It strongly supports code reusability and code sharing.

10. Disadvantages of VHDL
•It requires specific knowledge of the structure and
syntax of the language.
•It is more difficult to visualize and troubleshoot a
design.
•Some VHDL programs cannot be synthesized.
•VHDL is more difficult to learn.( not if you are keen)

11. Basic Elements of VHDL
There are the following three basic elements of VHDL:
I. Entity
II. Architecture
III.Configuration

12. Entity
The Entity is used to specify the input and output ports of the
circuit. An Entity usually has one or more ports that can be inputs
(in), outputs (out), input-outputs (inout), or buffer.
An Entity may also include a set of generic values that are used to
declare properties of the circuit.

13. Entity Declaration
entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;
NAME_OF_ENTITY: user defined
signal_names: list of signals (both input and output)
mode: in, out, buffer, inout
type: boolean, integer, character, std_logic

14. Example
entity orgate is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic ;
);
end orgate;

15. Using generic
entity entity_name is
generic (
generic_1_name : data_type;
generic_2_name : data_type;
........
generic_n_name : data_type ;
);
port (
port_1_name : mode data_type;
port_2_name : mode data_type;
........
Port_n_name : mode data_type ;
);
end entity_name;

16. Example
entity Logic_Gates is
generic (Delay : Time := 10ns);
port (
Input1 : in std_logic;
Input2 : in std_logic;
Output : out std_logic;
);
end Logic_Gates;

17. Things to remember
RULES FOR WRITING
PORT NAME
Port name consist of letters, digits, and
underscores.
May contain A-Z, a-z, 0-9, _
It always begins with a letter.
Port name is case insensitive.
May not end with _
May not include two consecutive _
MODES OF PORT
in Input port
out Output port
inout Bidirectional port
buffer Buffered output port

18. Architecture Declaration
architecture architecture_name of entity_name is
begin
(concurrent statements )
end architecture_name;

19. Example
architecture synthesis of andgate is
begin
(
c <= a AND b;
)
end synthesis;

20. Configuration
A configuration defines how the design hierarchy is linked
together. It is also used to associate architecture with an
entity.

21. Configuration Declaration
configuration configuration_name of entity_name is
--configuration declarations
for architecture_name
for instance_label : component_name
use entity library_name.entity_name(architecture_name);
end for;
--
end for;
end [configuration_name];

22. Example
configuration demo_config of even_detector_testbench is
for tb_archi
for uut : even_detector
use entity work.even_detector (sop_archi);
end for;
end for;
end demo_config;

23. Types of Modeling styles in VHDL
There are 4 types of modeling styles in VHDL:
1. Data flow modeling (Design Equations)
Data flow modeling can be described based on the Boolean expression. It shows how the data flows from input to
output. It works on Concurrent execution.
2. Behavioral modeling (Explains Behaviour)
Behavioral modeling is used to execute statements sequentially. It shows that how the system performs according
to the current statement.
Behavioral modeling may contain Process statements, Sequential statements, Signal assignment statements, and
wait statements.
3. Structural modeling (Connection of sub modules)
Structural modeling is used to specify the functionality and structure of the circuit.
Structural modeling contain signal declarations, component instances, and port maps in component instance.
4. Hybrid/ Mixed Modelling

24. Data Types in VHDL
1. Scalar Types
I. Integer :Integer data types are the set of positive and negative whole numbers
II. Floating point: Floating point data types are the set of positive and negative numbers that contain a
decimal point.
III. Enumeration: Enumeration data type is used to increase the readability of the code.
IV. Physical: Physical data type describes objects in terms of a base unit, multiples of base unit, and a
specified range.
2. Composite Types
I. Arrays: Arrays are used to hold multiple values of the same types under a single identifier
II. Records: Records are used to specify one or more elements, and each element has a different name
and different type.

25. Integer Data Type
◦ Minimum range for any implementation as defined by standard: - 2,147,483,647 to
2,147,483,647
◦ Example assignments to a variable of type integer :
ARCHITECTURE test_int OF test IS
BEGIN
PROCESS (X)
VARIABLE a: INTEGER;
BEGIN
a := 1; -- OK
a := -1; -- OK
a := 1.0; -- illegal
END PROCESS;
END test_int;

26. Enumerated
◦ User specifies list of possible values
◦ Example declaration and usage of enumerated data type :
TYPE binary IS ( ON, OFF );
... some statements ...
ARCHITECTURE test_enum OF test IS
BEGIN
PROCESS (X)
VARIABLE a: binary;
BEGIN
a := ON; -- OK
... more statements ...
a := OFF; -- OK
... more statements ...
END PROCESS;
END test_enum;

27. Real
◦ Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38
◦ Example assignments to a variable of type real :
ARCHITECTURE test_real OF test IS
BEGIN
PROCESS (X)
VARIABLE a: REAL;
BEGIN
a := 1.3; -- OK
a := -7.5; -- OK
a := 1; -- illegal
a := 1.7E13; -- OK
a := 5.3 ns; -- illegal
END PROCESS;
END test_real;

28. Physical
◦ Require associated units
◦ Range must be specified
◦ Time is the only physical type predefined in VHDL standard
◦ Example of physical type declaration :
TYPE resistance IS RANGE 0 TO 10000000
UNITS
ohm; -- ohm
Kohm = 1000 ohm; -- i.e. 1 KW
Mohm = 1000 kohm; -- i.e. 1 MW
END UNITS;

29. Booleans
type boolean is (false, true);
variable A,B,C: boolean;
C := not A
C := A and B
C := A or B
C := A nand B
C := A nor B
C := A xor B
C := A xnor B

30. Bits
type bit is (‘0’, ‘1’);
signal x,y,z: bit;
x <= ‘0’;
y <= ‘1’;
z <= x and y;

31. Standard Logic
library IEEE;
use IEEE.std_logic_1164.all;
type std_ulogic is ( ‘U’, -- Uninitialized
‘X’ -- Forcing unknown
‘0’ -- Forcing zero
‘1’ -- Forcing one
‘Z’ -- High impedance
‘W’ -- Weak unknown
‘L’ -- Weak zero
‘H’ -- Weak one
‘-’); -- Don’t care

32. VHDL Operators
1. Logical Operators
Logical Operators are used to control the program flow. When the logical operators
combined with signals or variables, then it is used to create combinational logic.
VHDL supports the following logical operators:
I. and
II. or
III. nand
IV. nor
V. xnor
VI. not
VII. xnor

33. VHDL Operators
2. Relational Operators
In VHDL, relational operators are used to compare two operands of the same data type,
and the received result is always of the Boolean type.
VHDL supports the following Relational Operators:
I. = Equal to
II. /= Not Equal to
III. < Less than
IV. > Greater than
V. <= Less than or equal to
VI. >= Greater than or equal to

34. VHDL Operators
3. Arithmetic Operators
Arithmetic Operators are used to perform arithmetic operations. These operators are numeric types, such as integer and real.
VHDL uses the following Arithmetic Operators:
I. + Addition
II. - Subtraction
III. * Multiplication
IV. / Division
V. & Concatenation
VI. mod Modulus
VII. rem Remainder
VIII. abs Absolute Value
IX. ** Exponentiation

35. VHDL Operators
4. Shift Operators
In VHDL, shift operator is used to perform the bit manipulation on the data by shifting
and rotating the bits of its first operand right or left.
VHDL supports the following Miscellaneous Operators:
I. Sll shift logical left
II. Srl shift logical right
III. Sla shift arithmetic left
IV. Sra shift arithmetic right
V. Rol rotate left
VI. Ror rotate right

36. VHDL Operators
I. <= Signal assignment operator

37. Structural Model
•Digital circuits consist of components and interconnection between them.
•A component can in turn be composed of sub-components and their
interconnections.
•A component interacts with other components through pins.
•Component is modeled as entity.
•Component pins are modeled as ports.
•Interconnections between components are modeled as signals.

38. Behavioral Model
•The behavior of a component is modeled inside an architecture body of the
entity
•It may be described using a collection of concurrently executing statements
•A concurrent statement is sensitive to a set of input signals and is executed
whenever any of its sensitive signal changes its value
•A concurrent statement called process statement can contain one or more
sequential statements
•A set of sequential statements can be clubbed together in a subprogram

39. Dataflow Model
•The flow of data through the entity is modelled primarily using concurrent
signal assignment statements.
•The structure of the entity is not explicitly specified but it can be implicitly
deduced.
Architecture MYARCH of MYENT is
begin
SUM <= A xor B after 8ns;
end MYARCH;

40. Example-1
entity Xor_gate is
port (in1, in2 : in bit; Out1 : out bit);
end Xor_gate ;
architecture behavioral of Xor_gate is
begin
process
begin
Out1 <= In1 xor In2;
wait on In1, in2;
end process;
end behavioral;

41. Example-2
entity Adder is
port ( A : in Bit;
B : in Bit;
Sum : out Bit;
Cout : out Bit );
end Adder;
architecture Behavioral_Desc of Adder is
begin
process (A, B)
Sum <= A or B;
Cout <= A and B;
end process;
end Behavioral_Desc