Dss

1. EE800, U of S 1
Decimal Floating-Point Arithmetic
Kasi Bandla

2. EE800, U of S 2
Objectives
• IEEE 754-2008 standard for Decimal
Floating-Point (DFP) arithmetic (Lecture 1)
– DFP numbers formats
– DFP number encoding
– DFP arithmetic operations
– DFP rounding modes
– DFP exception handling

3. EE800, U of S 3
Objectives (Con.)
• Algorithm, architecture and VLSI circuit
design for DFP arithmetic (Lecture 2)
– DFP adder/substracter
– DFP multiplier
– DFP divider
– DFP transcendental function computation

4. EE800, U of S 4
Background
The decimal computer arithmetic went out
of style 25 to 30 years ago; no one uses it
now." Is that true?

5. EE800, U of S 5
Introduction
• Decimal is still essential for specific applications
– Numbers in commercial databases are decimal
– Extensive use decimal in commercial applications
– Survey of commercial databases report
– Decimal fixed-point or floating-point number
• How to process decimal computation
– Software computation
– Convert back to decimal representation
– Problems

6. EE800, U of S 6
Introduction (Con.)
• Errors from decimal and binary conversion
– Example 1: represent 0.1 in DFP or BFP
Decimal representation (BCD code):0.0001
Binary representation: 0.00011… 0.09…
– Example 2: telephone billing Cost: 0.70; Tax: 5%
BFP arithmetic: 0.6999…8*(1.05)=0.734999…
DFP arithmetic: 0.70*(1.05)=0.74
• Decimal integer, fixed-point or floating-point?
• Decimal hardware or software solutions?

7. EE800, U of S 7
• DFP arithmetic defined in IEEE 754-2008
• IBM computing systems include DFP hardware
– IBM Power6, z9, z10
• Intel include DFP software solution in system
– Intel DFP software computation library
• DFP arithmetic IP blocks:
– Basic DFP arithmetic IPs:
DFP adder/substrcter, multiplier, divider, square root etc.
– Transcendental DFP arithmetic IPs:
DFP CORDIC, Logarithm, antilogarithm, reciprocal etc.
Current Researches

8. EE800, U of S 8
DFP Arithmetic in IEEE 754-2008
• Review BFP arithmetic in IEEE 754-2008
• How to define new DFP in IEEE 754-2008

9. EE800, U of S 9
BFP Floating-point representation
• Representation:
– sign, exponent, significand (or mantissa):
(–1)sign × significand × 2exponent
– more bits for significand gives more accuracy
– more bits for exponent increases range
• IEEE 754 floating point standard:
– single precision: 8 bit exponent, 23 bit significand
– double precision: 11 bit exponent, 52 bit significand

10. EE800, U of S 10
BFP floating-point Number
•Leading “1” bit of significand is implicit
–Example: if the significand is 011010110…0, the
actual significand is 1.011010110…0
•This is called a normalized number; there is
exactly one non-zero digit to the left of the
point.
–Unique representation of a number
–We get a little more precision: there are 24 bits in
the significand, but only 23 of them are stored.

11. EE800, U of S 11
Exponent
• Exponent is “biased” to make sorting easier
– all 0s is smallest exponent, all 1s is largest
– The actual exponent is e-127 for single precision, and
e-1023 for double precision
– Bias of 127 for single precision and 1023 for double
precision
– By biasing the exponent and storing it before the
significand, we can compare magnitudes as if they were
unsigned integers.
• If e = 1000 0011 (13110), the actual exponent is 131-127=4
• If e = 0101 1101 (9310), the actual exponent is 93-127=-34

12. EE800, U of S 12
BFP Floating-Point Formats
Short (32-bit) format
Long (64-bit) format
Sign Exponent Significand
8 bits,
bias = 127,
–126 to 127
11 bits,
bias = 1023,
–1022 to 1023
52 bits for fractional part
(plus hidden 1 in integer part)
23 bits for fractional part
(plus hidden 1 in integer part)

13. EE800, U of S 13
BFP Floating-Point Formats (Con.)
Negative
Overflow
Positive
Overflow
Expressible
negative
numbers
Expressible
positive
numbers
0
-2-127 2-127
Positive underflow
Negative underflow
(2 – 2-23)×2128
- (2 – 2-23)×2128
00000000 00000000000000000000000
Biased
exponent
Fraction
Positive and
negative zero
11111111 00000000000000000000000
Biased
exponent
Fraction
1
1
0
0
Positive and
negative infinity
exponent = 128 and fraction ≠ 0, It is called “not a number” or NaN
0
∞

14. EE800, U of S 14
Example
• Summary: FP representation
(–1)sign×(1+significand)×2exponent – bias
• Example:
– decimal: -.75 = -3/4 = -3/22
– binary: -.11 = -1.1 x 2-1
– floating point: exponent = 126 = 01111110
– IEEE single precision:
1 01111110 10000000000000000000000

15. EE800, U of S 15
• Representation:
– sign, exponent, significand (or mantissa):
(–1)sign × significand × 10exponent
– more digits for significand gives more accuracy
– more bits for exponent increases range representation:
• DFP formats:
– decimal32: DFP storage format encoded in 32-bit
– decimal64: DFP computational format encoded in 64-bit
– decimal128: DFP computational format encoded in 128-bit
DFP Number Representation

16. EE800, U of S 16
DFP Number format
• 1-bit Sign (S) is defined as same as BFP format
• w+5-bit combination (G) to two subfield:
– 5-bit (G0…G4) to encode: 2 MSBs of exponent; 1 MSD of
significand; Not-a-Number (NaN); Inf;
– W-bit(G5…Gw+4) as a suffix 2 MSBs derived from G0…G4,
which consists of w+2-bit nonnegative biased exponent.

17. EE800, U of S 17
DFP Exponent
• Exponent is “biased” to make sorting easier
– Binary format (not decimal)
– The actual exponent is e-101 for decimal32, e-398 for
decimal64, e-6167 for decimal128
– Range of exponent is (emin−q+1) ≤ e ≤ (emax−q+1);

18. EE800, U of S 18
DFP Number format (Con.)
• J×10-bit Trailing Significand (T) Field:
– Densely packed decimal (DPD) encoding
3-digit decimal number encoded to 10-bit binary number
DPD converted to binary coded decimal (BCD)
– Binary integer decimal (BID) encoding
decimal number encoded by binary integer
– Non-normalized decimal significand
(-1)0 × 0.00900 × 102 (-1)0 × 0.09000 × 101
– DFP number’s Cohort

19. EE800, U of S 19
Parameters in DFP Format

20. EE800, U of S 20
Example
• Summary: DFP representation
• (–1)sign×(significand)×10exponent-bias
• Convert -8.35×10-2 to decimal64
– Sign bit: “1” negative, “0” positive (sign 1)
– Exponent: -2+398=396 (8-bit “0110001100”)
– Significand: 835(50-bit DPD coding “0…00 02 3D”)
– Encoding of 5-bit MSBs (G0…G4) of Combinational
field “01000”
– Decimal-64 : “10100010001100…..00…1000111101”
“A2 30 00 00 00 00 02 3D” (binary/hex)

21. EE800, U of S 21
• Not-a-Number: G0…G4 “11111”;
• Infinite Number: G0…G4 “11110”, sign of Inf
according to the sign bit;
• Overflow: If DFP numbers with absolute values are
larger than the largest DFP number (|vmax|=(10q
-
1)×10emax-q+1
) then overflow occurs.
• Underflow: If DFP number are less than the smallest
DFP number (|vmin|=10emin-q+1
) then underflow
occurs. If the absolute value of DFP number is less
than 10emin
and larger than 10emax-q+1
, it produces
subnormal.
• Normal number: The remaining exponent values and
significands represent normal numbers.
DFP special values

22. EE800, U of S 22
• Basic DFP arithmetic operations
• Two decimal-specific DFP operations
– SameQuantum(DFP1,DFP2)
– Quantize(DFP1,DFP2)
• DFP comparison operations
– do not distinguish between redundant of the same
number
• DFP conversion operations
– DFP to BFP conversion (correctly rounded);
– DFP to integer conversion
• Recommended DFP operations
DFP Arithmetic Operations

23. EE800, U of S 23
• Basic DFP arithmetic operations
• Two decimal-specific DFP operations
– SameQuantum(DFP1,DFP2)
– Quantize(DFP1,DFP2)
• DFP comparison operations
– do not distinguish between redundant of the same
number
• DFP conversion operations
– DFP to BFP conversion (correctly rounded);
– DFP to integer conversion
• Recommended DFP operations
DFP Arithmetic Operations

24. EE800, U of S 24
• Non-normalized decimal significand
• DFP number’s Cohort
• Standard defines the preferred (required) exponent
(quantum)
– Exact operation results: the cohort member is selected
based on the preferred exponent (quantum) for a DFP
result of that operation
– Inexact operation results: the cohort member of least
possible exponent is used to get the maximum number of
significant digits
DFP Number’s Cohort

25. EE800, U of S 25
• Five types of active rounding modes
– roundTiesToEven
– roundTiesToAway
– roundTiesToPositive
– roundTiesToNegative
– roundTowardZero
• Correct rounding and Faithful rounding
• IEEE 754-2008 require to satisfy the correct
rounded results for all DFP arithmetic operations
• DFP operations should satisfy all rounding modes
DFP Rounding Modes

26. EE800, U of S 26
• Invalid operation: Operand is NaN; 0×Inf; quare-
root of negative operand; default result is NaN
• Division by zero: if the dividend is a finite non-zero
number and the divisor is zero. The default result is
a +inf or −inf.
• Overflow operation: if the magnitude of a result
exceeds the largest finite number representable in
the format of the operation.
• Underflow operation: if the magnitude of a result is
below 10emin
.
• Inexact: the correctly rounded result of an operation
differs from the infinite precision result.
DFP Exception Handling

27. EE800, U of S 27
DFP Addition/Subtraction

28. EE800, U of S 28
DFP Add/Sub Data flow

29. EE800, U of S 29
• Step 1: equalize the exponents
– add the mantissas only when exponents are the
same.
– the number with smaller exponent should be
shifting its point to the left, and the number with
larger exponent should be shifting its point to
right.
– Rewriting the operand with the smaller exponent
could result in a loss of the least significant digits
– keep guard digit, round digit, and stick digit for
the operand with smaller exponent
DFP Addition

30. EE800, U of S 30
DFP addition
• Step 2: add the mantissas
0099999x101
+0016234x10-3
0999990x100
0000016(234)x100
1000006(234) x100
• Step 3: Normalize the result if necessary

31. EE800, U of S 31
DFP addition
• Step 4: Round the number if needed
1000006234x100 =1000006x100
• Step 5: Repeat step 3 if the result is no
longer normalized
• The final result is 1000006
• The correct answer is 1000006.234

32. EE800, U of S 32
Guard bits
• To help minimize rounding problems, IEEE
specifies that intermediate steps of
operations must store guard digits -
additional internal digits that increase the
precision of the operations.
• Previous example: add one extra digit.
• IEEE 754-2008 requires one guard digit,
one rounded digit and one sticky digit to
make rounding more accurate.

33. EE800, U of S 33
DFP add/sub

34. EE800, U of S 34
General Description: Addition

35. EE800, U of S 35
Example: Addition

36. EE800, U of S 36
Example: Addition (Con.)

37. EE800, U of S 37
DFU: IBM POWER6 and Z10

38. EE800, U of S 38
High performance Implementation

39. EE800, U of S 39
High performance Implementation

40. EE800, U of S 40
High performance Implementation
[12] A. Vázquez and E. Antelo“A
High-performance Significand BCD
Adder with IEEE 754-2008 Decimal
Rounding” ARITH19, Portland. June
08-10 2009

41. EE800, U of S 41
Evaluation Results and Comparison
[Proposed]: A. Vázquez and E. Antelo“A High-performance Significand BCD
Adder with IEEE 754-2008 Decimal Rounding” ARITH19, Portland. June
08-10 2009

42. EE800, U of S 42
DFP Multiplication

43. EE800, U of S 43
Scheme of decimal multiplier
x : 1 9 6 3 ×
y : 8 1 4 5 =
xy0: 5x 9 8 1 5
0 0 0 0 0
xy1: 5x 9 8 1 5
−x - 1 9 6 3
xy2 : x 1 9 6 3
0 0 0 0 0
xy3: 10x 1 9 6 3 0
−2x - 3 9 2 6
1 5 9 8 8 6 3 5

44. EE800, U of S 44
Partial product generation
Generate XYi
Yi {1,2,3…7,8,9}
XYi is carry save format

45. EE800, U of S 45
Partial product generation
Solid Circles: BCD Sum (digit)
Hollow Circles: Carry (bit)
n-digit radix-10 CSA
m-digit radix-10 counter

46. EE800, U of S 46
Carry Save Adder Tree
CSA Tree to Generate
Multiplication Result

47. 47
Flowchart of DFP Multiplier

48. 48
Architecture of DFP Multiplier

49. 49
Exception Detection & Handling
• Invalid operation
– sNaN (pass significand of sNaN)
– 0 x ∞ (produce qNaN with significand 0)
• Overflow (and Inexact)
– IEIP – SLA > Emax
– Increase SLA until all LZs removed
• Underflow (and possibly Inexact)
– IEIP – SLA < Emin
– Decrease SLA until 0, then shift right
• Inexact

50. 50
Implementation Highlights
• Leverage operands' LZCs
– SC, SLA, and IESIP
• Handle NaNs with minimal overhead
– No dataflow modification
– Coerce multiplicand or multiplier to 1
• Support gradual underflow
– No dataflow modification
– Simply extend number of iterations
• Simple, control-based rounding scheme

51. 51
Synthesis Results
• 64-bit (16 digit) operands, DPD encoded
• LSI Logic's gflxp 0.11um CMOS, 55ps FO4
• Synopsys Design Compiler
• Results
– Fixed-point 119,653 um2 14.72 FO4s
– Floating-point 237,607 um2 15.45 FO4s
• Critical path
– Fixed-point 4:2 compressor (accumulator)
– Floating-point 128-bit barrel shifer

52. 52
Applicability to Parallel Designs
• IE and IP shift generation
• Rounding scheme
• NaN handling
• Exception detection and handling
• On-the-fly sticky bit generation... NO

53. 53
Sequential vs. Parallel
• Sequential
– Less area
– Potentially better cycle time
• Parallel
– Less latency
– Higher throughput

54. EE800, U of S 54
DFP Division

55. EE800, U of S 55
DFP Division Data Flow
Combinational Field
(5 bits)
Significands Field (50bits)
Sign (1 bit)
64 64
Sign Logic
Exponent
Substraction
Bias Addition
Exponent
Adjustment
Exponent
Adjustment
Mantissa Division
Normalization
Rounding
Unpacking
Rounding
Control
F
1
10
S1
1
1
S2
Sq
E2_b
E1_b
E12
1
8 8
10
11
Eb
Eq 8
Ea
1
Fa
72
M12
Mn
Fr
1
1
Fa2
72
64
Mq
64
Exponent Field (8 bits)
Combinational Field
(5 bits)
Significands Field (50 bits)
Sign (1 bit) packing
Exponent Field (8 bits)
Combinational
Div Process
5
5
10
C1 C2
2
E1_a
Combin_Register
2
E2_a
E2
E1 10 10
Combin_Register
DPD_to_BCD
M2_b
M1_b 50 50
M2_b
M1_b 60 60
4
4
M2_a
M1_a
M2
M1 64 64
Mn
72
Combinational
Com Process
Significand_Div
BCD_to_DPD
60
Mq
Mq
50
Exponent Div
10
Ea
2
Eq_C
4
Mq_C
5
Cq
• Unpacking
Decimal Floating-
Point Number
• Check for zeros
and infinity
• Subtract
exponents
• Divide Mantissa
• Normalize and
detect overflow
and underflow
• Perform rounding
• Replace sign
• Packing

56. EE800, U of S 56
Unpacking and Sign Logic
• Step1: Unpacking Floating-Point Number
Check for zeros and infinity (if F=0, Stop)
Sign Logic
1
S1 S2
1
Sq
1
• Step2: Sign Process
1 2
q
S S S
 
Combinational Field
(5 bits)
Significands Field (50bits)
Sign (1 bit)
64 64
Unpacking
Exponent Field (8 bits)

57. EE800, U of S 57
Exponent Subtraction
Exponent
Substraction
E2
E1
E12
11 11
11
Bias Addition
11
Eb
• Step3: Exponent Subtract
1 2
b
E E E bias
  +

58. EE800, U of S 58
Mantissa Division
Mantissa Division
M1 M2
64 64
68
M12
• Step4: Mantissa Division
1
0.1 1
M
  2
0.1 1
M
 
min 0.1
M  max 1 10 1
p
M 
  
min max 1 2 max min
0.1 / / / 10
M M M M M M
   
Algorithms Choose here?
1. Restoring division
2. Non-restoring division
3. High-Radix division
4. Convergence division

59. EE800, U of S 59
Normalization
• Step5 : Left shift over one bit is
needed to make Mantissa result
Normalized, also need to detect
overflow and underflow
Normalization
68
M12
Fa
1
68
Mn
Exponent
Adjustment
10
Eb
10
Ea
For example: “0934…2140819564” Left shift one bit 
“934…21408195640 Should tell exponent and Ea=Eb-1

60. EE800, U of S 60
Rounding and Packing
Rounding
Control
68
Rounding
Mn
Fr
68
1
Exponent
Adjustment
64 Mq
1
Fr
Ea
10
Eq
10
• Step6 : Truncate, Round-up, Round-to-nearest.
Sometimes, the Rounding Policy above is not fair,
according to IEEE Rounding standard: “Round to nearest
even” is more better.
• Step7: Packing the Sign bit and Exponent bits and
Significand bits together, detect the NaN, Infinity,
11
Eb M12
64
Combinational Field
(5 bits)
Significands Field (50 bits)
Sign (1 bit) packing
Exponent Field (8 bits)

61. EE800, U of S 61
High performance Implementation
[1] L.-K. Wang and M. J. Schulte, “Decimal Floating-Point Division Using Newton-Raphson
Iteration,” Proceedings of the IEEE International Conference on Application-Specific Systems,
Architectures and Processors, pp. 84-95, Sep. 2004.

62. EE800, U of S 62
High performance Implementation
[2] Tomás Lang and Alberto Nannarelli, “A Radix-10 Digit-Recurrence Division Unit: Algorithm and
Architecture,”IEEE Transactions on Computers, pp727–739, IEEE, June 2007.

63. EE800, U of S 63
High performance Implementation

64. EE800, U of S 64
Evaluation Results and Comparison
1: Synthesized with a STM 90-nm standard cell library
DFP Divider[1] DFP Divider[2]
Precision (digit) 16 (decimal64) 16 (decimal64)
Cycle time (ns) 0.57 1
# of cycles 150 20
Latency (ns) 85.5 20

65. EE800, U of S 65
DFP Transcendental Arithmetic

66. EE800, U of S 66
Contents
• Introduction
• Decimal Logarithmic Converter
• Decimal Antilogarithmic Converter
• Conclusions
• Future Work

67. EE800, U of S 67
32-bit DFP Logarithm
10 10 10
log ( ) log (10 ) log ( )
e
R X coefficient
  +
( 1) 10
s e
X coefficient
   
coefficient is a non-normalized decimal Integer.
To guarantee a 32-bit DFP Calculation, there need to
keep 14-digit FXP logarithmic calculation.
Example: 0 8
10
log (( 1) 10 0024589)
R    
10
8 5 log (0.2458900)
 + +

68. EE800, U of S 68
32-bit DFP Antilogarithm
10
log ( ) 10X
P Anti X
 
10 min 10 max
log ( ) log ( )
X X X
 
10
log ( ) 10 10 10 frac
Int Frac Int
X
X X X
Anti X  
  
Here:
For 32-bit DFP: [ 101,96.99999]
X  
Example:
1 5
10
log (( 1) 1940467 10 )
Anti 
  
19 0.4046700
10
log (19.40467) 10 10
Anti  
To guarantee a 32-bit DFP calculation, there need to
keep 8-digit FXP antilog calculation.

69. EE800, U of S 69
Digit-Recurrence Algorithm (Log)
The corresponding recurrences:
( 1) [ ](1 10 )
j
j
E j E j e 
+  +
10
( 1) [ ] log (1 10 )
j
j
L j L j e 
+   +
Here: [1]
E m
 [1] 0
L 
j
e ( 1)
E j +
selected so that converges to 1
ej ∈｛-9 -8 -7…0 1…7 8 9｝

70. EE800, U of S 70
Digit-Recurrence Algorithm (Antilog)
Any 7-digit fixed-point decimal input N:
( ) ln(10) '
10 e
m m m
e
 
The corresponding recurrences:
Here: [1] 1
E  [1] '
L m

j
e ( 1)
L j +
selected so that converges to 0
( 1) [ ] ln(1 10 )
j
j
L j L j e 
+   +
( 1) [ ] (1 10 )
j
j
E j E j e 
+   +
1 10 j
i j
f e 
 +
ej ∈｛-9 -8 -7…0 1…7 8 9｝

71. EE800, U of S 71
Selection By Rounding (cont.)
A scaled remainder is defined as:
[ ] 10 (1 [ ])
j
W j E j
 
j
e is achieved by Rounding W [j]
( [ ])
j
e round W j

e1 is achieved by using look-up table, e2…ej can
be obtained with selection by rounding
Log:
Antilog: [ ] 10 ( [ ])
j
W j E j


72. EE800, U of S 72
Architecture: Decimal Log Converter
Detector
Reg 1
28
Mult1
28
m
m2m 3m5m
56
32
8
2
m'
“0000”
4
e1
Mult2
Mux 2
Mux 1
4
56
56
56
Mux 3
56
Mux 4
1
56
14-Digit Decimal CLA Adder
56
56
56
9'sCom
56
14-Digit Dec CLA
56
Rounding Logic
4
56
4
ej
56
Shifter (x10) Shifter (x100)
56
Mux 6
56
4ej
ej
m' W[j]
56
m'
W[j]
Shifter (x10-j)
Mux 5
56
56
56
Tab II Mult3
Mux 8
(1/ln(10))
16-Digit Dec CLA
Mux 9
0 &
Mux
7
Stage 2
4
4
4
64 64
56
64
64
64
64
4
64
ej
e1
Log 10(5,2,3)
Stage 1
Reg
3
4
Reg 2
Reg 4
Reg
5
W[j]
Reg 6
Adjusted Costant
critical path
9'sCom
“0000”
56
Tab I
4
e1
8

73. EE800, U of S 73
Implementation Results
Logic Utilization Used Available* Utilization
# of Occupied Slices 2842 13696 21%
Maximum Frequency 47.7 MHz
# of Clock Cycles 17 clock cycle
*: Xilinx Virtex2p XC2VP30 with package ff1157 and speed -7
Critical Path Detail (ns):
Reg2 Mux2 Mult 2 Shifter Mux5 CLA Round Total
1.188 1.564 9.347 1.438 1.350 5.519 0.566 20.97

74. EE800, U of S 74
Architecture: Dec. Antilog Converter
Reg 2
TAB I
12
8
e1
AddGen
40
Mux 1
7
TABLE II
7
Shifter (x10j+1)
40
9'sCom
9'sCom
40 40
Mux 2
Mux 3
40
10-digit Dec CLA
40
40
Rounding Logic
40
Shifter_Reg
40
40
Reg 3
W[j]
4 ej
AddGen
7
4 ej
40
ej
“0000”
4
Stage 1
40
Stage 2
e1 ‘1’
Shifter (x10-j)
4
Mult
40
40
40
40
40 40
40
40
Reg 6
40
ej
Mux 4
“0000”
10-digit Dec CLA
Mux 5
m'
Critical Path
Reg 5
28
28
Final Rounding
L(j)
Reg 1
28
40
28
Cons Mul
28
32
“0000”
ln(10)
frac
X

75. EE800, U of S 75
Implementation Results
Logic Utilization Used Available* Utilization
# of Occupied Slices 2315 13696 17%
Maximum Frequency 51.5 MHz
# of Clock Cycles 11 clock cycle
*: Xilinx Virtex2p XC2VP30 with package ff1157 and speed -7
Critical Path Detail (ns):
Reg6 Mult Mux4 Shifter CLA Round Total
1.599 7.839 1.539 1.100 6.794 0.545 19.42

76. EE800, U of S 76
Comparison
(with Binary FXP Log and Exponential Converters)
• similar dynamic range for the normalized coefficients.
• Binary reference available having the same digit-
recurrence algorithm with Selection by Rounding.
• The radix-10 is close to radix-8.
52 16 53
2 10 2
 
23 7 24
2 10 2
 

77. EE800, U of S 77
Comparison (cont.)
(with Binary FXP Log and Exponential Converters)
1: Synthesized with a TMSC 0.18-um standard cell library
2: the area of 1-bit full adder
3: the delay of 1-bit full adder
Radix-10 Decimal1 Radix-8 Binary [1]
Log. Exp. Log. Exp.
Precision (digit) 7 16 7 16 24 53 24 53
Area (fa2) 1630 2640 1370 2260 647 1829 627 1777
Cycle time (T3) 17 19 16 18 7 8 7 8
# of cycles 8 17 8 17 8 18 11 21
Latency (T3) 136 323 128 306 56 144 77 168

78. EE800, U of S 78
Conclusions
• Achieved 32-bit DFP accuracy of decimal log and
antilog results.
• Implemented them on FPGA and ASIC.
• Compare them with binary converters.

79. EE800, U of S 79
EE990 April. 2009 79/18
Decimal Log and Antilog Converters
Future Work
• The 64-bit and 128-bit DFP logarithm and antilog
converters.
• The presented architecture can be optimized to
achieve a faster speed or occupy a smaller area.

80. EE800, U of S 80
Summary
• IEEE 754-2008 defines a DFP standard that
defines
– number representation in several precisions
– correct DFP arithmetic operations
– rounding modes
• Implementation of DFP Adder, Multiplier, Divider,
Logarithmic and Antilogarithmic Converter
• Implementing and programming DFP are both
really hard.