Yaron Aharoni has over 20 years of experience in senior hardware engineering roles involving chip design, architecture development, RTL implementation, verification, synthesis, timing analysis, and more. He has worked at companies such as DSPC, Intel, and Marvell on projects including the development of a WB-CDMA modem and post-silicon debugging and yield improvement.

1. Yaron Aharoni
229 Nahal Yeela St, Eshtaol 9977500
Home: 02-5870614 - Cell: 054-4301243 - Email: yaron.riki@gmail.com
Summary
Senior Hardware Engineer with 20 years experience in chip design, including HW architecture
development, RTL implementation and verification, Synthesis and Timing Analysis, Design for FPGA,
Multi Power domain designs, Power Management and Power Analysis, Multi Clocks designs and SOC
Clock Management, DFT leading, Post Silicon Debug and Yield Improvement.
Experience and Accomplishments
Senior chip design developer and technical leader 1998 – Current
DSPC / Intel / Marvell (DSPC was acquired by Intel in 2000, and re-acquired by Marvell in 2006)
 I was part of the construction crew of the WB-CDMA project. Responsible for the TX modem,
including HLD, detailed design, RTL coding, Testing and guidance.
 Developed infrastructure for automatic testing, and led verification team for the WB project.
 Led DFT activities and DFT team for a couple of years.
Defined DFT methodology, Design flow, rules definition, and was a focal point for DFT Guidance.
Managed activities such as – Scan (stuck & at-speed), JTAG Control, MBIST. PBIST, BS, IO's,
Monitoring and Debugging capabilities, RTL and gate-level validation, ATPG and STA.
 I was relocated one year at USA for post-silicon assistance. Mainly focused on Debugging, Failure
Analysis and Yield Improvement – for our products. (2005 – 2006)
 Learned and evaluated Power Analysis tools. Wrote a set of interface scripts, and defined a power
analysis flow for our designs.
 Used to be a design mentor for my colleagues, and provided ideas and directions for different cases.
 Throughout the past years I was responsible for Power management, Clock management, Fuse
Control and Security – along with a series of products.
Wrote PMU's and CCU's for complex chips with multi power domains and dynamic voltage.
Defined methodology for clock generation and clock management.
Developed solutions for Frequency-Change-On-The-Fly, PLL's control, Shared Resources Voting
Management, Register files, Wakeup mechanisms, State-Machines, JTAG and Debugging capabilities
with secure protection, inter-chips wakeup and power interface, App-SS, Comm-SS, Audio, GPS, DAP
and Tracing control, VCTCXO (Primary clock) control, Resets management and more.
 Wrote Fuse controller that manages the Fuse voltages for Read/Write, downloads the fuse data,
supports SW and JTAG access, and provides high level of protection mechanism.
 Took a part in different task forces, analysed and improved timing, performance and routing issues.
 Taught, instructed and worked in synchronization with parallel teams (System, SW, Verification,
Synthesis, BE, SV, PE) relating to our design solutions and capabilities.
Logic design developer 1995 – 1998
Softchip LTD. Jerusalem
 Developed and wrote RTL code for 8/16bit Micro-controller.
In this role (at a small startup company) – I was responsible for the front-end steps of this product,
including – HLD, RTL coding, Simulations, Synthesis, STA, and metal fix (ECO).
 Wrote a Firewall design for FPGA (XILINX).
Skills
Thorough and professional, ambitious, creative, imaginative and tend to be perfectionist.
Collaborative team player and technical leader.
Education and Training
 B.Sc in Computer Engineering, Israeli Technion - 1995
 Took various courses and seminars for EDA tools (Mentor, Synopsys, Cadence).
Attended conferences and exhibitions (DAC, ESNUG …)
 Received trainings in social and management skills.