This document contains the resume of Ching-Tsun Chou, who has almost 20 years of experience in computer architecture, hardware-software interfaces, performance modeling, and simulation and formal verification. He is looking for a position that utilizes his experience to improve system design and verification processes. His skills include computer architecture, cache coherence protocols, simulation, formal verification, and programming. He has worked at Intel and Fujitsu Labs of America and holds a Ph.D from UCLA.

1. Ching-Tsun Chou
Email: chingtsun.chou@gmail.com Mobile: (650) 283-4894
Web: http://www.linkedin.com/in/chingtsunchou Work: (408) 765-5468
Home: (650) 813-0251
Goal
Having almost 20 years of deep and diverse experiences in many aspects of
computer architecture, hardware-software interface, performance modeling,
and both simulation-based and formal verification, I am looking for a position
which can take advantage of my experiences to improve the architecting, design,
and verification process of complex systems for high quality and short time-to-market.
Skill Set
• Hands-on experiences in: Computer architecture in both processor core and
uncore subsystems; performance modeling; cache coherence protocol design,
specification, and verification; analysis of intricate protocol issues such as
deadlock and starvation avoidance and memory ordering; simulation-based
functional verification, formal verification; RTL coding; FPGA prototyping; binary
translation-based emulation; modification of QEMU internals; multi-core
programming; low-level programming with assembly; translators from one
language to another; debugging complex software.
• Languages: C/C++ (with embedded assembly), Python, Objective Caml, Verilog
and SystemVerilog, x86-64 ISA, Murphi, SMV, HOL.
• Tools: Git, Simics, QEMU, FeS2, Asim, Synopsys VCS, Verdi, Synplify, Xilinx ISE,
Auspy ACE.
Industry Experience
Intel Corporation
• Jan 2013 to now: Designing (register and memory) region atomicity
mechanisms for an out-of-order processor core to support binary
translation. Responsible for defining and specifying memory ordering
semantics for atomic regions and using it to prove the correctness of
code optimization transformations in binary translation. Exploring
microarchitectural design alternatives through performance

2. simulation. Coding and debugging of a complex simulation
infrastructure involving multiple ISAs and binary translation.
• 2010 to 2012: Developed a multi-threaded full-system simulator in
which each virtual CPU is executed by a separate host thread and can
dynamically switch between fast functional simulation based on
QEMU binary translation and slower but cycle-accurate performance
simulation of speculative out-of-order processors. The simulator can
run unmodified Debian Linux and workloads in a virtual machine.
• 2008 to 2010: Led the effort of building a 20-node FPGA-based full-system
emulator comprising Intel MIC Knights Ferry cores on a 4x5
mesh/torus-based interconnect and demoed the emulator at 2010
Intel Developer Forum in San Francisco. The emulator ran a version
of Linux and several visual computing related workloads. Also
involved in the discussion which finally led to the memory ordering
spec in x86 Software Developer’s Manual, volume 3.
• 2005 to 2008: Responsible for the cache coherence protocol chapter
of Intel QuickPath Interconnect specification. Revamped the chapter
by introducing a table-based specification methodology that has since
been adopted by other projects at Intel. Responsibilities included the
specification, verification, and evolution of the protocol spec based
on inputs from both internal and external customers, and the
generation and maintenance of validation collaterals (such as
executable reference models).
• 2000 to 2005: Worked with product design teams on validating RTL
implementation against protocol specifications by using both
simulation and formal techniques. Developed and verified several
cache coherence and other protocols which were not productized.
Analyzed several error correction or detection codes and wrote an
internal tutorial on CRC (cyclic redundancy check).
• 1997 to 2000: Worked in the formal verification team of the Merced
processor design project and used both formal verification and
simulation techniques to find bugs in the RTL of a processor front-end
unit and the bus cluster. Wrote verification coverage monitors.
Fujitsu Labs of America
• 1995 to 1997: Designed an Esterel-like synchronous language based
on interval temporal logic and developed a translation from this
language to synchronous circuits.

3. Education
University of California, Los Angeles - Los Angeles, CA
Ph.D. and M.S. in Computer Science
National Taiwan University - Taipei, Taiwan
B.S. in Electrical Engineering
Online Courses
• Coursera, Cryptography I, taught by Dan Boneh of Stanford University, Sep 2014
Statement of Accomplishment (Grade: 100% with Distinction)
• Coursera, GPS: An Introduction to Satellite Navigation, taught by Per Enge and
Frank van Diggelen of Stanford University, Dec 2014
Ongoing
Patents
6 granted and 2 pending: https://sites.google.com/site/chingtsunchou/patents
Publications
Downloadable PDFs: https://sites.google.com/site/chingtsunchou/publications
Google Scholar: http://scholar.google.com/citations?hl=en&user=ufGYoL0AAAAJ
Awards
• One of 2005 Mahboob Khan Outstanding Mentor Awards from SRC (Silicon
Research Corporation), which recognize individuals who demonstrate
outstanding commitment and effectiveness in facilitation of university research,
mentoring of graduate students, and dissemination of knowledge and research
results to industry.
Miscellaneous
• Citizenship: U.S.A.
• Erdös Number = 2 (http://www.oakland.edu/enp/)