Time and efforts for functional testing of digital logic is big chunk of overall project cycle in VLSI industry. Progress of functional testing is measured by functional coverage where test-plan defines what needs to be covered, and test-results indicates quality of stimulus. Claiming closer of functional testing requires that functional coverage hits 100% of original test-plan. Depending on the complexity of the design, availability of resources and budget, various methods are used for functional testing. Software simulations using various logic simulators, available from Electronic Design Automation (EDA) companies, is primary method for functional testing. The next level in functional testing is pre-silicon verification using Field Programmable Gate Array (FPGA) prototype and/or emulation platforms for stress testing the Design Under Test (DUT). With all the efforts, the purpose is to gain confidence on maturity of DUT to ensuresfirst time silicon success that meets time to market needs of the industry. For any test-environment the bottleneck, in achieving verification closer, is controllability and observability that is quality of stimulus to unearth issues at early stage and coverage calculation. Software simulation, FPGA prototype, or emulation, each method has its own limitations, be it test-time, ease of use, or cost of software, tools and
hardware-platform. Compared to software simulation, FPGA prototyping and emulation methods pose greater challenges in quality stimulus generation and coverage calculation. Many researchers have identified the problems of bug-detection / localization, but very few have touched the concept of quality stimulus generation that leads to better functional coverage and thereby uncover hidden bugs in FPGA prototype verification setup. This paper presents a novel approach to address above-mentioned issues by embedding synthesizable active-agent and coverage collector into FPGA prototype. The proposed architecture has been experimented for functional and stress testing of Universal Serial Bus (USB) Link Training and Status State Machine (LTSSM) logic module as DUT in FPGA prototype. The proposed solution is fully synthesizable and hence can be used in both software simulation as well as in prototype system. The biggest advantage is plug and play nature of this active-agent component, that allows its reusability in any USB3.0 LTSSM digital core.
Network Function Modeling and Performance EstimationIJECEIAES
This work introduces a methodology for the modelization of network functions focused on the identification of recurring execution patterns as basic building blocks and aimed at providing a platform independent representation. By mapping each modeling building block on specific hardware, the performance of the network function can be estimated in terms of maximum throughput that the network function can achieve on the specific execution platform. The approach is such that once the basic modeling building blocks have been mapped, the estimate can be computed automatically for any modeled network function. Experimental results on several sample network functions show that although our approach cannot be very accurate without taking in consideration traffic characteristics, it is very valuable for those application where even loose estimates are key. One such example is orchestration in network functions virtualization (NFV) platforms, as well as in general virtualization platforms where virtual machine placement is based also on the performance of network services offered to them. Being able to automatically estimate the performance of a virtualized network function (VNF) on different execution hardware, enables optimal placement of VNFs themselves as well as the virtual hosts they serve, while efficiently utilizing available resources.
Black Box Model based Self Healing Solution for Stuck at Faults in Digital Ci...IJECEIAES
The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.
Systematic Model based Testing with Coverage AnalysisIDES Editor
Aviation safety has come a long way in over one
hundred years of implementation. In aeronautics, commonly,
requirements are Simulink Models. Considering this, many
conventional low level testing methods are adapted by various
test engineers. This paper is to propose a method to undertake
Low Level testing/ debugging in comparatively easier and
faster way. As a first step, an attempt is made to simulate
developed safety critical control blocks within a specified
simulation time. For this, the blocks developed will be utilized
to test in Simulink environment. What we propose here is
Processor in loop test method using RTDX. The idea is to
simulate model (requirement) in parallel with handwritten
code (not a generated one) running on a specified target,
subjected to same inputs (test cases). Comparing the results
of model and target, fidelity can be assured. This paper suggests
a development workflow starting with a model created in
Simulink and proceeding through generating verified and
profiled code for the processor.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Advanced Verification Methodology for Complex System on Chip VerificationVLSICS Design
Verification remains the most significant challenge in getting advanced SOC devices in market. The
important challenge to be solved in the Semiconductor industry is the growing complexity of SOCs.
Industry experts consider that the verification effort is almost 70% to 75% of the overall design effort.
Verification language cannot alone increase verification productivity but it must be accompanied by a
methodology to facilitate reuse to the maximum extent under different design IP configurations. This
Advanced reusable test bench development will decrease the time to market for a chip. It will help in code
reuse so that the same code used in sub-block level can be used in block level and top level as well that
helps in saving cost for a tape-out of a chip. This test bench development technique will help us to achieve
faster time to market and will help reducing the cost for the chip up to a large extent.
Network Function Modeling and Performance EstimationIJECEIAES
This work introduces a methodology for the modelization of network functions focused on the identification of recurring execution patterns as basic building blocks and aimed at providing a platform independent representation. By mapping each modeling building block on specific hardware, the performance of the network function can be estimated in terms of maximum throughput that the network function can achieve on the specific execution platform. The approach is such that once the basic modeling building blocks have been mapped, the estimate can be computed automatically for any modeled network function. Experimental results on several sample network functions show that although our approach cannot be very accurate without taking in consideration traffic characteristics, it is very valuable for those application where even loose estimates are key. One such example is orchestration in network functions virtualization (NFV) platforms, as well as in general virtualization platforms where virtual machine placement is based also on the performance of network services offered to them. Being able to automatically estimate the performance of a virtualized network function (VNF) on different execution hardware, enables optimal placement of VNFs themselves as well as the virtual hosts they serve, while efficiently utilizing available resources.
Black Box Model based Self Healing Solution for Stuck at Faults in Digital Ci...IJECEIAES
The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.
Systematic Model based Testing with Coverage AnalysisIDES Editor
Aviation safety has come a long way in over one
hundred years of implementation. In aeronautics, commonly,
requirements are Simulink Models. Considering this, many
conventional low level testing methods are adapted by various
test engineers. This paper is to propose a method to undertake
Low Level testing/ debugging in comparatively easier and
faster way. As a first step, an attempt is made to simulate
developed safety critical control blocks within a specified
simulation time. For this, the blocks developed will be utilized
to test in Simulink environment. What we propose here is
Processor in loop test method using RTDX. The idea is to
simulate model (requirement) in parallel with handwritten
code (not a generated one) running on a specified target,
subjected to same inputs (test cases). Comparing the results
of model and target, fidelity can be assured. This paper suggests
a development workflow starting with a model created in
Simulink and proceeding through generating verified and
profiled code for the processor.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Advanced Verification Methodology for Complex System on Chip VerificationVLSICS Design
Verification remains the most significant challenge in getting advanced SOC devices in market. The
important challenge to be solved in the Semiconductor industry is the growing complexity of SOCs.
Industry experts consider that the verification effort is almost 70% to 75% of the overall design effort.
Verification language cannot alone increase verification productivity but it must be accompanied by a
methodology to facilitate reuse to the maximum extent under different design IP configurations. This
Advanced reusable test bench development will decrease the time to market for a chip. It will help in code
reuse so that the same code used in sub-block level can be used in block level and top level as well that
helps in saving cost for a tape-out of a chip. This test bench development technique will help us to achieve
faster time to market and will help reducing the cost for the chip up to a large extent.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
A VNF modeling approach for verification purposesIJECEIAES
Network Function Virtualization (NFV) architectures are emerging to increase networks flexibility. However, this renewed scenario poses new challenges, because virtualized networks, need to be carefully verified before being actually deployed in production environments in order to preserve network coherency (e.g., absence of forwarding loops, preservation of security on network traffic, etc.). Nowadays, model checking tools, SAT solvers, and Theorem Provers are available for formal verification of such properties in virtualized networks. Unfortunately, most of those verification tools accept input descriptions written in specification languages that are difficult to use for people not experienced in formal methods. Also, in order to enable the use of formal verification tools in real scenarios, vendors of Virtual Network Functions (VNFs) should provide abstract mathematical models of their functions, coded in the specific input languages of the verification tools. This process is error-prone, time-consuming, and often outside the VNF developers’ expertise. This paper presents a framework that we designed for automatically extracting verification models starting from a Java-based representation of a given VNF. It comprises a Java library of classes to define VNFs in a more developer-friendly way, and a tool to translate VNF definitions into formal verification models of different verification tools.
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
Abstract
Now a day’s many VLSI designers are implementing different applications on real time with the use of FPGAs. Although they are
working efficiently, they are not achieving their expected goals. This is only because of the faults which are occurring in the
FPGA at the runtime of the application. Those faults are remaining in the circuitry as there is no provision for removal of those
faults at application level. So there is a great need of detection & removal of faults. Mainly Interconnect faults, Logical Faults
and Delay are the faults which reduces the performance of FPGA. Although the manufacturers are trying to decrease the fault
present in the FPGA, it is very necessary to remove those faults at run time of the particular application. This paper includes the
brief discussion about the occurrence of different faults and various methods to remove those faults.
Key Words: Fault diagnosis, field-programmable gate array (FPGA), testing.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Functional Verification of Large-integers Circuits using a Cosimulation-base...IJECEIAES
Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer‘s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.
TEST-COST-SENSITIVE CONVOLUTIONAL NEURAL NETWORKS WITH EXPERT BRANCHESsipij
It has been proven that deeper convolutional neural networks (CNN) can result in better accuracy in many
problems, but this accuracy comes with a high computational cost. Also, input instances have not the same
difficulty. As a solution for accuracy vs. computational cost dilemma, we introduce a new test-cost-sensitive
method for convolutional neural networks. This method trains a CNN with a set of auxiliary outputs and
expert branches in some middle layers of the network. The expert branches decide to use a shallower part
of the network or going deeper to the end, based on the difficulty of input instance. The expert branches
learn to determine: is the current network prediction is wrong and if the given instance passed to deeper
layers of the network it will generate right output; If not, then the expert branches stop the computation
process. The experimental results on standard dataset CIFAR-10 show that the proposed method can train
models with lower test-cost and competitive accuracy in comparison with basic models.
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
Verification of the protection services in antivirus systems by using nusmv m...ijfcstjournal
In this paper, a model of protection services in the antivirus system is proposed. The antivirus system
behavior separate in to preventive and control behaviors. We extract the properties which are expected
from the model of antivirus system approach from control behavior in the form of CTL and LTL temporal
logic formulas. To implement the behavior models of antivirus system approach, the ArgoUML tool and the
NuSMV model checker are employed. The results show that the antivirus system approach can detects
fairness, reachability, deadlock free and verify some properties of the proposed model verified by using
NuSMV model checker.
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan
designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper
proposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely used
communication protocol for emulation, and an FPGA-based emulation platform. A high-level (SystemC)
testbench and FPGA synthesizable hardware transactor models are developed for the scan-chain ISCAS89
S400 benchmark circuit for high-speed communication between the host CPU workstation and the FPGA
emulator. The emulation results are compared to other verification methodologies (RTL Simulation,
Simulation Acceleration, and Transaction-based emulation), and found to be 82% faster than regular RTL
simulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of software
applications, drivers, and operating systems, as opposed to the Hz range in RTL simulation or submegahertz
range as accomplished in transaction-based emulation. In addition, the integration of scan
testing and acceleration/emulation platforms allows more complex DFT methods to be developed and
tested on a large scale system, decreasing the time to market for products.
DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTUREVLSICS Design
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. Reliability and process variability are serious issues for FPGAs in the future. With advancement in process technology, the feature size is decreasing which leads to higher defect densities, more sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield.
System reliability is an important issue in designing modern multiprocessor systems. This paper proposes a fault-tolerant, scalable, multiprocessor system architecture that adopts a pipeline scheme. To verify the performance of the proposed system, the SimEvent/Stateflow tool of the MATLAB program was used to simulate the system. The proposed system uses twelve processors (P), connected in a linear array, to build a ten-stage system with two backup processors (BP). However, the system can be expanded by adding more processors to increase pipeline stages and performance, and more backup processors to increase system reliability. The system can automatically reorganize itself in the event of a failure of one or two processors and execution continues without interruption. Each processor communicates with its neighboring processors through input/output (I/O) ports which are used as bypass links between the processors. In the event of a processor failure, the function of the faulty processor is assigned to the next processor that is free from faults. The fast Fourier transform (FFT) algorithm is implemented on the simulated circuit to evaluate the performance of the proposed system. The results showed that the system can continue to execute even if one or two processors fail without a noticeable decrease in performance.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
A VNF modeling approach for verification purposesIJECEIAES
Network Function Virtualization (NFV) architectures are emerging to increase networks flexibility. However, this renewed scenario poses new challenges, because virtualized networks, need to be carefully verified before being actually deployed in production environments in order to preserve network coherency (e.g., absence of forwarding loops, preservation of security on network traffic, etc.). Nowadays, model checking tools, SAT solvers, and Theorem Provers are available for formal verification of such properties in virtualized networks. Unfortunately, most of those verification tools accept input descriptions written in specification languages that are difficult to use for people not experienced in formal methods. Also, in order to enable the use of formal verification tools in real scenarios, vendors of Virtual Network Functions (VNFs) should provide abstract mathematical models of their functions, coded in the specific input languages of the verification tools. This process is error-prone, time-consuming, and often outside the VNF developers’ expertise. This paper presents a framework that we designed for automatically extracting verification models starting from a Java-based representation of a given VNF. It comprises a Java library of classes to define VNFs in a more developer-friendly way, and a tool to translate VNF definitions into formal verification models of different verification tools.
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
Abstract
Now a day’s many VLSI designers are implementing different applications on real time with the use of FPGAs. Although they are
working efficiently, they are not achieving their expected goals. This is only because of the faults which are occurring in the
FPGA at the runtime of the application. Those faults are remaining in the circuitry as there is no provision for removal of those
faults at application level. So there is a great need of detection & removal of faults. Mainly Interconnect faults, Logical Faults
and Delay are the faults which reduces the performance of FPGA. Although the manufacturers are trying to decrease the fault
present in the FPGA, it is very necessary to remove those faults at run time of the particular application. This paper includes the
brief discussion about the occurrence of different faults and various methods to remove those faults.
Key Words: Fault diagnosis, field-programmable gate array (FPGA), testing.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Functional Verification of Large-integers Circuits using a Cosimulation-base...IJECEIAES
Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer‘s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.
TEST-COST-SENSITIVE CONVOLUTIONAL NEURAL NETWORKS WITH EXPERT BRANCHESsipij
It has been proven that deeper convolutional neural networks (CNN) can result in better accuracy in many
problems, but this accuracy comes with a high computational cost. Also, input instances have not the same
difficulty. As a solution for accuracy vs. computational cost dilemma, we introduce a new test-cost-sensitive
method for convolutional neural networks. This method trains a CNN with a set of auxiliary outputs and
expert branches in some middle layers of the network. The expert branches decide to use a shallower part
of the network or going deeper to the end, based on the difficulty of input instance. The expert branches
learn to determine: is the current network prediction is wrong and if the given instance passed to deeper
layers of the network it will generate right output; If not, then the expert branches stop the computation
process. The experimental results on standard dataset CIFAR-10 show that the proposed method can train
models with lower test-cost and competitive accuracy in comparison with basic models.
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
Verification of the protection services in antivirus systems by using nusmv m...ijfcstjournal
In this paper, a model of protection services in the antivirus system is proposed. The antivirus system
behavior separate in to preventive and control behaviors. We extract the properties which are expected
from the model of antivirus system approach from control behavior in the form of CTL and LTL temporal
logic formulas. To implement the behavior models of antivirus system approach, the ArgoUML tool and the
NuSMV model checker are employed. The results show that the antivirus system approach can detects
fairness, reachability, deadlock free and verify some properties of the proposed model verified by using
NuSMV model checker.
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan
designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper
proposes a methodology to decrease scan-chain verification time utilizing SCE-MI, a widely used
communication protocol for emulation, and an FPGA-based emulation platform. A high-level (SystemC)
testbench and FPGA synthesizable hardware transactor models are developed for the scan-chain ISCAS89
S400 benchmark circuit for high-speed communication between the host CPU workstation and the FPGA
emulator. The emulation results are compared to other verification methodologies (RTL Simulation,
Simulation Acceleration, and Transaction-based emulation), and found to be 82% faster than regular RTL
simulation. In addition, the emulation runs in the MHz speed range, allowing the incorporation of software
applications, drivers, and operating systems, as opposed to the Hz range in RTL simulation or submegahertz
range as accomplished in transaction-based emulation. In addition, the integration of scan
testing and acceleration/emulation platforms allows more complex DFT methods to be developed and
tested on a large scale system, decreasing the time to market for products.
DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTUREVLSICS Design
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. Reliability and process variability are serious issues for FPGAs in the future. With advancement in process technology, the feature size is decreasing which leads to higher defect densities, more sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield.
System reliability is an important issue in designing modern multiprocessor systems. This paper proposes a fault-tolerant, scalable, multiprocessor system architecture that adopts a pipeline scheme. To verify the performance of the proposed system, the SimEvent/Stateflow tool of the MATLAB program was used to simulate the system. The proposed system uses twelve processors (P), connected in a linear array, to build a ten-stage system with two backup processors (BP). However, the system can be expanded by adding more processors to increase pipeline stages and performance, and more backup processors to increase system reliability. The system can automatically reorganize itself in the event of a failure of one or two processors and execution continues without interruption. Each processor communicates with its neighboring processors through input/output (I/O) ports which are used as bypass links between the processors. In the event of a processor failure, the function of the faulty processor is assigned to the next processor that is free from faults. The fast Fourier transform (FFT) algorithm is implemented on the simulated circuit to evaluate the performance of the proposed system. The results showed that the system can continue to execute even if one or two processors fail without a noticeable decrease in performance.
First Steps Toward Scientific Cyber-Security Experimentation in Wide-Area Cyb...DETER-Project
Abstract: Steps towards an environment for repeatable and scalable experiments on wide-area cyber-physical systems. The cyber-physical systems that underlie the world's critical infrastructure are increasingly vulnerable to attack and failure. Our work has focused on secure and resilient communication technology for the electric power grid, a subset of the general cyber-physical problem. We have demonstrated tools and methodology for experimentation with GridStat, a middleware system designed to provide enhanced communication service for the grid, within the DeterLab cyber-security testbed. Experiment design tools for DeterLab and for GridStat will ease the creation and execution of relatively large experiments, and they should make this environment accessible to users inexperienced with cluster testbeds. This abstract presents brief overviews of DeterLab and of GridStat and describes their integration. It also describes a large scale GridStat/DeterLab experiment.
For more information, visit: http://www.deter-project.org
Detailed Simulation of Large-Scale Wireless NetworksGabriele D'Angelo
WiFra is a new framework for the detailed simulation of very large-scale wireless networks. It is based on the parallel and distributed simulation approach and provides high scalability in terms of size of simulated networks and number of execution units running the simulation. In order to improve the performance of distributed simulation, additional techniques are proposed. Their aim is to reduce the communication overhead and to maintain a good level of load-balancing. Simulation architectures composed of low-cost Commercial-Off-The-Shelf (COTS) hardware are specifically supported by WiFra. The framework dynamically reconfigures the simulation, taking care of the performance of each part of the execution architecture and dealing with unpredictable fluctuations of the available computation power and communication load on the single execution units. A fine-grained model of the 802.11 DCF protocol has been used for the performance evaluation of the proposed framework. The results demonstrate that the distributed approach is suitable for the detailed simulation of very-large scale wireless networks.
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxfaithxdunce63732
CS 301 Computer Architecture
Student # 1
E
ID: 09
Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
Student # 2
H
ID: 09
Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
1
1. Introduction
High-performance processor design has recently taken two distinct approaches. One approach is to increase the execution rate by increasing the clock frequency of the processor or by reducing the execution latency of the operations. While this approach is important, much of its performance gain comes as a consequence of circuit and layout improvements and is beyond the scope of this research. The other approach is to directly exploit the instruction-level parallelism (ILP) in the program and to issue and execute multiple operations concurrently. This approach requires both compiler and microarchitecture support.
Traditional processor designs that issue and execute at most one operation per cycle are often called scalar designs. Static and dynamic scheduling techniques have been used to achieve better-than scalar performance by issuing and executing more than one operation per cycle. While Johnson[7] defines a superscalar processor as a design that achieves better-than scalar performance, popular usage of this term refers exclusively to those processors that use dynamic scheduling techniques. For clarity, we use instruction-level parallel processors to refer to the general class of processors that execute more than one operation per cycle of the computer both at the personal level, or the level of a small network of computers to do not require more of these types.
The primary static scheduling technique uses the compiler to determine sets of operations that have their source operands ready and have no dependencies within the set. These operations can then be scheduled within the same instruction subject only to hardware resource limits. Since each of the operations in an instruction is guaranteed by the compiler to be independent, the hardware is able to is- sue and execute these operations directly with no dynamic analysis. These multi-operation instructions are very long in comparison with traditional single-operation instructions and processors using .
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
COVERAGE DRIVEN FUNCTIONAL TESTING ARCHITECTURE FOR PROTOTYPING SYSTEM USING SYNTHESIZABLE ACTIVE AGENT
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
DOI : 10.5121/vlsic.2018.9304 41
COVERAGE DRIVEN FUNCTIONAL TESTING
ARCHITECTURE FOR PROTOTYPING SYSTEM USING
SYNTHESIZABLE ACTIVE AGENT
Dipakkumar Modi and Usha Mehta
EC Department, Institute of Technology, Nirma University, Ahmedabad, India
ABSTRACT
Time and efforts for functional testing of digital logic is big chunk of overall project cycle in VLSI industry.
Progress of functional testing is measured by functional coverage where test-plan defines what needs to be
covered, and test-results indicates quality of stimulus. Claiming closer of functional testing requires that
functional coverage hits 100% of original test-plan. Depending on the complexity of the design, availability
of resources and budget, various methods are used for functional testing. Software simulations using
various logic simulators, available from Electronic Design Automation (EDA) companies, is primary
method for functional testing. The next level in functional testing is pre-silicon verification using Field
Programmable Gate Array (FPGA) prototype and/or emulation platforms for stress testing the Design
Under Test (DUT). With all the efforts, the purpose is to gain confidence on maturity of DUT to ensures
first time silicon success that meets time to market needs of the industry. For any test-environment the
bottleneck, in achieving verification closer, is controllability and observability that is quality of stimulus to
unearth issues at early stage and coverage calculation. Software simulation, FPGA prototype, or
emulation, each method has its own limitations, be it test-time, ease of use, or cost of software, tools and
hardware-platform. Compared to software simulation, FPGA prototyping and emulation methods pose
greater challenges in quality stimulus generation and coverage calculation. Many researchers have
identified the problems of bug-detection / localization, but very few have touched the concept of quality
stimulus generation that leads to better functional coverage and thereby uncover hidden bugs in FPGA
prototype verification setup. This paper presents a novel approach to address above-mentioned issues by
embedding synthesizable active-agent and coverage collector into FPGA prototype. The proposed
architecture has been experimented for functional and stress testing of Universal Serial Bus (USB) Link
Training and Status State Machine (LTSSM) logic module as DUT in FPGA prototype. The proposed
solution is fully synthesizable and hence can be used in both software simulation as well as in prototype
system. The biggest advantage is plug and play nature of this active-agent component, that allows its
reusability in any USB3.0 LTSSM digital core.
KEYWORDS
Testing, Functional Coverage, Synthesizable Active Agent, Universal Serial Bus (USB), Link Training and
Status State Machine (LTSSM)
1. INTRODUCTION
In recent times the complexity of the VLSI designs has increased rapidly with advancements in
nanotechnology and gate capacity from million gates to billion gates in a chip. High-speed serial
communication interfaces such as USB and PCIe provides high data transfer capabilities which is
a need of modern era applications. In cycle accurate and time-based software simulations, the
testing-time becomes bottleneck while running iterative simulations to achieve functional
coverage and detect bugs in time, and overall it affects project schedule
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
42
The next level of verification with prototyping and emulation systems provide accelerated
verification platforms to run time-sensitive scenarios. For high-speed serial protocols, there are
two time-sensitive test areas; a) link-training and low power phase b) data-transfer phase.
Verification in FPGA prototyping system greatly help stressing out the DUT with heavy data
traffic stimulus and reduces the test-time for long and iterative simulations. The DUT can be
simulated by injecting heavy data-traffic with different types of data, and number of data-packets
with varying length to uncover more corner scenarios. The data transfer test-scenarios are driven
from higher-level in the prototyping system, where user has better controllability and
observability for closed-loop testing and hence proper functional coverage can be realized.
However, for link-training related test scenarios there is very limited access where generating
right stimulus and achieving functional coverage is a big challenge.
The USB3.0 LTSSM, many other standard protocols, has timers ranging from 10 µsec to 300
msec for link-training or low power state transitions. Stress testing and coverage for such huge
time sensitive scenarios is herculean task in software simulation, and its unreachable in standard
prototype system. This paper proposes architecture where time-sensitive link-training and low
power states logic is targeted with an embedded active-agent in prototype system that uses
advanced error injection. In a proposed architecture, the active agent controls the stimulus and
coverage collector provides observability for closed-loop functional testing of such time-sensitive
scenarios. The technique used in this architecture focuses on stress testing time sensitive LTSSM
transition arcs and mutation coverage where injected error is observed for predictable behaviour
of DUT. This approach is feasible for many such prototyping systems where lower layers of DUT
can be stress tested using synthesizable active-agent such as proposed in this paper.
2. BACKGROUND AND MOTIVATION OF RESEARCH
In a typical test-environment of prototyping system, traffic injection to DUT is done in two ways;
a) through a test-component b) using a standard real device.
For USB designs when the DUT is USB target device, the test-component at other end could be a
proprietary hardware from Electronic Design Automation (EDA) company, that mimic real USB-
host component. The DUT in such emulated system may run at slower operating clock and sees
the test-component as protocol compliant device at the other end. Such test-components provide
greater flexibility in generating desired stimulus. However, these high-end proprietary test-
components are costly, and interface requirements with DUT are complex. Moreover, if multiple
USB components exist in a system, multiple such test-components would be required to stress test
the system concurrently.
Prototyping system with a real device against a DUT is comparatively easy to build and cost
effective. Such test setup also helps early software development and testing with real components.
The advantage is that all the testing happens in real world and at-speed. The drawback is
controllability of stimulus as the other end of the DUT is actual device where it behaves as per the
protocol defined. In such prototyping system heavy data-traffic can be injected with upper layer
application control. For USB link, when the DUT is USB target device and other end of the link
is real USB-Host, host side application can inject various types of transfers and data traffic.
However, there is very minimum control over how the lower layer of the design is stimulated.
Lower level module for USB-target device is link layer logic with LTSSM. Also, negative testing
options are very limited. Now, here is where the opportunity lies for improvement in the
prototyping system that became motivation of our research work.
The architecture presented here provides controllability of stimulus with synthesizable active-
agent and observability with coverage collector for link-layer LTSSM of the USB3.0 target
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
43
device DUT. The prototype of the proposed architecture is operational and presents promising
results with better stimulus generation. The scope of improvement and future work is to reduce
resource overhead in the prototyping system to provide competitive edge to this approach. The
same approach is feasible for many such prototyping systems where lower layers of design can be
stress tested using synthesizable active-agent such as proposed in this paper.
3. RELATED WORK
Authors from academia and industry have researched in area of pre-silicon verification,
synthesizable test-components, controlled stimulus, issue detection, and coverage collection. All
the work relates to improving effectiveness of testing and its suitability to specific application.
F. Moraes et al. in the paper [1], “A generic FPGA emulation framework” perfectly highlights
challenges associated with software-simulation based testing and proposes generic emulation
framework to improve controllability and observability of design under verification (DUV). The
presented structure is combination of software and hardware components. It uses host-PC for
higher level control of stimuli and the tests are driven to DUV via standard interfaces like PCIe or
Ethernet.
S. S. Shankar et al. in paper [2], “Synthesizable Verification IP to Stress Test System On-Chip
Emulation and Prototyping Platforms”, authors have highlighted the challenges associated with
pre-silicon verification and proposed synthesizable verification architecture compliant with
Standard Co-Emulation Modelling Interface (SCE-MI) infrastructure through which the protocol
specific traffic is injected at industry standard interfaces. This approach is based on combination
of high-level test sequences and protocol specific transactors implemented with synthesizable
models. The paper presents the approach with USB2 logic with Transceiver Macrocell Interface
(UTMI) interface as design under test. This approach highly relies on directed testing and the
stimulus is controlled from higher layer test-sequences.
H. Krrikyan et al. in paper [3], “Prototyping system for USB3.0 link layer using synthesizable
assertions and partial reconfiguration”, presents problems related to bug detection/localization
and coverage calculation. The proposed solution is based on embedding synthesizable assertions
into prototype and the experiment was done on USB3.0 link layer FPGA prototype. The paper
focuses on observability aspect of verification with assertion-based testing in prototype system.
Synthesizable assertions allow its usability in both software-based simulation test-environment
and FPGA prototype /emulation platforms. The experiment utilizes FPGA partial configuration
feature for Xilinx architecture-based FPGA and tool set.
O. Amin et al. proposes an architecture in paper [4], “System Verilog Assertions Synthesis Based
Compiler”, helps assertion-based verification idea for prototyping systems. The non-synthesizable
code written as SystemVerilog Assertions (SVA) in software-simulation based test-environment
can be converted to synthesizable code that can be ported on FPGA. Again, this approach focuses
on observability part of DUT verification and is used to watch how the design performs in testing
setup.
A. Yehia et al. in paper [5], "Faster coverage closure: Runtime guidance of Constrained Random
stimuli by collected coverage” proposes closed-loop verification concept to improve the coverage
and make verification more efficient. This approach is targeted for software simulation based
functional testing where stimuli based on constrained random verification uses data from
coverage collector to optimize the testing run time. It shows how collected coverage can
dynamically guide random stimuli generators during simulation to generate uncovered scenarios
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
44
and avoid generating redundant ones. Similar concept is applied in our architecture for the
prototyping system.
4. PROPOSED ARCHITECTURE
Presented in Figure 1. is use case showing active agent placement in overall FPGA prototype
system. The prototyping system on Xilinx Kintex®-7 FPGA, constitutes USB3.0 Device
controller as DUT, the application layer of DUT is supported by standard mass storage device
driver running on local processor with Advance Microcontroller Bus Architecture (AMBA) -
Advanced eXtensible Interface (AXI) based system-bus. The link layer of DUT connects to
USB3.0 PHY via intel PHY Interface for PCIe and USB (PIPE). The other side of the USB link is
standard host with USB3.0 host port that generates stimulus while running real bulk-transfer
application. Building such prototyping system is easy and cost effective compared to protocol
specific high-end emulators or test-components. The objective of our prototyping system is to
address time sensitive stimulus generation and stress test the DUT. Here data intensive traffic is
injected from standard USB host and the application can inject desired stimulus. To address
stimulus generation for lower layer logic area, LTSSM in this case, the synthesizable active agent
plays a role.
The synthesizable active-agent design is based on Universal Serial Bus (USB) specification [6]
and PIPE [7] specification. The configuration space access of the USB device IP core is accessed
through AXI-Lite interface that follows AMBA-AXI specification [8]. The active agent intercepts
the PIPE interface signalling of USB3.0 link layer and injects error to create specific test scenario
that otherwise wouldn’t have occurred in normal prototype test-environment setup.
USB
PHY
USB3.0 Device IP Core (DUT)
LTSSM
Link Layer
Protocol
Layer
Application
Layer
System with
USB Device-
driver
PIPE interface
Xilinx Zynq FPGA platform
USB3cable
Standard
USB3.0 Host
Active
AgentConfig
Space
Figure 1. Active-agent in prototyping system for USB3 LTSSM
The link Layer interface with PHY is Intel PIPE interface having unidirectional data-flow that
allows adding pipe-line stages to insert our active-agent, without affecting specification timing
requirements. The active-agent is placed on the receive path at upstream port (USP) PIPE
interface where USB3.0 Device IP core connects with standard USB3.0-PHY.
This active agent is a plug-and-play component and work with any USB3.0 controller DUT with
just knowledge about the core’s LTSSM current state value that is available as part of debug port
in typical FPGA prototype system. The active-agent maintains scenario coverage information and
accordingly injects anomaly at available opportunity in an ongoing test. For simplicity This paper
focuses on specific portion of LTSSM and the same would be extended to cover more scenarios
for stress testing of complete LTSSM in an automated way.
In traditional simulation-based verification architecture there are passive agents acting as protocol
checker, scoreboard data collector, or functionality monitors that are vital components in overall
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
45
closed-loop verification. Also, call-back mechanism is used to inject error in the transfer by
manipulating the information and thus, creating specific directed scenario. Similarly, active-agent
manipulates information, within specification boundaries, at standard interface thereby deviating
from standard state-transition of DUT. It is obvious that this active-agent needs some extra
information, to be more effective, rather than purely taking the DUT as black-box. This
information helps find appropriate opportunity to inject variation in the received information from
other end of the USB-link and execute certain directed scenarios.
Active-agent architecture incorporates most part of decode logic in USB link layer that includes
descrambler, CRC, LFPS detection, and de-framing. It adds pipe-line stages to the receive
datapath to cover for decode latency and allow time to inject variation at right time. The active-
agent also implements configuration space with information on masking specific scenario
injection and collecting coverage statistics.
Major functional blocks are shown in the architectural diagram Figure 2. of active agent.
Figure 2. USB3.0-LTSSM Active Agent Architecture
4.1. DESCRAMBLER
Before the information can be identified to act upon by the agent it must be decoded at the receive
path of PIPE interface, and the first stage is descrambling. It’s based on free running linear
feedback shift register (LFSR) and if enabled the logic follows USB3.0 specification with
polynomial;
G(x) = x^16 + x^5 + x^4 + x^3 + 1
Control (K codes) symbols are bypassed and the LFSR is reset to FFFF at every COM symbol. If
the PHY contains this logic, it can be easily bypassed from the agent logic.
4.2. FRAMING DETECTION
After descrambling the decode logic performs detection of framing pattern and special symbols.
The sliding pattern match mechanism is used to detect symbol position in aligned or unaligned
packet. Framing detection is performed for Link Commands (LC), Header Packet (HP), Data
Packet (DPP, END/ENDB), and Ordered Sets (OS). The packets are checked for CRC and after
anomaly injection the CRC is recalculated to re-validate the packet.
4.3. LFPS DETECT
Low Frequency Periodic Signalling (LFPS) detection is performed as per USB3.0 specification
and is primarily used for low power mode exit and warm-reset. The details of normative LFPS
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
46
implementation can be found in the USB specification. The latency increases by few clock cycles
while the decode logic is active before it acts for scenario injection based on constraints. This
does not impact the functionality of the DUT neither it violates USB3.0 or PIPE specification.
4.4. CONFIGURATION SPACE
The active agent also has configuration space that is accessible through simple register space
access interface that is memory mapped in local processor. The configuration spaces access is
used to fetch coverage statistic and to enable or disable specific scenario injection logic and to
configure and modify constraints of scenario injection driver.
4.5. ERROR INJECTION AND PIPELINE STAGES
This block is part of pipeline stage and performs error injection in receive path with manipulated
information. The required information for manipulation and content update is received from other
modules. Scenario injection logic acts based on the information from coverage statistics that help
update the constraints of scenario injection logic for uncovered state transitions during future test
iterations. Coverage constraints applicability is restricted to state-transitions where occurrence of
transition conditions can be varied in time. Manipulating receive path information is tricky and
requires extra care while exercising this approach staying within boundaries of USB3.0
specification. The implementation is simple once the concept is understood and the efforts put in
developing such active-agent are worth as the results seen are promising for coverage closer on
prototype system.
Table 1. Xilinx-Kintex7 FPGA series resource utilization
Resource Slice LUTs Slice Registers RAMB36
USB-Device 21764 12766 16
Active agent
% of DUT
2840 810 0
13% 6% 0%
5. VERIFICATION AND RESULTS
As per USB3.0 specification there are total of 20 LTSSM state and sub-states for USP with more
than 85 possible transition arcs where 20 transitions are associated with ‘directed’ from upper
layer through warm-reset. From rest of the transition arcs, less than 20 transition arcs are usually
covered in normal prototype environment. There is scope of error injection, within specification
boundaries, to stress test the DUT and the active agent plays effective role. All the LTSSM states
and sub-state transitions are tracked and coverage information is collected at state entry event.
During the research work specific set of test conditions were targeted for this experiment.
A simple event of cable connect-disconnect can exercise more test-condition and increase the
DUT coverage. However, performing this connect-disconnect test manually and expecting it to
occur at specific point in time at all possible opportunities, is practically impossible in typical
FPGA prototype platform. With active agent this is made possible. USB device can be connected
or disconnected from host port at any time and cover all reachable scenarios on existing prototype
platform. At PIPE interface the connect-disconnect event is stimulated using relevant input
signals as listed in table 2.
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47
By overriding inputs signals to DUT at PIPE interface device connect-disconnect event is tested
for each all LTSSM states and sub-states. The active-agent has helped significantly in uncovering
multiple corner conditions that did not get caught during normal testing on the prototype system.
Table 2. PIPE interface signals for active-agent
Signal Direction Description
RxDataValid Input Instruct the Link layer DUT logic to ignore the data
interface for one clock cycle. A value of one indicates the
upper layer logic will use the data, a value of zero
indicates it will not use the data.
RxValid Input Indicates symbol lock and valid data on RxData and
RxDataK
PhyStatus Input Used to communicate completion of several PHY
functions including stable PCLKafter Reset# de-assertion,
power management state transitions, rate change, and
receiver detection. When this signal transitions during
entry and exit from any PHY state where PCLK is not
provided, then the signalling is asynchronous.
RxElecIdle Input Indicates receiver detection of an electrical idle. While
de-asserted with the PHY in P0, P1, P2, or P3, indicates
detection of LFPS
RxStatus[2:0] Input Encodes receiver status and error codes for the received
data stream when receiving data.
3'b000 : Received data OK
3'b001 : 1 skip OS added
3'b010 : 1 skip OS removed
3’b011 : Receive detected
3'b100 : 8b10b decode error
3'b101 : EB overflow
3'b110 : EB underflow
3'b111 : Receiver disparity error
PowerPresent Input Indicates the presence of VBUS
Scenario injection is simpler and more effective while exercising negative conditions for state
transition. Let’s understand this with one of the core state of the ‘LTSSM: Polling’ state and sub-
states. Polling.LFPS is a sub-state designed to establish the PHY’s DC operating point for LFPS
operation, and to synchronize the operation between the two link partners after exiting from
Rx.Detect. This is also a sub-state for a port to identify itself based on various Polling.LFPS
signatures.
Figure 3. Shows polling sub-states of USB LTSSM. Let’s understand how the active agent
generates desired stimulus and help generate quality stimulus. In normal operation, with standard
prototype system, the Polling state moves straight forward through Polling.LFPS ->
Polling.RxEQ -> Polling.Active-> Polling.Configuration-> Polling.Idle-> U0. There are multiple
other functionally possible test conditions that are not reachable in standard prototype system.
When the scenario injection is enabled the active agent finds opportunity of injecting specific
condition when the LTSSM enters Polling.LFPS. So apart from its normal route that is
Polling.LFPS Polling.RxEQ, the LTSSM is stress tested for error conditions in Polling.LFPS
state and for transitions to SS.Disabled or Compliance. There is a provision to enable or disable
scenario injection by masking condition via configuration space access interface.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
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Rx.Detect
Polling.LFPS
Polling.RxEQ
Polling.Active
Polling.Configuration
Polling.Idle
Compliance
SS.Disabled
U0
Hot Reset
Loopback
Rx.Detect
Figure 3. USB3.0-LTSSM – Polling sub-states
Table 3. lists multiple functional testing scenarios for Polling.LFPS sub state in UpStream Port
component. It is evident from the list of possible scenarios that just state transition coverage is not
sufficient to gain confidence before claiming closer in pre-silicon verification with FPGA
prototype systems.
Table 3. Polling.LFPS Test scenarios and Active agent
The real benefit of active agent is not just covering all the state transition of DUT on FPGA
prototype, rather its ability to inject error without violating the specification to stress test specific
state of LTSSM.
Table 4. presents improved results with active-agent generated stimulus for the DUT.
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.9, No.3, June 2018
49
Table 4. Polling.LFPS coverage
Transition arc Test Coverage
Current State Exit State # Default With Active agent
Polling.LFPS Polling.RxEQ 1 1 1
Polling.LFPS Polling.RxEQ 1a 0 1
Polling.LFPS Polling.RxEQ 1b 0 1
Polling.LFPS Compliance 2 0 1
Polling.LFPS SS.Disabled 3 0 1
Irrespective of what method is chosen for offline simulation, pre-silicon verification, or post-
silicon testing, important aspects of any verification idea are controllability, and observability. In
proposed method, this is covered to some extent with control of scenario injection and coverage
collector. However major concern with such non-trivial testing methodology for FPGA prototype
is trouble shooting and bug localization. To manage this concern, a simple debug mechanism was
created. Explained in brief; local memory was added, with configurable depth, that logs state
transitions and the contents rollover when the test is run for longer period beyond its storage
capacity. Interrupt is asserted to local processor for initiating the memory-read when entry to
Rx.Detect occurs for warm-reset and was not intended as per scenario injection. The content of
memory gives transaction log that helps understand state transitions. In our experiment we’ve
debug port from DUT that provides all important error flags due to which the state transitions
deviate from its expected route. This information helps in bug-localization.
6. CONCLUSION
The stress testing and coverage improvement using proposed architecture is demonstrated in this
paper with sample experiment. The proposed approach is very efficient in uncovering hidden
bugs without inviting much in hardware or software infrastructure resources. The experiment was
done on limited scenarios of LTSSM, however more scenarios would be added in future to
exercise further stress testing with varying state exit and error injection. This active agent is
reusable component and can be safely used with any USB3.0 USP DUT. The same methodology
can be applied to USB3.0 DSP, and for that matter, any standard protocol interface for the
purpose of stress testing and finding corner scenarios at earliest with less effort on FPGA
prototype systems.
ACKNOWLEDGEMENTS
The authors would like to thank Softnautics LLP. for their supports and providing FPGA
prototype platform along with all the associated infrastructure to test active-agent. The authors
would also like to thank Dr. D. J. Shah for his guidance.
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AUTHORS
Dipakkumar Modi received the BE degree in instrumentation and control engineering
from L. D. College of Engineering, Ahmedabad, Gujarat in 2001. He is currently
working with Softnautics LLP as technical director IP group. He has worked in VLSI
industry for more than 16 years, his research interests are in field of SoC design,
hardware accelerated verification, and emulation.
Prof. Usha Mehta has done her Ph. D. in the area “Testing of VLSI Design” and is
currently working as Professor at Nirma University, Ahmedabad. She has more than
22 years of academic and industrial experience. She has one patent, has published a
book and more than 50 research papers in international journals and conferences.
She is a senior member of IEEE and currently holds the position of chair, IEEE WIE
Affinity group, Gujarat section. Her research interests are in testing VLSI Design,
Digital VLSI Design, and programmable Logic.