Direct mapping maps each main memory block to only one cache line, based on a modulo function. The example addresses would map to cache lines 3294 and 1110 respectively, and the minimum and maximum addresses of each block are provided. Some tag values in the example cache are shown, and it is possible to determine which addresses are contained in the cache based on comparing tags. Set associative mapping divides the cache into sets, with each set containing multiple lines that a block can map to. An example shows a 2-way set associative cache with 4K lines and 16-word blocks. For given addresses, it is explained how to determine the set number, tag value, and block minimum and maximum addresses based on the

1. Cache Mapping Examples

2. Direct Mapping
Direct Mapping  Each block of main memory maps to only one cache line – i.e. if a block is in
cache, it will always be found in the same place
Line number is calculated using the following function
i = j modulo m
where
i = cache line number
j = main memory block number
m = number of lines in the cache

3. Direct Mapping
What cache line number will the following addresses be stored to, and what will the
minimum address and the maximum address of each block they are in be if we have a
cache with 4K lines of 16 words to a block in a 256 MB memory space (28-bit address)?
a.) 9ABCDEF16 1001 1010 1011 1100 1101 1110 1111 - Line 3294
b.) 123456716 0001 0010 0011 0100 0101 0110 0111 - Line 1110
a.) 9ABCDEF16 9ABCDE0 - 9ABCDEF
b.) 123456716 1234560 - 123456F
Tag s-r
12 12 4
Line or slot r Word w
P1

4. Direct Mapping
Assume that a portion of the tags in the cache in our example looks like the table
below. Which of the following addresses are contained in the cache?
a.) 438EE816 b.) F18EFF16 c.) 6B8EF316 d.) AD8EF316
P2

5. P3

6. P3

7. P3

8. P4

9. P4

10. Fully Associative Mapping
• A main memory block can load into any line of cache
• Memory address is interpreted as:
– Least significant w bits = word position within block
– Most significant s bits = tag used to identify which block is stored in a
particular line of cache
• Every line's tag must be examined for a match
• Cache searching gets expensive and slower
Tag – s bits
(22 in example)
Word – w bits
(2 in ex.)

11. P1
Fully Associative Mapping Example
Assume that a portion of the tags in the cache in our example looks
like the table below. Which of the following addresses are contained
in the cache?
a.) 438EE816 b.) F18EFF16 c.) 6B8EF316 d.) AD8EF316

12. P2

14. P3

15. Set - Associative Mapping
Set Associative Mapping Traits
• Address length is s + w bits
• Cache is divided into a number of sets, v = 2d
• K blocks/lines can be contained within each set
• K lines in a cache is called a k-way set associative mapping
• Number of lines in a cache = v•k = k•2d
• Size of tag = (s-d) bits

16. • Hybrid of Direct and Associative
k = 1, this is basically direct mapping
v = 1, this is associative mapping
• Each set contains a number of lines, basically the number of lines divided by
the number of sets
• A given block maps to any line within its specified set – e.g. Block B can be in
any line of set i.
• 2 lines per set is the most common organization.
– Called 2 way associative mapping
– A given block can be in one of 2 lines in only one specific set
– Significant improvement over direct mapping

17. Set Associative Mapping Example
• What cache set number will the block be stored to?
• What will their tag be?
• What will the minimum address and the maximum address of each block they
are in be?
1. 9ABCDEF16
2. 123456716
For each of the following addresses, answer the following questions based on a 2-way
set associative cache with 4K lines, each line containing 16 words, with the main
memory of size 256 Meg memory space (28-bit address):
Tag s-r
13 11 4
Set s Word w

18. • Address length = (s + w) bits
• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (s – d) bits
Set Associative Mapping Summary

19. P1

20. P2

21. P2

22. P2

23. P3

24. P3

25. P4

26. P4