Chinh Nguyen has over 25 years of experience in the semiconductor industry as a process engineer specializing in etch manufacturing processes. He currently works as a Wets FEOL Etch Process Engineer at IBM where he has driven improvements such as reducing defects densities by 10x and identifying and containing sources of defects. Prior to IBM, he held process engineering roles at various semiconductor companies where he worked on developing, optimizing, and sustaining etch and clean processes.

1. Chinh T. Nguyen
New Milford, CT 06776
Cell: (714) 553-3157
E-Mail: nguyen_ct@yahoo.com
http://www.linkedin.com/in/tchinhnguyen
Profile:
Results-oriented Process Engineer in the semiconductor industry with extensive knowledge of Etch
manufacturing processes and Process Integration. Respected for leadership, interpersonal, and team
building skills by both managers and colleagues.
Core Competencies
• Certified Six Sigma Green Belt • Utilizing 8-D Process for • Certified ISO 9001-2008 /
• Certified Six Sigma Black Belt Root Cause Analysis and AS9100C and ISO 13485 Internal
Problem Solving Auditor
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Professional Experience
IBM – Microelectronics Division E. Fishkill, NY 2010 – Present
Fully automated 300mm Fab of CMOS, SOI and hybrid semiconductor for 60 to 14nm technology
nodes.
Wets FEOL Etch Process Engineer (2010 – Present)
Responsible for FEOL Wet Etch sector metrics including cpk, defect density and line yield by using
SPC, DOE and other Six Sigma tools to improve sectors controls.
 Driving an 8-D to reduce defects density 10-fold down to 0.08 defect/cm2 for Wets batch etch
processes.
 Identified and contained the cause of poor resist adhesion resulting in 100% reduction in litho rework.
 Identified, contained and driving solutions for broken poly lines and ESD defects from Wets single wafer
tool processes affecting 1% in the yield.
 Developed and optimized recipes for Wets single wafer tools for the contact module resulting in a 3 to
5x defects reduction.
 Utilizing Six Sigma techniques such as SIPOC, Gage R&R and SPC to reduce the variation of the
deep-trench crystallographic silicon batch etch process.
NXP Semiconductors E. Fishkill, NY 2005 – 2009
NXP is a newly independent semiconductor company (founded by Philips) with a fifty-year history of
providing semiconductor products.
Etch Process Engineer (2005 – 2009)
Metal RIE, Wet Etch and Ash Process Engineer responsible for characterizing, optimizing and
sustaining the processes in these sectors.
 Implemented real-time tool monitoring and control by utilizing Brookside software and achieving:
 A 96% wafer loss reduction by limiting risk to one wafer per lot.
 Savings over $6400 annually by going paperless for graphical interface of critical parameters.
 Identification of equipment failures using root cause analysis to prevent future wafer loss.
 Reduced Metal RIE defects density by 2% by re-organizing work flow strategies.
 Developed and qualified an Initial Wafer Wet Clean process that reduced rework by 100%.
 Increased through-put by 50 to 100% from developing efficient wet clean processes.
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2. Chinh Nguyen (714) 553-3157 2
 Critical team member in many R&D projects from identifying and eliminating defects to eliminating one
mask level from the process that resulted in 5 to 10% increase in yield.
 Set new standards in the manufacturing documentations and streamlined tool monitoring procedures
resulting in a 57% reduction in qualification downtime without sacrificing quality.
DNS Electronics E. Fishkill, NY 2001 – 2005
DNS is a Japanese manufacturer of semiconductor equipment that include batch and single wafer wet
clean systems, photo resist, SOG, SOD, polyimide processing equipment, and RTP systems.
Senior Process Engineer – Clean Etch (2001 – 2005)
Ensure smooth transfer of 200mm and 300mm equipment from start-up through process development
and qualifications. Negotiate equipment and process specifications, testing procedures and timelines with
customers. Identify causes and implement solutions for DNS equipment / process related issues.
 Led a high performance team to overcome 21 days of facilities delays and met customer’s scheduled
release date for a 300mm Wets batch systems.
 Identified the cause and implemented solutions for wafer edge pitting reducing customer’s false
particles count failures by 20%.
 Reduced equipment downtime by 20% by driving for better test monitors flows by the customers.
 Identified the cause and implemented solutions for high particles count failures of a BOE solution in a
minimizing a 14-days delay enabling the customer to meet important production dates.
 Developed a Wets single wafer tool etch recipe that increased the customer’s productivity by more than
100% by eliminating reworks and a secondary step.
 Negotiated win-win solutions between the customers and DNS such as reducing testing time by 60%
without sacrificing data integrity and providing process alternatives for test monitors rework.
Conexant Systems (currently Jazz Semiconductors) Newport Beach, CA 1987 – 2001
A $2 billion worldwide supplier of ASICs and hybrid semiconductor solutions.
Senior Process Engineer – Integration (2000 – 2001)
Facilitate smooth transfer of processes from R&D to manufacturing through monitoring and improving
process controls through SPC, process optimization, and directing projects within Core Teams.
 Provided documentation and process optimization for the successful transfer of the 0.18um RF
process, 0.25um Imager process and quad level metal 0.35um BiCMOS process.
 Performed tests, directed Core Team projects to identify possible causes and solutions for dielectric
breakdown failures within the 0.35um BiCMOS process resulting in a 20 to 80% reduction in scrap.
 Performed process optimization for the 0.25um and 0.18um processes to increase yield by 4 to 6% at
the same time reducing cycle time by 24 hours.
Senior Process Engineer – Etch (1991 – 2000)
Responsibilities include development; characterization and sustaining of FEOL and BEOL RIE and Wet
Etch processes.
 Exhibited effective leadership skills as pro-tem Etch Section Manager with successes such as:
 Organized an orderly recovery after a Fab-wide power outage and contained the wafers scrapped
to 10% of the work in progress in the Etch Sectors.
 Supervised workflow during a Fab-wide work stoppage to maintain 25% of production with the
remaining 3% of the workforce for the Etch Sectors.
 Responsible for Wets and RIE startup of a 200mm Fab within 8 months of a typical 12 months
timeframe.

3. Chinh Nguyen (714) 553-3157 3
 Developed robust modules for the 0.25um Shallow Trench and Nitride Spacer Etch, and the 0.35um
Poly Etch to maximize device performance.
 Driven defect reduction projects that resulted in a 95% reduction of defects while increasing equipment
productivity by greater than 400% for the 0.25um Poly Etch.
Education: Bachelor of Science in Electrical Engineering California State University, Long Beach, CA