This document discusses cache-based side channel attacks and proposes new cache designs to prevent them. It begins with an introduction to side channel attacks and two examples: an RSA attack using cache interference and an AES attack analyzing computation times. It then proposes two new cache architectures: a partitioned locked cache that isolates sensitive processes and a randomly permuting cache that obscures which cache lines are evicted. The models are evaluated using an OpenSSL AES implementation, finding the proposed designs prevent attacks with minimal performance overhead.