1. Durgesh Chaurasiya
Curriculum Vitae
"Chase your dream because it do come true!!"
Objective
Being enthusiastic, curious and motivated, I am seeking an innovative and challeng-
ing career in the field of Digital CMOS Circuit/ASIC/FPGA/Phyical design and
Verification Engineering.
Education
2015 M.Tech. in Microlectronics and VLSI, Indian Institute of Technology, Hyder-
abad, CGPA – 8.29.
2011 B.E. in ECE, The University Institute of Technology, Bhopal, Percentage – 72.78.
2006 Higher Secondary, Nalanda Publich HS School, Bhopal, Percentage – 83.33.
2004 High School, Nalanda Publich HS School, Bhopal, Percentage – 93.4.
Technical skills
Programming Verilog, VHDL, C, C++, Shell Scripting, MySQL.
EDA Tools ModelSim, Xilinx ISE, Cadence Virtuoso,Synopsys ICC.
Physics CAD Comsol Multiphysics, Coventorware, Silvaco, Matlab.
Relevant Courses
Digital IC Design & Verification, Advanced Topics in Digital Circuit Design,
Embedded Memory Design (FCC), Computer Architecture,Analog IC Design,
VLSI Technology, Device Physics and Modeling, Digital Signal Processing.
Academic Projetcs
Title "Designe of an Algorithm for ECG signal compression and implementation on
FPGA."
Room Number 119, Old Boys’ Hostel, IIT Hyderabad, ODF, Yeddumailaram, Medak
Hyderabad, Telangana, India 502205
(+91) 9640654953, (+91) 8099567191 • ee12m1013@iith.ac.in
http://in.linkedin.com/in/durgesh90 1/3

2. Description We designed an algorithm to compress the ECG signal to keep computational
complexity at minimum level because operation is targeted to be done at minimal
energy. The proposed compression methodology is based on the Discrete Wavelet
Transform (DWT).
Title "Design of SRAM cell using 65nm technology and analysis of timing for critical
path for read and write operation."
Description We were involved in design and simulation of SRAM array of 256x64 size using
cadence Virtuoso. We extracted timing of critical path for read and write operation.
Title "Design and realization of RAM and ROM memories."
Title "Design of Peripheral Component Interconnect on FPGA."
Title "Design of sensor based Traffic Light Controller on FPGA."
Title "Conductivity Enhancement of SU-8 based MEMS Structures."
Masters Thesis
Title Design of a CMOS compatible Biosensor for Lab-on-a-Chip applications
Supervisors Associate Professor Dr. Shiv Govind Singh & Assistant Prof. Dr. Siva Vanjari.
Description Nanoscale biosensors are widely regarded as a potential candidate for ultra-sensitive,
label-free detection of biochemical molecules. Our motivation is to design low cost
and very sensitive device, by combining advantages of electrical and mechanical
bio-sensors, which should be able to detect as less number of malignant tissue
(DNA) as possible. Our approach is based on Flexure FET.
Experience
2013–Present Research Associate at IIT Hyderabad.
Key Learnings:
RTL Coding in Verilog HDL.
Low Power Design.
Asic Design Flow.
Static Timing Analysis.
Digital CMOS Circuit Design.
2011–2012 Associate System Engineer-T, TCSL, Mumbai.
Publication
D. Chaurasiya, B. Srinivasan, S. Vanjari, S.G. Singh, "SU-8 Based Flexure-
FET Biosensor to Achieve Ultrasensitive Response.",TechConnect World Innova-
tion, Conference & Expo, Washington DC USA, 2015.
B. Srinivasan,D. Chaurasia, S. Vanjari, S.G. Singh, "A simple process for selective
bio-functionalization of SU-8 surface for Lab-on-a-Chip applications.",TechConnect
World Innovation, Conference & Expo, Washington DC USA, 2015.
Achievements
Secured 99 Percentile in Gate 2011 at First attempt.
Secured SECOND rank in High School at District level.
Room Number 119, Old Boys’ Hostel, IIT Hyderabad, ODF, Yeddumailaram, Medak
Hyderabad, Telangana, India 502205
(+91) 9640654953, (+91) 8099567191 • ee12m1013@iith.ac.in
http://in.linkedin.com/in/durgesh90 2/3

3. Received scholarship from HINDUJA Foundation which provides scholarship to
only 3 meritorious students every year from Madhya Pradesh state.
Obtained 100 marks in Mathematics in High School.
Secured THIRD rank in Essay competition at District level.
CO-CURRICULUM ACTIVITIES
Attended a two day workshop on Analog IC Design organized by IEEE CAS in
collaboration with Austria Microsystems.
Undergone training onSynopsys IC Compiler by Synopsys.
M.Tech. Placement Coordinator in EE Department at IITH.
Webcasting of Elections to the municipal Council 2014, Medak,Telangana, India.
Head of Organizing team of PG farewell and fresherâĂŹs welcome party respec-
tively at Institute level in IIT Hyderabad.
Mess Committee Member since August 2014 to April 2015.
Hobbies
Playing Cricket, Badminton and Table Tennis, Cooking and Listening Music.
Personal Details
Nationality Indian.
Date of Birth May 6,1990.
Languages English, Hindi.
Declaration
I hereby state that all the information provided above by me is correct to the best
of my knowledge.
Place:Hyderabad
Dated: May 2, 2015
Room Number 119, Old Boys’ Hostel, IIT Hyderabad, ODF, Yeddumailaram, Medak
Hyderabad, Telangana, India 502205
(+91) 9640654953, (+91) 8099567191 • ee12m1013@iith.ac.in
http://in.linkedin.com/in/durgesh90 3/3