Gibin M. George is seeking a position that utilizes his technical skills. He has a M.Tech in Microelectronics from Manipal Institute of Technology with a 7.9 CGPA. He has a B.Tech in Electronics and Communication from College of Engineering, Kidangoor with a 72% aggregate. His skills include digital VLSI design, analog and mixed signal design, verification and validation. He has experience with Cadence design tools, Verilog, SystemVerilog, VHDL and Python. His past projects include designing an AMBA APB 3.0 protocol using SystemVerilog and UVM and implementing an I2C master core in VHDL. He has worked as an intern at

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GIBIN M. GEORGE
MOBILE 9663931959,7795620975
Home 9400013069
Citizenship:
INDIAN
DOB:04/10/1989 Gender : Male EMAIL gibinmgeorge89@gmail.com
Present
Address
Mylakkattu (h), Puthuppally P.O., Kottayam, Kerala - 686011
Permanent
Address
Mylakkattu (h), Puthuppally P.O., Kottayam, Kerala - 686011
Objective To be part of an organization where I can utilize my technical knowledge and skills
Educational Qualifications
Grade School / College Board / University Duration (yr) % / CGPA
M. Tech Manipal Institute of
Technology, Manipal
Manipal 2 7.90
B.Tech College of Engineering,
Kidangoor, Kottayam
CUSAT 4 72.00
12
th
Donbosco H.S.S.,
Puthuppally, Kottayam
Higher Secondary 1 86.33
10
th
Donbosco H.S.S.,
Puthuppally, Kottayam
Kerala State 1 95.13
B.Tech Branch: ELECTRONICS & COMMUNICATION
Sem 1 Sem 2
Sem
3
Sem 4
Sem
5
Sem 6
Sem 7 Sem 8
GPA / % 71.09 71.1 69.45 72.64 69.27 69.73 77.05 75.7
CGPA / % 72.00
M.Tech Branch: MICROELECTRONICS CGPA : 7.9
Elective
Subjects
 VLSI Physical design & Verification
 VLSI Testing and Testability
 Analog VLSI for Signal processing
 Applied Linear Algebra
Areas of Interest
 Digital VLSI design
 Analog & mixed signal design
 VLSI verification & validation
 Embedded systems
 Signal processing
Skill Sets
Software
 Cadence Design Tool (Virtuoso, Incisive, Encounter RTL Compiler)
 Modelsim
 Xilinx ISE
 MATLAB
 PSPICE
Programming
languages
 C
 Verilog
 System Verilog
 VHDL
Verification
Methodology
UVM (basics)
Scripting
languages
Python (basics)
Protocols
known
AMBA APB , I
2
C

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Technical Activities
 M.Tech Project : Design and advanced verification of ARM AMBA APB 3.0 using System Verilog and UVM
Brief summary: AMBA APB 3.0 protocol was designed as master –slave configuration using memory controller
as slave. The driver part of testbench environment acted as master. Hierarchical testbench environments were build using
plain System Verilog and UVM to verify the operations, basic write and read, burst transfer, write and read with wait states.
Functional coverage and assertions were included to measure the quality of verification process. Cadence Incisive Simulator
was used for the project.
 Mini Projects : 1.Design of low power Carry Select Adder in Verilog
Brief summary : Low power carry select adder was designed using Verilog HDL .It was simulated using
Cadence Incisive simulator and synthesized in Cadence RTL Compiler
2.Standard Cell Layout of Inverter, NAND gate
Brief summary: Circuits were simulated with Spectre simulator. The std. cell layout was done in Virtuoso.
Finally, DRC and LVS checks were done.
3. Design of low pass, high pass and bandpass filters using OTA
Brief summary: Circuits were designed using Operational Transconductance Amplifier and
capacitors.Frequency responses were plotted using Spectre Simulator.
 B.Tech Project : Design and Implementation of I
2
C Master core using VHDL
Brief summary : I
2
C Master core was designed using VHDL and simulated in Modelsim .Design was
implemented in Xilinx Spartan 3 FPGA kit
 Attended 6 - month training programme on Cadence Design Tool for Digital VLSI design conducted by
KARMIC DESIGN PVT. LTD., Manipal
Hobbies : Reading, travelling, playing badminton
Work Experience
1. Internship at KARMIC DESIGN PVT. LTD., Manipal (September 2014 – July 2015)
2. Project fellow in KSCSTE sponsored project -“Effect of mimicked speech on automatic speaker verification
system.”( July 2012 to July 2013)
Achievements
 Qualified GATE (Graduate Aptitude Test in Engineering)
 Co-author in two publications
1. Leena Mary, Anish Babu K.K., Aju Joseph, Gibin M. George
“ Evaluation Of Mimicked Speech Using Prosodic Features ” Proceedings of International Conference on Acoustics,
Speech, and Signal Processing (ICASSP 2013) ,Vancouver, Canada
2. Aju Joseph, Gibin M. George, Anish Babu K. K., Leena Mary
“ Computation of Speaker Similarity using Phrase Level Prosodic Features ” Proceedings of National Technological
Congress (NATCON 2013) , RIT Kottayam pp. 112-115
References:
1.Prof. D.V Kamath, Professor, Dept. of ECE, Manipal Institute of Technology
Ph: 91-9611942374 (M), 0820 2924829 (O),Email: reachdvkamath@yahoo.com
2.Prof.S.N.Bhat, Associate Professor, Dept. of ECE, Manipal Institute of Technology
Mob. No: 91-9448623784,Email: msnbhat299@gmail.com
The above information provided by me is true and have all the relevant documents to authenticate the same.
GIBIN M. GEORGE

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