Ade manual with co po-18scheme

Dept. of CSE, AMCEC Page 1
AMC ENGINEERING COLLEGE
18th
K.M, BANNERGHATTA ROAD, KALKERE, BANGALORE-560083
DEPARTMENT OF COMPUTER SCIENCE
&
ENGINEERING
III SEMESTER
ANALOG AND DIGITAL ELECTRONICS LABORATORY
(CBCS SCHEME 18CSL37)
Name of the Student: __________________________
USN No: __________________________

TABLE OF CONTENTS
ADE LAB MANUAL (CBCS) -18CSL37
Department of Computer Science, AMCEC
EXPT
No.
NAME OF THE EXPERIMENT Pg.No.
1 VISION & MISSION OF THE INSTITUTION 3
2 VISION & MISSION OF THE DEPARTMENT 4
3 PROGRAM EDUCATIONAL OBJECTIVES PROGRAM SPECIFIC OUTCOMES 5
4 PROGRAM OUTCOMES (POs) 6
5 COURSE OBJECTIVE, SYLLABUS 7
PART-A
6 ASTABLE MULTIVIBRATOR 9
7 RELAXATION OSCILLATOR 11
8 WINDOW COMPARATOR (SCHMITT TRIGGER) 13
PART –B
9 STEPS FOR USING XILINX 15
10 ADDERS AND SUBTRACTORS 16
11 8:1 MULTIPLEXER 22
12 J-K MASTER SLAVE FLIP-FLOP 26
13 CODE CONVERTORS 29
15 SYNCHRONOUS UP COUNTER 32
16 ASYNCHRONOUS DECADE COUNTER 35
18 CONTENT BEYOND SYLLABUS 37
19 VIVA QUESTIONS 46

VISION OF THE INSTITUTION
“ To be a leader in imparting value based Technical Education and Research for
the benefit of society ”
MISSION OF THE INSTITUTION
M1 To provide state of the art Infrastructure facilities
M2 To implement modern pedagogical methods in delivering the academic programs
with experienced and committed faculty
M3 To create a vibrant ambience that promotes Learning, Research, Invention and
Innovation
M4 To undertake manpower and skill development programmes for Academic
Institutions and Industries
M5 To enhance Institute Industry Interface through Collaborative Research and
Consultancy
M6 To generate and disseminate knowledge through training programmes/
workshops/ seminars/ conferences/ publications
M7 To be a more comprehensive college in terms of the number of programs offered
M8 To relentlessly pursue professional excellence with ethical and moral values

VISION OF THE DEPARTMENT
“ Be a premier department in the field of Computer Science & Engineering to meet
the technological challenges of the society ”
MISSION OF THE DEPARTMENT
MD 1 To provide state of the art infrastructure facilities
MD 2 To provide exposure to the latest tools in the area of computer hardware and
software
MD 3 To strive for academic excellence through research in Computer Science and
Engineering with creative teaching-learning pedagogy
MD 4 To establish Industry Institute Interaction and make students ready for the
Industrial environment
MD 5 To transform students into entrepreneurial, technically competent, socially
responsible and ethical computer science professional

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
After the Program completion, CSE graduates will be able to:
PEO1: Graduates possess advanced knowledge of Computer Science & Engineering and excel in
leadership roles to serve the society.
PEO2: Graduates of the program will apply Computer Engineering tools in core technologies for
improving knowledge in the Interdisciplinary Research and Entrepreneurs.
PEO3: Graduates adapt Value-Based Proficiency in solving Real Time problems.
PROGRAM SPECIFIC OUTCOMES (PSOs)
PSO1: Professional Skills: Ability of applying the Computing Concepts, Data Structure, Computer
Hardware, Computer Networks and Suitable Algorithm..
PSO2: Software Skills: Ability to build Software Engineering System with Development Life Cycle
by using analytical knowledge in Computer Science & Engineering and applying modern
methodologies

PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering Fundamentals,
and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information
to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports
and design documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

ANALOG AND DIGITAL ELECTRONICS LABORATORY
(Effective from the academic year 2018 -2019)
SEMESTER – III
Course Code 18CSL37 CIE Marks 40
Number of Contact Hours/Week 0:2:2 SEE Marks 60
Total Number of Lab Contact Hours 36 Exam Hours 03
Credits – 2
Course Learning Objectives: This course (18CSL37) will enable students to:
This laboratory course enable students to get practical experience in design, assembly and
evaluation/testing of
 Analog components and circuits including Operational Amplifier, Timer, etc.
 Combinational logic circuits.
 Flip - Flops and their operations
 Counters and registers using flip-flops.
 Synchronous and Asynchronous sequential circuits.
 A/D and D/A converters
Descriptions (if any):
 Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant.
 For Part A (Analog Electronic Circuits) students must trace the wave form on Tracing sheet /
Graph sheet and label trace.
 Continuous evaluation by the faculty must be carried by including performance of a student in
both hardware implementation and simulation (if any) for the given circuit.
 A batch not exceeding 4 must be formed for conducting the experiment. For simulation individual
student must execute the program.
Laboratory Programs:
PART A (Analog Electronic Circuits)
1. Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50% and >50%)
using NE 555 timer IC. Simulate the same for any one duty cycle.
2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And
simulate the same.
3. Using ua 741 opamp, design a window comparator for any given UTP and LTP. And
simulate the same.
PART B (Digital Electronic Circuits)
4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic
gates. And implement the same in HDL.
5. Given a 4-variable logic expression, simplify it using appropriate technique and realize the
simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.
6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.
7. Design and implement code converter I)Binary to Gray (II) Gray to Binary Code using basic
gates.
8. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.
9. Design and implement an asynchronous counter using decade counter IC to count up from 0
to n (n<=9) and demonstrate on 7-segment display (using IC-7447)
Laboratory Outcomes: The student should be able to:
 Use appropriate design equations / methods to design the given circuit.
 Examine and verify the design of both analog and digital circuits using simulators.
 Make us of electronic components, ICs, instruments and tools for design and testing of circuits

for the given the appropriate inputs.
 Compile a laboratory journal which includes; aim, tool/instruments/software/components used,
design equations used and designs, schematics, program listing, procedure followed, relevant
theory, results as graphs and tables, interpreting and concluding the findings.
Conduct of Practical Examination:
 Experiment distribution
o For laboratories having only one part: Students are allowed to pick one experiment from
the lot with equal opportunity.
o For laboratories having PART A and PART B: Students are allowed to pick one
experiment from PART A and one experiment from PART B, with equalopportunity.
 Change of experiment is allowed only once and marks allotted for procedure to be made zero of
the changed part only.
 Marks Distribution (Courseed to change in accoradance with university regulations)
a) For laboratories having only one part – Procedure + Execution + Viva-Voce: 15+70+15 =
100 Marks
b) For laboratories having PART A and PART B
i. Part A – Procedure + Execution + Viva = 6 + 28 + 6 = 40 Marks
ii. Part B – Procedure + Execution + Viva = 9 + 42 + 9 = 60 Marks

EXPT NO: 1 ASTABLE MULTIVIBRATOR
1. Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50% and >50%)
using NE 555 timer IC. Simulate the same for any one duty cycle.
COMPONENTS REQUIRED: 555 Timer, diode (1N4007), resistors (2 – 3.3K,) and capacitors
(0.1F, 0.01F)
ASTABLE MULTIVIBRATOR:
Circuit Diagram for Duty Cycle > 66%:
Design:
Given: Duty Cycle - 66%, Frequency – 1.5KHz
Charging Time, CRRT BA )(693.01  -------(1)
Discharging Time, CRT B693.02  ------------(2)
Time Period, mS
Kf
T 66.0
5.1
11

Duty Cycle 66.0%661
21
1



T
T
TT
T
D
mSTT 435.066.01 
mSTTT 225.0435.066.012 
Using (2),
C
T
RB
693.0
2

Let FC 1.0

K
m
RB 24.3
1.0693.0
225.0




Using (1), K
m
C
T
RR BA 42.6
1.0693.0
445.0
693.0
1




KKKRKR BA 3.33.34.64.6 
Procedure:
1. Before making the connections, check the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the capacitor voltage waveform at 6th
pin of 555 timer on CRO.
4. Observe the output waveform at 3rd
pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty cycle.
Expected Output Voltage waveforms for Astable Multivibrator
0v
2/3Vcc
1/3Vcc
5V
pin3 o/p
pin6 o/p
Output Waveform s for Astable Multivibrator
Sym m etrical waveform (66% Duty Cycle)

EXPT NO: 2 RELAXATION OSCILLATOR
2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And
simulate the same.
COMPONENTS REQUIRED: A741 Op-amp, Resistors - 4.7k, 10k, Capacitor-0.1F
Design:
The period of the output rectangular wave is given as 










1
1
ln2RCT -------(1)
Where,
21
1
RR
R

 is the feedback fraction,
If R1 = R2, then from equation (1) we have T = 2RC ln (3)
Another example, if R2=1.16 R1, then T = 2RC ----------(2)
Example: Design for a frequency of 1kHz (implies ms
f
T 110
10
11 3
3
 
)
Use R2=1.16R1, for equation (2) ,
Let R1 = 10kΩ, then R2 = 11.6kΩ (use 10kΩ as 11.6 k is not available)
Choose next a value of C and then calculate value of R3 from equation (2).
Let C=0.1µF (i.e., 10-7
), then 

 

K
C
T
R 5
102
10
2 7
3
3 = 4.7K (available)
The voltage across the capacitor has a peak voltage of satc V
RR
R
V
21
1


Procedure :
1. Before making the connections check all the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the voltage waveform across the capacitor on CRO.
4. Also observe the output waveform on CRO. Measure its amplitude and frequency.

EXPT NO: 3 SCHMITT TRIGGER
3. Using ua 741 opamp, design a window comparator for any given UTP and LTP. And
simulate the same.
COMPONENTS REQUIRED: A741 Op-amp & Resistors (10K, 100K)
THEORY / HYPOTHESIS:
• A comparator is a circuit which compares a signal voltage applied at one input of an opamp with a
known reference voltage at the other input.
• A window comparator is basically the inverting and the non-inverting comparators, combined into a
single comparator stage. The window comparator detects input voltage levels that are within a specific
band or window of voltages, instead of indicating whether a voltage is greater or less than some preset
or fixed voltage reference point.
• In window comparator, the output changes state when the input voltage goes above or below the reset
reference voltage. In a window comparator, there are two reference voltages, called lower and upper
trip points (UTP & LTP). Output is in one state, when it is inside the window created by the lower and
the upper trip points and in the other state when it is outside the window.
WINDOW COMPARATOR CIRCUIT:
Design: Design goals: UTP = 3.33V, LTP = 1.66V
A reference voltage, VCC, is divided down by resistors R1-R3. The two node voltages, UTP and
LTP, define the upper window voltage and lower window voltage, respectively. When the input
voltage is between UTP and LTP, the output is ‘HIGH’, or VP; when outside the window voltage,
the output is pulled down to 0V. Equations (1) and (2) define UTP and LTP, respectively:

Given, UTP = 3.33V & LTP = 1.66V; then
To limit the current drawn from the reference voltage source, R1 and R2 were selected to be 10KΩ.
While the values of R1 and R2 are related to the ratio of the window voltages, R3 determines the
voltage value, R3 is calculated as follows:
Procedure:
1. Rig up the circuit as shown in the circuit diagram
2. Apply a 1KHz, 10Vp-p Sinusoidal signal to the input and observe the output signal.
3. Select the XY position on the CRO and observe the transfer characteristic. Note down
the LTP & UTP Values.

Steps to fallow in XILINX/ISE to execute the program and verify the
result:
 Click on Xilinx ISEi
 Click File  New Project in File Menu.
Enter following details
Project Name: gateimp
Top Level Module: HDL  Next
 New Project Dialog enter/select
Device family: Spartan2
Device: xc3s200
Package: pq208
Top-Level Module: HDL
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator(VHDL/Verilog)
Select Enable Enhanced design summary :  next
 Click New Source, select VHDL Module or Verilog Module (add to project should be selected)
Enter file Name: example Andgate  next enter the portsnextnextFinish
This will create Andgate.vhd or Andgate.v source file.
Open sources and process window from the view toolbar
 Double click on Andgate.vhd in Sources window
Edit and Enter the VHDL (Verilog) source code of your project  save
 Click on .vhd file in Sources window right click on Synthesis XST in the processes window
run correct the errors if exit, save rerun synthesis XST
 Projectnew sourceTest bench waveform, enter file name(any name), (add to project should
be selected) nextselect combinational(internal clock in the Initialize timing
windowFinish
 Set the inputs values in the .tbw filesave
 Change synthesis/Implementation to behavioral simulation in the sources window.
 Click on the .tbw file in the sources windowRun behavioral simulation module under the
Xilinx ISE simulator in the processes window
 Verify the output waveform in the simulation result.

EXPT NO: 4 ADDER & SUBTRACTOR
4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic
gates. And implement the same in HDL.
COMPONENTS REQUIRED: Trainer kit, Patch chords, ICs-7408, 74LS86, 7432, 7404
Pinout diagram:
XOR GATE 74LS86 OR/AND GATE 74LS32/7408
4a. HALF ADDER
Half Adder is a combinational circuit that performs addition of two bits. It has two inputs and two
outputs. The two I/Ps are the two 1-bit numbers A and B designated as augend and addend bits. The
two O/Ps are the sum ‘S’ of A and B and the carry bit, denoted by ‘C’.
Half adder symbol and logic diagram: A Half Adder circuit can be implemented using AND & OR
logic gates or by using XOR & AND logic gates. Both these implementations are shown in the image
below:
Inputs Outputs
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
4b. FULL ADDER
The main difference between the Full Adder and the previous Half Adder is that a full adder has three
inputs. The same two single bit data inputs A and B as before plus an additional Carry-in (C-in) input
to receive the carry from a previous stage as shown below.

Full Adder Block Diagram
Then the full adder is a logical circuit that performs
an addition operation on three binary digits and ust like
the half adder, it also generates a carry out to the next
addition column. Then a Carry-in is a ossible carry
from a less significant digit, while a Carry-out
represents a carry to a more significant digit.
In many ways, the full adder can be thought of as two half adders connected together, with the first half
adder passing its carry to the second half adder as shown.
Full Adder Logic Diagram
As the full adder circuit above is basically two half adders connected together, the truth table for the
full adder includes an additional column to take into account the Carry-in, CIN input as well as the
summed output, S and the Carry-out, COUT bit.
Truth Table
C-in B A Sum C-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

4C. HALF SUBTRACTOR
The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has
two inputs, the minuend and subtrahend and two outputs the difference and borrow out B out
4d. FULL SUBTRACTOR
A logic Circuit which is used for Subtracting Three Single bit Binary digit is known as Full Subtractor. The truth
table of Full Subtractor is shown below.
Inputs Outputs
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Truth Table
A B B-in Diff B-out
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

HDL code for HALF ADDER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity adr is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end adr;
architecture Behavioral of adr is
begin
s<=a xor b;
c<=a and b;
end Behavioral;
FULL ADDER:
library IEEE;
--library UNISIM;
entity FA is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin: in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end FA;
architecture Behavioral of FA is
signal wire_1:std_logic;
begin

wire_1<=a xor b;
wire_2<=wire_1 and cin;
wire_3<=a and b;
s<=wire_1 xor cin;
c<=wire_2 or wire_3;
end Behavioral;
HDL code for HALF SUBTRACTOR:
library IEEE;
--library UNISIM;
entity HS is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Diff : out STD_LOGIC;
Cy : out STD_LOGIC);
end HS;
architecture Behavioral of HS is
begin
Diff <=A xor B;
wire_1<=not A;
Cy <= wire_1 and B;
end Behavioral;

HDL code for FULL SUBTRACTOR
library IEEE;
--library UNISIM;
entity FULLSUBTRACTOR is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
BIN : in STD_LOGIC;
DF : out STD_LOGIC;
BO : out STD_LOGIC);
end FULLSUBTRACTOR;
architecture Behavioral of FULLSUBTRACTOR is
begin
wire_1<= A xor B;
wire_2<= not A;
wire_3<= wire_2 and B;
DF<=BIN xor wire_1;
wire_4<=not wire_1;
wire_5<=BIN and wire_4;
BO<= wire_3 or wire_5;
end Behavioral;

EXPT NO : 5 8:1 MULTIPLEXER
5. Given a 4-variable logic expression, simplify it using appropriate technique and realize the
simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.
COMPONENTS REQUIRED: Digital IC Trainer kit, Patch chords, IC-74151, IC 7404
THEORY: A Multiplexer routes one among the many inputs 2n
to the output based on addressing or
selection. It is called many to one logic circuit. An 8:1 multiplexer has 8 inputs and 1 output, for
addressing it has 3 selection lines.
Map Entered Variable (MEV): MEV is an alternative to K-map where a variable is placed as output
or one of the input variable is placed inside karnaugh map. This reduces the K-map size by 1 degree.
Problem:
Simplify the function using MEV technique f (a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)
MEV Map
ABC 000 001 010 011 100 101 110 111
D0 0 1 1 0 1 1 0 0
D1 0 1 1 0 1 1 1 1
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7

Truth Table: Circuit Diagram
PROCEDURE:
1. Place the IC by seeing the notch on the ziff socket.
2. Properly connect Vcc and Ground as well as input and output pins.
3. Do not switch on the IC trainer kit, till the wiring is complete.
4. Design the circuit using the given logical expression by reducing the variables using MEV method.
5. Take the selection lines (A,B,C) as first three inputs and D as the MEV, this D will be either
complimented or un complimented.
6. Switch ON the kit and verify the truth table values.

Simulation with HDL
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity mux8 is
Port(I: in std_Logic_vector(7 downto 0);
Sel: in std_logic_vector (2 downto 0);
Zout: out std_logic_vector);
End mux8;
Architecture Behavioral of mux8 is
Begin
Zout<= I(0) when sel = ”000” else
I(1) when sel = “001” else
I(7);
End behavioral;
Truth Table:
SEL 2 SEL 1 SEL0 OUT PUT
0 0 0 I 0
0 0 1 I 1
0 1 0 I 2
0 1 1 I 3
1 0 0 I 4
1 0 1 I 5
1 1 0 I 6
1 1 1 I 7

Ports:
PORTS PORTS BUS MSB LSB
I IN YES 7 0
SEL IN YES 2 0
ZOUT OUT NO
Simulation output:

EXPT NO: 6 J-K MASTER SLAVE FLIP-FLOP
6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.
COMPONENTS REQUIRED: IC Trainer kit, IC 7400 and IC 7410 NAND gate.
THEORY: A Flip-Flop is a multivibrator (bistable) circuit that has two stable states Logic 0 and Logic
1 .It has two inputs J,K and two outputs Q and Qbar.
Basically a Flip-Flop stores or remembers the
logical states. A Flip-Flop is the basic building block of all sequential circuits . A Flip-Flop can be
realized using Universal gates.
Here Two JK Flip-Flops are there .One acts as Master and the other as Slave. When Master is
active state ,slave will be in Inactive state. Master is Positive Edge Triggered and the Slave is Negative
Edge Triggered. Hence Master responds to its JK inputs before the slave.
Master Slave J-K Flip Flop Using NAND gates only:
Truth Table –1:
_
Inputs Output
Operation Performed
Clk Clr Pre Q
1 1 1 Q Normal FF (table – 2)
0 0 1 0 FF cleared (Reset)
0 1 0 1 FF preset (Set)

Truth Table – 2:
Inputs Output
Comments
CLK J K Qn+1
High 0 0 Qn No change
High 0 1 0 Reset
High 1 0 1 Set
High 1 1 Qn,
Toggle
Note: Keep pre = 1 and clr = 1 for verifying the Truth Tables of JKMS FF
PROCEDURE:
3. Connect PRE and CLR to switches and keep it HIGH.
4. Give CLOCK input using 1Hz continuous clock or Mono pulse.
5. Do not switch on the IC trainer Kit, till the wiring is complete.
6. Switch ON the Trainer Kit and Verify the truth table.
Simulation with HDL
JK Master Slave flip flop
library IEEE;
--library UNISIM;
entity JKM is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
Q : inout STD_LOGIC;
Qp : inout STD_LOGIC;
Pre : in STD_LOGIC;
Clr : in STD_LOGIC;
clk :in STD_LOGIC);
end JKM;
architecture Behavioral of JKM is

begin
wire_1<=(Qp nand j)nand clk;
wire_2<=(clk nand k)nand Q;
wire_3<=(wire_1 nand Pre) nand wire_4;
wire_4<=(wire_3 nand wire_2) nand Clr;
wire_5<= not clk;
wire_6<=wire_3 nand wire_5;
wire_7<=wire_5 nand wire_4;
Q<=wire_6 nand Qp;
Qp<=wire_7 nand Q;
end Behavioral;

EXPT NO: 7 CODE CONVERTORS
7. Design and implement code converter I)Binary to Gray (II) Gray to Binary Code using basic
gates.
COMPONENTS REQUIRED: Trainer kit, Patch chords, ICs: 74LS86
Theory: The logical circuit which converts binary code to equivalent gray code is known as binary to
gray code converter. The gray code is a non-weighted code. The successive gray code differs in one bit
position only, that means it is a unit distance code. It is also referred as cyclic code. It is not suitable for
arithmetic operations. It is the most popular of the unit distance codes. It is also a reflective code. Gray
codes are also known as reflected binary code (RBC), Gray codes are widely used to facilitate error
correction in digital communications such as digital terrestrial television and some cable TV systems.
7a) Binary to Gray code convertor: An n-bit Gray code can be obtained by reflecting an n-1 bit code
about an axis after 2n-1
rows, and putting the MSB of 0 above the axis and the MSB of 1 below the axis.
The 4 bits binary to gray code conversion table is given below, That means, in 4 bit gray code, (4-1) or
3 bit code is reflected against the axis drawn after (24-1
)th
or 8th
row. The bits of 4 bit gray code are
considered as G4G3G2G1. Now from conversion table,
From above SOPs, let us draw K -maps for G4, G3, G2 and G1.
G4: All the entries of B4Â and G4 are same in truth table. Hence G4 = B4

G3 G2
G1
Circuit for Binary to Gray code convertor

7b) Gray code to binary convertor: The conversion of gray to binary code also requires XOR'ing,
but this time bits of gray code is XOR'ed with output binary code bits. The M.S.B is written as it
is, then the output M.S.B in binary is XOR'ed with the adjacent bit in the gray code, and then the
next adjacent bit if gray code is XOR'ed with last obtained binary bit.
Circuit for Gray code to binary convertor
Truth table for grey to binary convertor

EXPT NO: 8 SYNCHRONOUS UP COUNTER
8. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.
COMPONENTS REQUIRED: IC Trainer kit, IC7476 (2) MS JK FLIP-FLOP and IC 7408(1) AND
gate.
THEORY: A counter is one of the useful circuits in digital system. Counter driven by clock is used to
count the number of clock cycles. In synchronous counter, every Flip-Flop is triggered in synchronous
with clock. Clock inputs are applied simultaneously to all Flip-Flops .The UP Counter counts the
numbers from 000 to 111 for mod 8 counter.
Truth Tables: Clock
Pulses
Desired Count
table
Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Present state Next state Excitation inputs
Qc Qb Qa Qc +1 Qb+1 Qa+1 Jc Kc Jb Kb Ja Ka
0 0 0 0 0 1 0 x 0 X 1 x
0 0 1 0 1 0 0 x 1 X X 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 x 0 1 X
1 1 1 0 0 0 X 1 x 1 X 1

Pin details of 7476 IC
J K Clk
Sd
(Pre)
Rd
(Clr)
Q
__
Q
Vcc Gnd
4 16 1 2 3 15 14 5 13
9 12 6 7 8 11 10

PROCEDURE:
3. Verify the truth Tables.
4. To see the counts on the 7-segment display refer the circuit as given in 10th experiment.

EXPT NO: 9 DECADE COUNTER
9. Design and implement an asynchronous counter using decade counter IC to count up from 0
to n (n<=9) and demonstrate on 7-segment display (using IC-7447)
COMPONENTS REQUIRED: IC Trainer kit, IC7400 NAND gate and IC7490 Decade counter.
THEORY: A decade counter is one that counts in decimal digits, rather than binary. A decade counter
may have each digit binary encoded (that is, it may count in binary-coded decimal, as the 7490
integrated circuit did) Alternatively, it may have a "fully decoded" output The decade counter is also
known as a mod-counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). A Mod Counter that counts to
64 stops at 63 because 0 counts as a valid digit.
Block diagram of IC 7490 and 7-segment display:
Clock
Pulses
Desired Count table
Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

PROCEDURE:
3. MS1, MS2, MR1and MR2 inputs are connected to GND.
4. Clock input is given to Clock A
5. Output Q0 and Clock B are shorted so that it acts as Divide-by 10 counter with BCD count sequence.
6. Verify the truth table and observe the count on seven segment display.

Experiments beyond Syllabus:
These experiments are done using the very basic componrnts, while others are the
applications of these basic experiments. Hence these are included.
EXPT No: A1 CLIPPER AND CLAMPER
A1. a) Design and construct a suitable circuit and demonstrate the working of positive clipper,
double-ended clipper and positive clamper using diodes.
b) Demonstrate the working of the above circuits using a simulation package.
AIM: To design and construct a suitable circuit and demonstrate the working of positive clipper,
double-ended clipper and positive clamper using diodes.
COMPONENTS REQUIRED: 2 – 1N4007/BY127 Diodes, Resistors:3.3K, 100K
Theory: The circuit used to shape a waveform by removing i.e. clipping a portion of the applied wave
is known as a clipper. These clippers can remove signal voltages above or below a specified level.
A few types of diode clippers are:
a. positive clippers,
b. negative clipper,
c. shunt clippers,
d. series clippers, &
e. combinational clippers.
Clipping circuits are used to select a part of a signal waveform which lies above or below a certain
reference voltage level for transmission.
The series configuration is defined as one where the diode is in series with the load while the
parallel/shunt has the diode in a branch parallel to the load.
POSITIVE PEAK – SHUNT CLIPPING:
Design: To find the value of R:
Given: Rf = 100 Ω, Rr=100 K Ω
R = √ √
R=3.16 K Ω. Choose R as 3.3 K Ω

Procedure:
1. Before making the connections check all components using multimeter.
2. Make the connections as shown in circuit diagram.
3. Using a signal generator (Vi) apply a sine wave of 1KHz frequency and a peak-to-peak
amplitude of 8V to the circuit. (Square wave can also be applied.)
4. Keep the CRO in dual mode, connect the input (Vi) signal to channel 1 and output waveform
(Vo) to channel 2. Observe the clipped output waveform. Also record the amplitude and time
data from the waveforms.
5. Now keep the CRO in X-Y mode and observe the transfer characteristic waveform.
Note:
i. Vary Vref and observe the variation in clipping level. For this use variable DC power supply for
Vref.
ii. Change the direction of diode and Vref to realize a negative clipper.
iii. For double-ended clipping circuit, make the circuit connections as shown in fig.3 and the output
waveform is observed.
iv. Adjust the ground level of the CRO on both channels properly and view the output in DC mode
(not in AC mode) for both clippers and clampers.
Input and expected output wave forms for positive peak clipping (Positive Peak Shunt clipping):
Tabular column for readings:
Sl. Vref in volts Vo(p-p) in volts

Double ended Clipper:
Input and expected output voltage waveforms:

POSITIVE CLAMPER:
Theory: The clamping circuit adds d.c. component to the signal and pushes the signal
upwards/downwards such that the negative/positive peaks fall on/below the zero level. Before
clamping the signal will have -5 to 0 to +5, but after clamping the signal will range from 0 to +10v or 0
to -10v. The original shape of the signal will not change, only there is a vertical shift in the signal. If
the signal is pushed above zero level i.e. 0 to +10v it is called positive clamping. If the signal is pushed
below zero level i.e. -10 to 0, is called negative clamping.
Design: For T=20msec, f=50hz R and C should be chosen such that T=RC is large enough to ensure
that the capacitor does not discharge while the diode is not conducting. Hence for RC>>t, chose c =
0.1µf, then R > 200kΩ
Procedure:
1. Before making the connections check all components using multimeter.
2. Make the connections as shown in circuit diagram (fig. 5).
3. Using a signal generator apply a sine wave input (Vi) of peak-to-peak amplitude of 8V (and
frequency greater than 50Hz) to the circuit. (Sine wave can also be applied)
Observe the clamped output waveform on CRO
Input and expected output voltage waveforms:

PART B: Demonstrate the working of the above circuits using a simulation package.

Positive Clamper
Fig. 6: Input and output waveform for positive clamper without reference voltage.
Fig. 7: Input and output waveform for positive clamper circuit with reference voltage = 2V

EXPT NO: B2 RING COUNTER & SWITCHED TAIL COUNTER
B2.a) Design and implement a ring counter using 4-bit shift register and demonstrate its
working.
b) Design and develop the Verilog / VHDL code for switched tail counter. Simulate and
verify its working.
AIM: Design and implement a ring counter using 4-bit shift register and demonstrate its
working.
COMPONENTS REQUIRED: IC trainer kit, IC 7495bpc, Universal Shift Register &IC 7404
Inverter gate.
THEORY: Registers are used to store data .A register is basically an array of Flip-Flops. Ring counter is a basic
register with feedback that the contents of the registers simply circulate around the register when the clock is
running.
Realization of Ring counter using IC 7495bpc:
Truth Table:
Clock Time
Outputs
Q3 Q2 Q1 Q0
0 T0 0 0 0 1
1 T1 1 0 0 0
2 T2 0 1 0 0
3 T3 0 0 1 0
4 T4 0 0 0 1

PROCEDURE:
3. If the serial output Q0 of the shift register is connected back to the serial input DS, then an injected pulse
will keep circulating. This is known as ring counter.
4. Mode control is made 1.
5. Parallel inputs 0001 are given to D3D2D1D0 inputs.
6. CLK 2 is pulsed once. Now D3D2D1D0 parallel inputs appear on Q3, Q2, Q1, Q0 lines.
7. CLK 1 is connected to the pulser.
a. Now mode control is made LOW.
b. circulates around the circuit as shown.
c. Observe the output waveforms Q3, Q2, Q1,Q0 on CRO.
8. Verify the truth table.
b) Design and develop the Verilog / VHDL code for switched tail counter. Simulate and
verify its working.
THEORY: A switch-tail counter (also called twisted ring counter, Johnson counter) uses the complement of the
serial output of a right shift register as its serial input. A Johnson counter (or switchtail ring counter,
twisted-ring counter, walking-ring counter) is a modified ring counter, where the output from the last
stage is inverted and fed back as input to the first stage. The register cycles through a sequence of bit-
patterns, whose length is equal to twice the length of the shift register, continuing indefinitely. These
counters find specialist applications, including those similar to the decade counter, digital-to-analog
conversion, etc. They can be implemented easily using D- or JK-type flip-flops.
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity johs is
Port(clk,e,rst:in std_logic);
Q:inout std_logic_vector(3 downto 0));
End johs;
Architecture behavioral of johs is
Begin
Process(clk,rst)
Begin
If rst=’1’ then q<=”0001”
Else if rising_edge(clk) then
If e=’1’ then q<=(not q(0)) & q(3 downto 1);
End if;
End if;
End if;
End process;
End behavioral;

Viva Questions with answers:
1. What is the necessary of the coupling capacitor?
A. It is used to block the c signal to the transistor amplifier. It allows a c &blocks the d c.
2. Define sensitivity.
A. It is the ratio of percentage change in voltage gain with feedback to the percentage change
in voltage gain without feed back.
3. Define Desensitivity.
A. It is the ratio of percentage change in voltage gain without feedback to thepercentage
change in voltage.
4. Define an operational amplifier.
A. An operational amplifier is a direct-coupled, high gain amplifier consisting of one or more
differential amplifier. By properly selecting the external components, it can be used to
perform a variety of mathematical operations.
5. Mention the characteristics of an ideal op-amp.
A. * Open loop voltage gain is infinity.
* Input impedance is infinity.
* Output impedance is zero. *Bandwidth is infinity.
* Zero offset.
6. Define input offset voltage.
A. A small voltage applied to the input terminals to make the output voltage as zero when
the two input terminals are grounded is called input offset voltage.
7. Define input offset current.
A. The difference between the bias currents at the input terminals of the op-amp is called as
input offset current.
8. What are the basic elements of power supply ?
A. (i) Transformer (ii) Rectifier. (iii) Filter.
9. What is ripple factor(Υ)?
A. Ripple factor (γ) may be defined as the ratio of the root mean square (rms) value of the
ripple voltage to the absolute value of the dc component of the output voltage, usually
expressed as a percentage. However, ripple voltage is also commonly expressed as the
peak-to-peak value. This is largely because peak-to-peak is both easier to measure on an
oscilloscope and is simpler to calculate theoretically. Filter circuits intended for the
reduction of ripple are usually called smoothing circuits.
10. What is a rectifier?
A. A rectifier is an electrical device that converts alternating current (AC), which periodically

reverses direction, to direct current (DC), which flows in only one direction. The process
is known as rectification.
11. Define SMPS .
A. A switched-mode power supply (switching-mode power supply, SMPS, or simply
switcher) is an electronic power supply that incorporates a switching regulator in order to
be highly efficient in the conversion of electrical power. An SMPS is usually employed to
efficiently provide a regulated output voltage, typically at a level different from the input
voltage.
12. What is the need for differential amplifiers?
A. Differential amplifiers are small signal direct coupled amplifiers used to amplify the
difference between two signals. The need for differential amplifier arises in physical
measurements, instrumentation amplifiers and medical instrumentation.
13. What are the advantages of Differential Amplifiers?
A. * High voltage gain.
* High input impedance
* High Bandwidth
* Good bias stability.
14. Define CMRR.
A. Common Mode Rejection Ratio (CMRR) is the ability of the differential amplifiers to reject
the common mode signals. It is defined as the ratio of difference mode gain Ad to
common mode gain Ac.
15. Why Differential amplifiers are widely used in Integrated Circuits?
A. It has good bias stability and good voltage gain without the use of large bypass capacitors.
Hence it is used in ICs.
16. What is DIGITAL GATE?
A. Digital gates are basically electronic components which are used for switching and
manipulating binary data
17. What do u mean by universal gate?
A. The universal gates are those gate from which we can make any gate by using
them. The universal gates are- NAND & NOR
18. What is truth table?
A. Truth table is a table from which we can get o/p of different gates
19. What is different between Ex-or & Ex-nor gate?
A. The basic difference between this two gate is that Ex-or gate gives o/p when both
the i/p is different & Ex-nor gate give o/p when both i/p same.
20. What is D’morgans theorem.

A. D’morgans theorem is theorems through which we can easily manipulate and reduce the
given equation.
21. Writes D’morgans theorem equations.
A. 1. (A+B)’=A’B’ 2. A’B’= (A+B)’
22. Solve following example by using D’morgans theorem.
A (ABC)’=A’+B’+C’
23. Solve following example by using D’morgans theorem. (A+B+C)’
A (A+B+C)’=A’B’C’
24. Solve following example by using D’morgans theorem. (ABC)’ (AB)’
A. (ABC)’ (AB)’= (A’+B’+C’) (A’+B’)
25. Who invent the D’morgans theorem?
A The law is named after Augustus De Morgan (1806–1871)
26. De Morgan theorem is used for what?
A this theorem is useful for solving the different bullion expressions.
27. What is IC?
A. In electronics, an integrated circuit (also known as IC, chip, or microchip) is a miniaturized
electronic circuit (consisting mainly of semiconductor devices, as well as passive
components) that has been manufactured in the surface of a thin substrate of
semiconductor material. Integrated circuits are used in almost all electronic equipment in
use today and have revolutionized the world of electronics. Computers, cellular phones,
and other digital appliances are now inextricable parts of the structure of modern
societies, made possible by the low cost of production of integrated circuits.
28. What is flip-flop?
A15: - Flip-flop is a 1 bit storing element.
29. How many types of flip-flop are used?
A; 4 types of flip –flop, S-R, J-K, D, T
30. What is disadvantage of SR flip-flop?
A When both the input is one then it gives invalid output.
31. What is disadvantage of JK flip-flop?
A. Race around condition.
32. To remove race around condition what we use?
A. Master slave Flip-flop.

33. What is race around condition?
A. When pulse width is more then signal width then for signal change of pulse width many
no of times signal changes its state that is called race around condition.
34. What are the characteristic equation for T flip-flop?
A Q = TQ’+ QT’
35. Which Gates are used in SR flip flops to a JK flip-flop?
A. Nand Gates
36. D flip-flop is used for?
A. Providing delay.
37. What is counter?
A. In digital logic and computing, a counter is a device which stores (and sometimes displays)
the number of times a particular event or process has occurred, often in relationship to a
clock signal.
38. Give types of counter?
A. There are two types of counters(1) Up counters, which increase (increment) in value (2)
Down counters, which decrease (decrement) in value .
39. What are the implements of counter?
A. In electronics, counters can be implemented quite easily using register-type circuits such
as the flipflop, and a wide variety of designs exist, e.g.:(1)Asynchronous (ripple) counter –
changing state bits are used as clocks to subsequent state flip-flops (2)Synchronous
counter – all state bits change under control of a single clock (3)Decade counter – counts
through ten states per stage (4)Up–down counter – counts both up and down, under
command of a control input (5)Ring counter – formed by a shift register with feedback
connection in a ring (6)Johnson counter – a twisted ring counter (7)Cascaded counter
40. Explain Asynchronous (ripple) counter?
A. An asynchronous (ripple) counter is a single K-type flip-flop, with its J (data) input fed
from its own inverted output. This circuit can store one bit, and hence can count from
zero to one before it overflows (starts over from 0). This counter will increment once for
every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate
between a transition from 0 to 1 and a transition from 1 to 0. Notice that this creates a new
clock with a 50% duty cycle at exactly half the frequency of the input clock. If this output is
then used as the clock signal for a similarly arranged D flip-flop (remembering to invert
the output to the input), you will get another 1 bit counter that counts half as fast. Putting
them together yields a two bit counter.

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