An Analog to Digital Converter (ADC) bridges the analog world to the digital world, and is crucial to any modern sensor system. We find that our customers increasingly demand ADCs to be absorbed into their mixed-signal Application Specific Integrated Circuits (ASICs), with huge benefits to their systems in terms of cost, power and size. But some expertise is required for the potential gains to be realized, both on the part of the ASIC supplier and on the part of the customer.
Retrofit, build, or go cloud/colo? Choosing your best directionSchneider Electric
When faced with the decision of upgrading an existing data center, building a new data center or leasing space in a third party colocation data center, there are both quantitative and qualitative differences to consider. This session reviews several key factors to help make a sound decision including a business’ sensitivity to cash flow, deployment timeframe, data center life expectancy, regulatory requirements, and other strategic factors.
How Data Center Infrastructure Management Software Improves Planning and Cuts...Schneider Electric
Business executives are challenging their IT staffs to convert data centers from cost centers into producers of business value. Data centers can make a significant impact to the bottom line by enabling the business to respond more quickly to market demands. This presentation demonstrates, through a series of examples, how data center infrastructure management (DCIM) software tools can simplify operational processes, cut costs, and speed up information delivery.
Learn more about "what is a solid state relay", key features and targeted applications.
For more details:
http://www.schneider-electric.com/en/product-range/60278-zelio-relays?parent-category-id=2800&filter=business-1-Industrial%20Automation%20and%20Control
New Trends in Video Security: Traditional Security Monitoring to Advanced Ope...Schneider Electric
As presented at AIST 2014: With the magnitude of both internal and external threats on the rise, asset owners in the industrial space have begun to search for new solutions capable of protecting plant assets from challenges ranging from safety and regulatory issues, to the proactive protection of mission critical company assets.
Over the past few years, we have seen some industries react to perimeter attacks, but as the attacks have become more sophisticated in nature, so has the need to take advantage of some of the newer technologies revolving around advanced video analytics to ensure the protection of organization.
This presentation describes end to end asset protection solutions to ensure the integrity of the organizations ecosystem.
integratedprocessandpowerautomation-110225095416-phpapp02 (1)Eiden Lai Cherhuat
This document discusses electrical integration using ABB's Integrated Process and Power Automation solution. It defines electrical integration as integrating process automation and power automation into one system. ABB's solution provides full plant integration using System 800xA with electrical integration based on open standards. It offers a complete portfolio from ABB and customer benefits like reduced costs, improved effectiveness, availability, and energy savings. Example references of installations are provided.
ETAP 14 is an electrical power system analysis software that features a 64-bit architecture, local SQL database, auto-build and theme manager tools, automated protection and coordination evaluation, short circuit and contingency analysis, updated arc flash standards, interfaces for importing models from other software, thousands of new protective device models, and free data conversion from legacy software.
Learn more about SCADA expert ClearSCADA:
- Simplicity & Enhanced User Experience for faster deployment and improved time-to-market
- Reduced Maintenance Efforts for protection of investment
- Enhanced Security capability for better protection of the system
- Enhanced Operational Intelligence to help optimize operations and maintenance activities
- Integrated with the complete Schneider Electric Telemetry portfolio
The document provides an overview of the process for designing and producing an application specific integrated circuit (ASIC) with Swindon Silicon Systems. It discusses the design process from initial specification through layout, fabrication, and testing. Key steps include specification, design and simulation, processing including wafer thinning and dicing, and prototype evaluation. Swindon offers full turnkey ASIC design and supply services from concept to production.
Retrofit, build, or go cloud/colo? Choosing your best directionSchneider Electric
When faced with the decision of upgrading an existing data center, building a new data center or leasing space in a third party colocation data center, there are both quantitative and qualitative differences to consider. This session reviews several key factors to help make a sound decision including a business’ sensitivity to cash flow, deployment timeframe, data center life expectancy, regulatory requirements, and other strategic factors.
How Data Center Infrastructure Management Software Improves Planning and Cuts...Schneider Electric
Business executives are challenging their IT staffs to convert data centers from cost centers into producers of business value. Data centers can make a significant impact to the bottom line by enabling the business to respond more quickly to market demands. This presentation demonstrates, through a series of examples, how data center infrastructure management (DCIM) software tools can simplify operational processes, cut costs, and speed up information delivery.
Learn more about "what is a solid state relay", key features and targeted applications.
For more details:
http://www.schneider-electric.com/en/product-range/60278-zelio-relays?parent-category-id=2800&filter=business-1-Industrial%20Automation%20and%20Control
New Trends in Video Security: Traditional Security Monitoring to Advanced Ope...Schneider Electric
As presented at AIST 2014: With the magnitude of both internal and external threats on the rise, asset owners in the industrial space have begun to search for new solutions capable of protecting plant assets from challenges ranging from safety and regulatory issues, to the proactive protection of mission critical company assets.
Over the past few years, we have seen some industries react to perimeter attacks, but as the attacks have become more sophisticated in nature, so has the need to take advantage of some of the newer technologies revolving around advanced video analytics to ensure the protection of organization.
This presentation describes end to end asset protection solutions to ensure the integrity of the organizations ecosystem.
integratedprocessandpowerautomation-110225095416-phpapp02 (1)Eiden Lai Cherhuat
This document discusses electrical integration using ABB's Integrated Process and Power Automation solution. It defines electrical integration as integrating process automation and power automation into one system. ABB's solution provides full plant integration using System 800xA with electrical integration based on open standards. It offers a complete portfolio from ABB and customer benefits like reduced costs, improved effectiveness, availability, and energy savings. Example references of installations are provided.
ETAP 14 is an electrical power system analysis software that features a 64-bit architecture, local SQL database, auto-build and theme manager tools, automated protection and coordination evaluation, short circuit and contingency analysis, updated arc flash standards, interfaces for importing models from other software, thousands of new protective device models, and free data conversion from legacy software.
Learn more about SCADA expert ClearSCADA:
- Simplicity & Enhanced User Experience for faster deployment and improved time-to-market
- Reduced Maintenance Efforts for protection of investment
- Enhanced Security capability for better protection of the system
- Enhanced Operational Intelligence to help optimize operations and maintenance activities
- Integrated with the complete Schneider Electric Telemetry portfolio
The document provides an overview of the process for designing and producing an application specific integrated circuit (ASIC) with Swindon Silicon Systems. It discusses the design process from initial specification through layout, fabrication, and testing. Key steps include specification, design and simulation, processing including wafer thinning and dicing, and prototype evaluation. Swindon offers full turnkey ASIC design and supply services from concept to production.
This document discusses on-chip self-test solutions for analog-to-digital converters (ADCs). It begins with an introduction explaining the challenges of testing high-performance ADCs and how built-in self-test (BIST) techniques can help overcome these challenges. It then provides an overview of common ADC types and testing parameters. The proposed work involves developing on-chip BIST techniques for ADCs using machine learning, deep learning, fuzzy logic or a modified histogram approach. If implemented, the goal is to achieve low-cost and small-area on-chip testing that is flexible and can accommodate new variables or development purposes. In conclusion, previous work focused on enhancing reliability and reducing test costs and time.
The document discusses trends in factory automation including increasing use of sensors, machine vision, motor control, and Ethernet networks for control. It provides examples of National Semiconductor solutions that support factory automation needs such as high-speed ADCs, PHYTER Ethernet PHYs, and motion control products. These solutions enable applications like sensor interfacing, machine vision systems, motor control sensing, and industrial Ethernet networks.
Power Efficient 4 Bit Flash ADC Using Cadence ToolIRJET Journal
This document describes the design and simulation of a 4-bit flash analog-to-digital converter (ADC) using Cadence tools in 180nm technology. It discusses the key components of a flash ADC including the resistor ladder, comparators, encoder, and how they are combined. Simulation results show the designed 4-bit flash ADC has a power dissipation of 2.88mW, frequency of 11MHz, and delay of 12.9ns. The flash ADC architecture is concluded to be suitable for high-speed, low-power applications.
This document summarizes a quality improvement project to address low first-time yield (FTY) percentages in the PVI-3KW production area of Power-One Italy. Data from October 2012 shows an FTY of 88.8%, with the two biggest sources of failure being issues with manual testing processes and low efficiency rates on the 3000W model. Root cause analysis identified factors like low illumination, complicated manual phases, and wiring/connector issues as contributing to failures during manual testing. Statistical analysis of efficiency data showed a non-normal distribution with outliers below the minimum specification. The project aims to increase the FTY rate to 93% by addressing these key causes of failure.
This document provides an overview of analyzing SDCCH drop rate as a key performance indicator. It discusses the causes of SDCCH drops, investigation procedures, and troubleshooting techniques. Tools described include Business Objects, ZXG10 OMCR, TEMS Investigation, and MCOM 4.2. The technical procedure outlines analyzing SDCCH availability, causes, alarms, measurements, parameters, and drive testing. Examples demonstrate addressing hardware problems, interference, transmission issues, and parameter changes.
The document discusses challenges in designing low power speech processing systems-on-chip (SoCs). It outlines C-DAC's focus on low power applications and describes their ASTRA portfolio of IPs. It then covers various low power design techniques like clock gating, power gating, voltage and frequency scaling. The document concludes by describing C-DAC's NAADA speech processor SoC that integrates these techniques and achieves less than 5mW power consumption.
IRJET- Implementation of 16-Bit Pipelined ADC using 180nm CMOS TechnologyIRJET Journal
This document describes the implementation of a 16-bit pipelined analog-to-digital converter (ADC) using 180nm CMOS technology. A 4-stage pipelined architecture is used, with each stage having a 4-bit resolution enabled by a successive approximation register (SAR) based sub-ADC. SAR ADCs consume low power but have speed and resolution limitations. To overcome these, a pipelined ADC is proposed that achieves high speed and low power consumption. Key blocks include SAR sub-ADCs, digital-to-analog converters, comparators, sample-and-hold circuits, and flip-flops. The design achieves medium sampling rate and 16-bit resolution for applications such as
This document discusses addressing signal integrity challenges in radar and electronic warfare systems due to increasing data bus rates. It describes how high speeds can lead to signal degradation through various effects. Measurement and characterization tools are needed to help designers avoid problems and ensure signals are transmitted and received correctly. Simulation and testing of high-speed digital designs is important from early stages of development through compliance testing.
This document is a final year project report for a 6-bit current steering digital to analogue converter. It includes an introduction that describes the objectives and design specifications of the project. The background section provides an overview of digital to analogue conversion, thermometer decoding, and current source DAC architectures. The design and architecture section describes the implementation of the thermometer decoder and current source DAC. The simulation results are presented and the document is concluded by discussing potential future work.
Embedding Passive and Active Devices in SubstratesMichael Tschandl
AT&S is a global technology company focused on printed circuit boards and advanced packaging solutions. They offer Embedded Component Packaging (ECP), which embeds active or passive components inside printed circuit boards or integrated circuit packages. ECP provides benefits like miniaturization, improved electrical and mechanical performance, enhanced thermal management, and security. The document discusses the ECP process, design and reliability testing, application examples, and trends in electronics packaging.
IRJET- Calibration Techniques for Pipelined ADCsIRJET Journal
1. The document discusses calibration techniques for pipelined analog-to-digital converters (ADCs).
2. It describes sources of error in pipelined ADCs like comparator offset, capacitor mismatch, and op-amp finite gain.
3. The document compares different digital calibration techniques for pipelined ADCs including nested background calibration, least mean square calibration, and split calibration. It analyzes the advantages and limitations of each technique.
The document discusses low power design techniques in VLSI. It begins by explaining why low power has become important, especially with the rise of mobile devices. It then discusses the different sources of power consumption, including dynamic and static power. Several low power design techniques are covered, such as clock gating, multi-Vt libraries, multi-voltage design, and power gating. The document emphasizes analyzing power at the system level and using EDA tools to implement low power techniques throughout the design flow. Overall, it provides an overview of analyzing power consumption and the goals and methods of low power VLSI design.
The document discusses programmable logic controllers (PLCs) and supervisory control and data acquisition (SCADA) systems. It provides an overview of PLC and SCADA course contents, including digital electronics, hardware, programming, and communication. It also describes automation components, PLC applications in various industries, PLC architecture involving input/output devices and a central processing unit, and common PLC programming languages and software. Finally, it outlines the purpose and basic functions of SCADA systems for monitoring and controlling industrial plants and equipment.
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Presentation of the new Energy Systems Sector in SUPSI, with focus on "developing innovative approaches to intelligent energy management and to photovoltaic systems quality,
facilitating their implementation in the built environment,
promoting the knowledge transfer to industry, professionals and younger generation.
Efficient Motor Commutation through Advanced Position SensingHEINZ OYRER
The document is a presentation about improving electric motor efficiency through advanced position sensing technologies. It discusses how brushless DC motors and magnetic position sensors can provide highly accurate motor commutation, especially with Dynamic Angle Error Compensation (DAECTM) which compensates for position measurement errors at high speeds. The presentation provides examples of how these technologies are used in automotive applications like electric power steering to improve fuel efficiency and comply with safety and emissions regulations.
Segmented Sigma Delta DAC using Coarse and Fine ArchitectureIRJET Journal
The document describes a segmented sigma-delta digital-to-analog converter (DAC) architecture that provides benefits over traditional unsegmented DAC designs. It divides the DAC into two sub-DACs - a coarse DAC and a fine DAC. This segmented approach offers significant memory savings and a reduced size for the reconstruction filter. The architecture pushes quantization noise to higher frequencies through noise shaping using a sigma-delta modulator and feedback, improving accuracy and resolution. Overall, the segmented sigma-delta DAC combines advantages of traditional segmented DACs and sigma-delta modulation techniques.
This document provides an overview of ABB's drives and motors catalogue for 2010, including:
- A product quickfinder that allows selection of drives and motors by criteria like power, voltage, enclosure type, and more.
- Brief descriptions and selection criteria for ABB's main drive and motor product families to help customers choose the appropriate product.
- Information on ABB's services including drive installation, commissioning, repair, and training.
- Contact details for ABB and its channel partners for sales and support.
Digital switchgear combines digital technologies with ABB's medium voltage switchgear platforms to provide increased flexibility, reliability, safety and efficiency. Key benefits include reduced footprint and weight, faster delivery and installation, increased switchgear and system reliability through digital communication protocols like IEC 61850, and improved safety during operation and maintenance through sensor technology. ABB offers digital versions of its UniGear, UniSec, ZX and SafePlus switchgear families. References showcase applications in data centers, smart city distribution networks, and other utility and industrial segments worldwide.
Itacoil is an Italian company that produces custom and standard PCB transformers and inductors. It was founded in 1981 and has since expanded its product portfolio and global reach. Itacoil prides itself on its customization capabilities, superior performance that saves customers time and costs, and technological leadership in LLC and LCC resonant topologies. The company has manufacturing facilities in Italy and Hong Kong and partners with major semiconductor brands on custom designs. It forecasts 2022 sales of 6.5 million euros across various product families and market sectors.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
This document discusses on-chip self-test solutions for analog-to-digital converters (ADCs). It begins with an introduction explaining the challenges of testing high-performance ADCs and how built-in self-test (BIST) techniques can help overcome these challenges. It then provides an overview of common ADC types and testing parameters. The proposed work involves developing on-chip BIST techniques for ADCs using machine learning, deep learning, fuzzy logic or a modified histogram approach. If implemented, the goal is to achieve low-cost and small-area on-chip testing that is flexible and can accommodate new variables or development purposes. In conclusion, previous work focused on enhancing reliability and reducing test costs and time.
The document discusses trends in factory automation including increasing use of sensors, machine vision, motor control, and Ethernet networks for control. It provides examples of National Semiconductor solutions that support factory automation needs such as high-speed ADCs, PHYTER Ethernet PHYs, and motion control products. These solutions enable applications like sensor interfacing, machine vision systems, motor control sensing, and industrial Ethernet networks.
Power Efficient 4 Bit Flash ADC Using Cadence ToolIRJET Journal
This document describes the design and simulation of a 4-bit flash analog-to-digital converter (ADC) using Cadence tools in 180nm technology. It discusses the key components of a flash ADC including the resistor ladder, comparators, encoder, and how they are combined. Simulation results show the designed 4-bit flash ADC has a power dissipation of 2.88mW, frequency of 11MHz, and delay of 12.9ns. The flash ADC architecture is concluded to be suitable for high-speed, low-power applications.
This document summarizes a quality improvement project to address low first-time yield (FTY) percentages in the PVI-3KW production area of Power-One Italy. Data from October 2012 shows an FTY of 88.8%, with the two biggest sources of failure being issues with manual testing processes and low efficiency rates on the 3000W model. Root cause analysis identified factors like low illumination, complicated manual phases, and wiring/connector issues as contributing to failures during manual testing. Statistical analysis of efficiency data showed a non-normal distribution with outliers below the minimum specification. The project aims to increase the FTY rate to 93% by addressing these key causes of failure.
This document provides an overview of analyzing SDCCH drop rate as a key performance indicator. It discusses the causes of SDCCH drops, investigation procedures, and troubleshooting techniques. Tools described include Business Objects, ZXG10 OMCR, TEMS Investigation, and MCOM 4.2. The technical procedure outlines analyzing SDCCH availability, causes, alarms, measurements, parameters, and drive testing. Examples demonstrate addressing hardware problems, interference, transmission issues, and parameter changes.
The document discusses challenges in designing low power speech processing systems-on-chip (SoCs). It outlines C-DAC's focus on low power applications and describes their ASTRA portfolio of IPs. It then covers various low power design techniques like clock gating, power gating, voltage and frequency scaling. The document concludes by describing C-DAC's NAADA speech processor SoC that integrates these techniques and achieves less than 5mW power consumption.
IRJET- Implementation of 16-Bit Pipelined ADC using 180nm CMOS TechnologyIRJET Journal
This document describes the implementation of a 16-bit pipelined analog-to-digital converter (ADC) using 180nm CMOS technology. A 4-stage pipelined architecture is used, with each stage having a 4-bit resolution enabled by a successive approximation register (SAR) based sub-ADC. SAR ADCs consume low power but have speed and resolution limitations. To overcome these, a pipelined ADC is proposed that achieves high speed and low power consumption. Key blocks include SAR sub-ADCs, digital-to-analog converters, comparators, sample-and-hold circuits, and flip-flops. The design achieves medium sampling rate and 16-bit resolution for applications such as
This document discusses addressing signal integrity challenges in radar and electronic warfare systems due to increasing data bus rates. It describes how high speeds can lead to signal degradation through various effects. Measurement and characterization tools are needed to help designers avoid problems and ensure signals are transmitted and received correctly. Simulation and testing of high-speed digital designs is important from early stages of development through compliance testing.
This document is a final year project report for a 6-bit current steering digital to analogue converter. It includes an introduction that describes the objectives and design specifications of the project. The background section provides an overview of digital to analogue conversion, thermometer decoding, and current source DAC architectures. The design and architecture section describes the implementation of the thermometer decoder and current source DAC. The simulation results are presented and the document is concluded by discussing potential future work.
Embedding Passive and Active Devices in SubstratesMichael Tschandl
AT&S is a global technology company focused on printed circuit boards and advanced packaging solutions. They offer Embedded Component Packaging (ECP), which embeds active or passive components inside printed circuit boards or integrated circuit packages. ECP provides benefits like miniaturization, improved electrical and mechanical performance, enhanced thermal management, and security. The document discusses the ECP process, design and reliability testing, application examples, and trends in electronics packaging.
IRJET- Calibration Techniques for Pipelined ADCsIRJET Journal
1. The document discusses calibration techniques for pipelined analog-to-digital converters (ADCs).
2. It describes sources of error in pipelined ADCs like comparator offset, capacitor mismatch, and op-amp finite gain.
3. The document compares different digital calibration techniques for pipelined ADCs including nested background calibration, least mean square calibration, and split calibration. It analyzes the advantages and limitations of each technique.
The document discusses low power design techniques in VLSI. It begins by explaining why low power has become important, especially with the rise of mobile devices. It then discusses the different sources of power consumption, including dynamic and static power. Several low power design techniques are covered, such as clock gating, multi-Vt libraries, multi-voltage design, and power gating. The document emphasizes analyzing power at the system level and using EDA tools to implement low power techniques throughout the design flow. Overall, it provides an overview of analyzing power consumption and the goals and methods of low power VLSI design.
The document discusses programmable logic controllers (PLCs) and supervisory control and data acquisition (SCADA) systems. It provides an overview of PLC and SCADA course contents, including digital electronics, hardware, programming, and communication. It also describes automation components, PLC applications in various industries, PLC architecture involving input/output devices and a central processing unit, and common PLC programming languages and software. Finally, it outlines the purpose and basic functions of SCADA systems for monitoring and controlling industrial plants and equipment.
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Presentation of the new Energy Systems Sector in SUPSI, with focus on "developing innovative approaches to intelligent energy management and to photovoltaic systems quality,
facilitating their implementation in the built environment,
promoting the knowledge transfer to industry, professionals and younger generation.
Efficient Motor Commutation through Advanced Position SensingHEINZ OYRER
The document is a presentation about improving electric motor efficiency through advanced position sensing technologies. It discusses how brushless DC motors and magnetic position sensors can provide highly accurate motor commutation, especially with Dynamic Angle Error Compensation (DAECTM) which compensates for position measurement errors at high speeds. The presentation provides examples of how these technologies are used in automotive applications like electric power steering to improve fuel efficiency and comply with safety and emissions regulations.
Segmented Sigma Delta DAC using Coarse and Fine ArchitectureIRJET Journal
The document describes a segmented sigma-delta digital-to-analog converter (DAC) architecture that provides benefits over traditional unsegmented DAC designs. It divides the DAC into two sub-DACs - a coarse DAC and a fine DAC. This segmented approach offers significant memory savings and a reduced size for the reconstruction filter. The architecture pushes quantization noise to higher frequencies through noise shaping using a sigma-delta modulator and feedback, improving accuracy and resolution. Overall, the segmented sigma-delta DAC combines advantages of traditional segmented DACs and sigma-delta modulation techniques.
This document provides an overview of ABB's drives and motors catalogue for 2010, including:
- A product quickfinder that allows selection of drives and motors by criteria like power, voltage, enclosure type, and more.
- Brief descriptions and selection criteria for ABB's main drive and motor product families to help customers choose the appropriate product.
- Information on ABB's services including drive installation, commissioning, repair, and training.
- Contact details for ABB and its channel partners for sales and support.
Digital switchgear combines digital technologies with ABB's medium voltage switchgear platforms to provide increased flexibility, reliability, safety and efficiency. Key benefits include reduced footprint and weight, faster delivery and installation, increased switchgear and system reliability through digital communication protocols like IEC 61850, and improved safety during operation and maintenance through sensor technology. ABB offers digital versions of its UniGear, UniSec, ZX and SafePlus switchgear families. References showcase applications in data centers, smart city distribution networks, and other utility and industrial segments worldwide.
Itacoil is an Italian company that produces custom and standard PCB transformers and inductors. It was founded in 1981 and has since expanded its product portfolio and global reach. Itacoil prides itself on its customization capabilities, superior performance that saves customers time and costs, and technological leadership in LLC and LCC resonant topologies. The company has manufacturing facilities in Italy and Hong Kong and partners with major semiconductor brands on custom designs. It forecasts 2022 sales of 6.5 million euros across various product families and market sectors.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
A SYSTEMATIC RISK ASSESSMENT APPROACH FOR SECURING THE SMART IRRIGATION SYSTEMSIJNSA Journal
The smart irrigation system represents an innovative approach to optimize water usage in agricultural and landscaping practices. The integration of cutting-edge technologies, including sensors, actuators, and data analysis, empowers this system to provide accurate monitoring and control of irrigation processes by leveraging real-time environmental conditions. The main objective of a smart irrigation system is to optimize water efficiency, minimize expenses, and foster the adoption of sustainable water management methods. This paper conducts a systematic risk assessment by exploring the key components/assets and their functionalities in the smart irrigation system. The crucial role of sensors in gathering data on soil moisture, weather patterns, and plant well-being is emphasized in this system. These sensors enable intelligent decision-making in irrigation scheduling and water distribution, leading to enhanced water efficiency and sustainable water management practices. Actuators enable automated control of irrigation devices, ensuring precise and targeted water delivery to plants. Additionally, the paper addresses the potential threat and vulnerabilities associated with smart irrigation systems. It discusses limitations of the system, such as power constraints and computational capabilities, and calculates the potential security risks. The paper suggests possible risk treatment methods for effective secure system operation. In conclusion, the paper emphasizes the significant benefits of implementing smart irrigation systems, including improved water conservation, increased crop yield, and reduced environmental impact. Additionally, based on the security analysis conducted, the paper recommends the implementation of countermeasures and security approaches to address vulnerabilities and ensure the integrity and reliability of the system. By incorporating these measures, smart irrigation technology can revolutionize water management practices in agriculture, promoting sustainability, resource efficiency, and safeguarding against potential security threats.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
1. ADCs in ASICs
An Overview for System Designers
Dr. Mike Coulson
28/05/2015 Swindon Template Slides 01 1
2. Presentation Contents
28/05/2015 Swindon Template Slides 01 2
Introduction
The Benefits of an Integrated ADC
Essential Terminology for Describing ADCs
Types of ADC
The Challenges of Integration
To Integrate or Not?
Questions
3. Embedded sensor systems are typically mixed signal designs
Introduction
28/05/2015 Swindon Template Slides 01 3
Analog side
From
transducer
To main
system
Analog Digital
4. An ASIC is most useful when it contains the ADC too
Introduction
28/05/2015 Swindon Template Slides 01 4
Analog sideAnalog Digital
8. Dynamic Performance Measures
Reflect static & dynamic errors
Can be measured by FFT
SNR
− Fundamental limit
THD
− Just harmonic power
SINAD
− Both noise and harmonics
ENOB
Essential Terminology for Describing ADCs
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𝑆𝑁𝑅 (𝑑𝐵) = 6.02 𝑁 + 1.76
9. Many different architectures exist
We will discuss four of the most important
Difficult to quote absolute resolution and bandwidth
Types of ADC
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10. Flash ADCs
Highest speeds
Large (approx. 2N comparators), so constrained to low resolutions (8 bit)
Power hungry
Types of ADC : Flash
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11. Pipeline ADCs
Each sample passes through a series of stages, like a production line
Each stage adds further precision to the result, but also adds further ‘pipeline delay’
High speed, but high power
Popular for 8-14 bit applications
Types of ADC : Pipeline
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12. Successive Approximation (SAR) ADCs
SAR logic attempts to recreate input with an internal DAC
Several clock cycles per conversion, as different codes are tried
Popular for moderate speed applications, in the 8-14 bit range
Can be very power efficient
Types of ADC : SAR
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13. Sigma Delta ADCs
Type of oversampling
Popular in audio applications
Low speed
High resolution (16-18 bit)
Care required in design
Types of ADC : Sigma Delta
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14. Interference
Digital and analog circuits are poor neighbours on an ASIC…
Interference via shared power supplies
Interference via shared silicon substrate
The Challenges of Integration
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15. Small geometry processes may be required to suit digital portions of the ASIC
But analog performance may be compromised… for example:
Low supply voltages (to suit digital parts)
− These limit signal swings within the chip
− Robust design is more difficult (process, temperature, ageing)
− So partition into multiple supply domains, or use special circuit architectures
Capacitor, resistor and transistor matching
− Mismatch introduces INL and DNL
− So employ digital error correction and calibration
Success comes down to experience, and having a portfolio of proven circuits
The Challenges of Integration
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16. Not appropriate
To Integrate or Not?
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Where ADC performance is crucial
requiring a specialized fabrication process
Highly beneficial
Most automotive & industrial systems
e.g. process monitoring & control
When size or power is critical
e.g. hearing aids, medical implants
When cost is absolutely critical
so a mixed signal ASIC is the only option
Mike Coulson – design engineer at Swindon Silicon Systems in England. We design “Application Specific ICs” (ASICs).
My talk today concerns the growing use of analogue to digital converters (ADCs) within application specific ICs.
It is intended as a briefing for system designers who may opt to go down this advantageous route.
I will start with some further words of introduction about sensor systems and ASICs…
and why you would want to integrate an ADC within an ASIC
Then, because the ASIC design process is always a dialogue between the ASIC designer and their customer, I will explain some essential ADC concepts that may come in useful, including some key terminology and some common circuit architectures.
I will also describe some of the challenges that chip designers face when building ADCs within ASICs.
With this in mind, I can address the question: when is it appropriate to integrate an ADC , and when is it not?
Embedded sensor systems are often mixed signal designs, where an analogue input from a transducer (such as a voltage, or a current) is preconditioned, digitized by an ADC [circle ADC], and then subject to processing in the digital domain.
An ASIC is a custom designed silicon chip, which replaces numerous discrete components on a PCB.
The conventional ASIC solution would look like this [reveal ASIC board].
The analog functionality has been absorbed into an analog ASIC, and the digital functionality has been absorbed into a digital ASIC.
The ASIC solution is desirable because it is [reveal Cheap, small, robust] cheap, small and robust, having fewer parts to purchase, test and assemble.
But an ASIC is most useful when it contains the ADC too. This allows both the analogue and digital chips to be absorbed into the same package.
[Reveal single chip solution]. Taken to the extreme, you end up with your entire signal chain sitting within a single chip.
Now this is hugely advantageous. First, the benefits of cost, size and robustness are even more pronounced.
But having an integrated ADC is also [reveal flexible] more flexible, because the chip designer isn’t restricted to choosing an ‘off the shelf’ ADC, and can instead optimise the circuit for the task in hand.
It is also [reveal more convenient] more convenient, because the entire signal path comes under the care of the ASIC supplier, and the customer receives a complete, fully production-tested solution to drop into their product.
Although highly beneficial, ADC integration isn’t trivial, and the ASIC designer must work closely with the customer throughout.
For this reason, it’s important that the customer – the system level designer - should be familiar with how ADCs are specified. So I’ll now cover some essential ADC background.
We’ll start with essential terminology for describing ADCs.
At the simplest level, an ADC is specified in terms of conversion rate and resolution.
The conversion rate is perhaps self explanatory: the number of times the ADC can digitise its analogue input, each second.
The resolution (often given as the number of bits in the output) describes the number of different levels that the ADC can represent.
[Reveal transfer function] These output levels are called output codes. When you plot the output code against the input voltage, you obtain the ‘transfer function’.
The transfer function is described by the code transition voltages. For an ideal, linear transfer function the code transition voltages are evenly spaced.
This means that the input voltage range over which each output code is produced (termed the code width) is equal for every code.
[Reveal static performance measures] This brings us onto ‘static performance measures’, which describe deviations of the real transfer function from the perfectly linear case, and which are measured under DC inputs.
We now look at a non-linear transfer characteristic
The code transition voltages are not uniformly spaced
This means that some codes are ‘narrow’ (persisting over a smaller input range), and some codes are ‘wide’.
The code width error is termed the ‘DNL’. We typically specify the maximum DNL encountered across the whole input range.
Now you can perhaps see that error in a given code transition voltage will be the sum of all preceding code width errors.
For example, if the first 100 codes are all 1% too wide, the 100th code transition will occur a full code width higher than expected.
This cumulative sum of the DNL is termed the Integral Non-Linearity (or ‘INL’). We typically specify the maximum INL encountered across the whole input range.
As this graph shows, a higher resolution converter could have a small peak DNL, yet its INL may grow to a large value over hundreds of codes.
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In some applications, the INL matters, in others the DNL is more important.
For example, if we have a temperature sensor that measures an absolute value, the maximum INL might be of concern.
But if we measure a rate of change, exciting each code in sequence, the maximum DNL might be more critical.
So the application must always be properly understood when choosing an ADC.
We then have ‘dynamic performance measures’, which describe output signal purity under a full scale sinusoidal input, shown by the dotted line.
They are typically measured by taking an FFT of the output.
Dynamic performance is always worse than static performance, as it reflects dynamic errors such as the incomplete charging of capacitors, and the finite bandwidth of amplifiers.
The first dynamic performance measure is the signal to noise ratio (SNR), which describes general noise and interference in the ADC’s output
The SNR is fundamentally limited by the ‘quantisation error’ that is always present between the input and it’s digitised representation.
A classic equation relates the SNR limit to the converter resolution. Unsurprisingly, when the resolution is increased, the quantisation errors become smaller, and the SNR limit is improved.
(The equation makes sense: it says that for each extra bit of resolution, which will halve the quantisation error, the noise power will fall by 6dB which is the expected factor of 4).
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The THD is the Total Harmonic Distortion, and represents only harmonic power in the output spectrum. It is particularly important for audio applications.
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The SINAD measures both noise and harmonics, so gives a measure of overall signal purity.
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Finally, the ENOB is an intuitive way of describing the SINAD. It is the resolution of a perfect converter that has the same noise and distortion as the real one under test.
So you may find a 16-bit ADC that seems perfect for your application, but which starts to look less attractive when you discover it has an ENOB of 12.
Difficult to quote absolute resolution and bandwidth, because these are so process dependent.
we’ll choose cheapest process we can, to maximise savings for customer
process choice may be a compromise to suit analog and digital aspects of the ASIC
We will start with flash ADCs, which are the fastest but also the largest and most power hungry.
They are large because they consist of a large bank of comparators, each fed with a staggered reference voltage from a resistor ladder.
Each comparator simultaneously compares the input voltage with its own reference, explaining both the high speed and high power consumption.
Flash ADCs are reserved for the highest speed applications, such as communications systems.
Pipeline delay may cause instability in closed-loop control systems.
Sigma Delta ADCs employ a form of oversampling. In oversampling, many noisy low resolution conversions are averaged to obtain a single high resolution result.
This is usually taken to the extreme, where the low resolution conversion results are 1-bit. The output is then a random PWM signal.
The random PWM signal is then digitally averaged (that is, passed through a filter) to remove high frequencies, and recover a high resolution result.
Digital circuitry is noisy: it draws current from the power rail at high frequency, and dumps it to the ground.
This disturbs not only the power supplies, but the voltage of the silicon substrate, in which the analogue circuits are built.
Low supply voltages
- Limited signal swings: signals can’t exceed the power supply voltages, and in many circuits can’t be allowed to approach them
- Robustness to variations in the fabrication process, variations in temperature, and variations as the chip ages
requires voltage margins… but with low supply voltages, you have little margin to play with
Solution
- This is a well known problem, and there are clever circuit architectures that can help.
- Some processes provide both high voltage and low voltage transistors, so you can partition the chip into multiple supply domains, if you can tolerate the complexity & extra pins.
Poorer matching – multiple supply domains and device geometries are an option.
(High leakage currents – architectural solutions such as digital error correction exist to counter this kind of effect)
This is where experience counts: in truth, a lot of these solutions come down to experience of what works and what doesn’t, and if you’ve done a lot of this kind of integration you build up a porfolio
so as you want an ASIC supplier who has previously run into these problems and has a library of optimised circuit blocks to draw elements from.
The primary reasons to integrate an ADC are reduction of cost and size.
So we’d normally do this on a absolute budget, using the cheapest process options, to maximise the customer’s return.
For this reason, an integrated ADC is unlikely to match the performance of a cutting edge discrete.
So where ADC performance is crucial, requiring a specialized fabrication process, integration is probably not appropriate.
However, a mixed signal ASIC brings considerable benefits in the vast majority of cases.