The document presents a seminar on a novel high-speed multiplier design using a hybrid adder technique, addressing challenges associated with multiplier designs. It includes details on methodology, FPGA implementation, and performance analysis, showing that the hybrid multiplier outperforms traditional adders like Brent Kung and Kogge Stone in terms of speed and delay. Future work aims to reduce logic complexity while maintaining efficiency.

1. NATIONAL INSTITUTE OF TECHNOLOGY,SILCHAR
A Novel Design of High Speed Multiplier
Using Hybrid Adder Technique
DEPARTMENT OF ELECTORNICS & COMMUNICATION
BY
Anirban Nath (2424223)
M.Tech (1ST Sem)
A Seminar Presentation on

2. Outline of the Presentation
1 Introduction
What are multipliers, challenges of multiplier design?
2 Methodology
Hybrid adder design, FPGA implementation.
3 Results & Discussion
Performance analysis and comparison .
4 Conclusion & References
Summary, future directions, and relevant citations.
5 Q&A
Open for questions and discussion.

3. Introduction
1 Multipliers: Essential Circuits
2 Applications

4. Delay Power Area

5. Proposed Solution: Hybrid Multiplier
Brent Kung Adder
Kogge Stone Adder
Hybrid Adder
Combines strengths of both

6. Methodology
Hybrid Adder

7. 8-bit Hybrid Adder [1]
Designed for smaller data sizes.
Cout

8. 12-bit Hybrid Adder [1]
Mid-range data size.

9. 16-bit Hybrid Adder [1]
Designed for larger data sizes.

10. Step 1
AND operation of input bits.
Step 2
Generation of partial products.
Step 3
Addition of partial products using a
hybrid adder.
Fig -Partial Product Generation [1]

11. 1 Simulation
Xilinx ISE software
2 FPGA Board
Artix-7
3 Hybrid Multiplier
Designed and tested

12. Results & Discussion
Delay
Brent Kung - 4.315 nsec
Kogge Stone- 4.618 nsec
Hybrid adder - 4.062 nsec

13. Results & Discussion
Key Results
Proposed hybrid multiplier delay: 4.062 ns.
Speed improvement:
6.22% vs. Brent Kung Adder
13.68% vs. Kogge Stone Adder

14. Results & Discussion
Trade-offs:
Faster and more efficient in terms of delay and speed.
higher logic complexity

15. Conclusion
Hybrid adder-based multiplier achieves lower delay and better speed
efficiency.
Future Work: Reducing the logic complexity of the proposed design.

16. References
.N. Leela, D. Keerthi Chandrika, K. Swetha, D. G. Kalali and G. Shanthi, "A Novel Design of High Speed
Multiplier Using Hybrid Adder Technique," 2024 3rd International Conference for Innovation in Technology
(INOCON), Bangalore, India, 2024.
1.
Safiullah Khan, Khalid Javeed, Yasir Ali Shah,High-speed FPGA implementation of full-wordMontgomery
multiplier for ECC applications,Microprocessors and Microsystems,Volume 62,2018
2.
H. Waris, C. Wang and W. Liu, "Hybrid Low Radix Encoding-Based Approximate Booth Multipliers," in
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3367-3371, Dec. 2020
3.
H. Waris, C. Wang, W. Liu, J. Han and F. Lombardi, "Hybrid Partial Product-Based High-Performance
Approximate Recursive Multipliers," in IEEE Transactions on Emerging Topics in Computing, vol. 10, no.
1, pp. 507-513, 1 Jan.-March 2022,
4.
M. S. Ansari, H. Jiang, B. F. Cockburn and J. Han, "Low-Power Approximate Multipliers Using Encoded
Partial Products and Approximate Compressors," in IEEE Journal on Emerging and Selected Topics in
Circuits and Systems, vol. 8, no. 3, pp. 404-416, Sept. 2018,
5.
M. A. A. Amin, M. Kartiwi, M. Yaacob, E. A. Z. Hamidi, T. S. Gunawan and N. Ismail, "Design of Brent
Kung Prefix Form Carry Look Ahead Adder," 2022 8th International Conference on Wireless and
Telematics (ICWT), Yogyakarta, Indonesia, 2022,
6.

17. Thank You
Any Questions?