The document presents a seminar on designing a high-speed multiplier using a hybrid adder framework, highlighting the importance of multipliers and their applications. It discusses the methodology involving a hybrid adder and FPGA implementation, along with performance analysis showing speed improvements and trade-offs in complexity. The conclusion indicates that the hybrid adder design achieves lower delay and higher speed efficiency, with future work aimed at reducing logic complexity.

1. NATIONAL INSTITUTE OF TECHNOLOGY,SILCHAR
Design of A High Speed Multiplier Using
Hybrid Adder Framework
DEPARTMENT OF ELECTORNICS & COMMUNICATION
BY
Anirban Nath (2424223)
M.Tech (1ST
Sem)
A Seminar Presentation on

2. Outline of the Presentation
1 Introduction
What are multipliers, challenges of multiplier design?
2 Methodology
Hybrid adder design, FPGA implementation.
3 Results & Discussion
Performance analysis and comparison .
4 Conclusion & References
Summary, future directions, and relevant citations.
5 Q&A
Open for questions and discussion.

3. Introduction
1 Multipliers: Essential Circuits
2 Applications

4. Delay Power Area

5. Proposed Solution: Hybrid Multiplier
Brent Kung Adder
Kogge Stone Adder
Hybrid Adder
Combines strengths of both

6. Carry Select Adder
[1
]

7. Carry Select Adder
=0
0
0
0
0 1
1
1
1
0
1

8. Carry Select Adder
=1
0
0
0
0 1
1
1
0
1
1

9. Kogge Stone Adder

10. Kogge Stone Adder
Pre-Processing State
Generation of Carry
Final Processing State
Gi= (Pi AND Gi*) OR Gi
Pi= (Pi AND Pi*)
Ci=Gi
Si=Pi XOR Ci*

11. Brent Kung Adder

12. Brent Kung Adder
Pre-Processing State
Generation of Carry
Final Processing State
Cp= (Pi AND P*)
Cg= Gi OR (Pi AND G*)
Ci=Cg
Si=Pi XOR Ci*

13. Brent Kung Adder Kogge Stone Adder

14. Gi= (Pi AND Gi*) OR Gi
Pi= (Pi AND Pi*)
Ci=Gi
Si=Pi XOR Ci*
P G
A=1010101
0
B=11001100
P G
C0=0
S0=0
C1=0
S1=1
C2=0
S2=1
C3=1
S3=0
C4=0
S4=1
C5=0
S5=1
C6=0
S6=1
C7=1
S7=0
Sum- 101110110
P G
P G
P G
P G
P G

15. Methodology
Hybrid Adder

16. 8-bit Hybrid Adder [1]
Designed for smaller data sizes.
Cou
t

17. 12-bit Hybrid Adder [1]
Mid-range data size.

18. 16-bit Hybrid Adder [1]
Designed for larger data sizes.

19. Step 1
AND operation of input bits.
Step 2
Generation of partial products.
Step 3
Addition of partial products using a
hybrid adder.
Fig -Partial Product Generation
[1]

20. 1 Simulation
Xilinx ISE software
2 FPGA Board
Artix-7
3 Hybrid Multiplier
Designed and tested

21. Results & Discussion

22. Results & Discussion
Key Results
• Proposed hybrid multiplier delay: 4.062 ns.
• Speed improvement:
⚬6.22% vs. Brent Kung Adder
⚬13.68% vs. Kogge Stone Adder

23. Results & Discussion
• Trade-offs:
⚬Faster and more efficient in terms of delay and speed.
⚬ higher logic complexity

24. Conclusion
Hybrid adder-based multiplier achieves lower delay and better speed
efficiency.
Future Work: Reducing the logic complexity of the proposed design.

25. References
1. .N. Leela, D. Keerthi Chandrika, K. Swetha, D. G. Kalali and G. Shanthi, "A Novel Design of High Speed
Multiplier Using Hybrid Adder Technique," 2024 3rd International Conference for Innovation in Technology
(INOCON), Bangalore, India, 2024.
2. Safiullah Khan, Khalid Javeed, Yasir Ali Shah,High-speed FPGA implementation of full-wordMontgomery
multiplier for ECC applications,Microprocessors and Microsystems,Volume 62,2018
3. H. Waris, C. Wang and W. Liu, "Hybrid Low Radix Encoding-Based Approximate Booth Multipliers," in
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3367-3371, Dec. 2020
4. H. Waris, C. Wang, W. Liu, J. Han and F. Lombardi, "Hybrid Partial Product-Based High-Performance
Approximate Recursive Multipliers," in IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 1,
pp. 507-513, 1 Jan.-March 2022,
5. M. S. Ansari, H. Jiang, B. F. Cockburn and J. Han, "Low-Power Approximate Multipliers Using Encoded
Partial Products and Approximate Compressors," in IEEE Journal on Emerging and Selected Topics in
Circuits and Systems, vol. 8, no. 3, pp. 404-416, Sept. 2018,
6. M. A. A. Amin, M. Kartiwi, M. Yaacob, E. A. Z. Hamidi, T. S. Gunawan and N. Ismail, "Design of Brent Kung
Prefix Form Carry Look Ahead Adder," 2022 8th International Conference on Wireless and Telematics
(ICWT), Yogyakarta, Indonesia, 2022,

26. Thank You
Any Questions?