2820.pdf

Biasing in BJT Amplifier Circuits
The biasing problem is that of establishing a constant dc current in the collector of the
BJT. This current has to be calculated, predictable, and insensitive to the variations in
temperature and to a large variations in the value of β encountered among the
transistors of the same type.
Attempting to bias the BJT by fixing the voltage VBE by using a voltage divider across
the power supply VCC, as shown in figure below (a) is not viable approach. The very
sharp exponential relationship iC – vBE means that any small and inevitable differences
in VBE from the desired value will result in large differences in IC and VCE. Secondly,
biasing the BJT by establishing a constant current in the base, as shown in (b) below,
where IB ≡ (VCC – 0.7)/RB, is also not recommended approach. Here the typical large
variations in the value of β among units of the same device type will result in
corresponding large variations in IC and hence VCE.

Two obvious schemes for biasing the BJT: (a) by fixing VBE; (b) by fixing IB. Both
result in wide variations in IC and hence in VCE and therefore are considered to be
“bad.” Neither scheme is recommended.

The Classical Discrete-Circuit Bias Arrangement
Figure (a) below shows the arrangement most commonly used for biasing a discrete-circuit
transistor amplifier if only a single power supply is available. The technique consists of
supplying the base of the transistor with a fraction of supply voltage VCC through the voltage
divider R1, R2. In addition, a resistor RE is connected to the emitter. The figure in (b) below
shows the same circuit with the voltage divider network replaced by its Thevenin equivalent.
Classical biasing for BJTs using a single
power supply:
(a) circuit;
(b) circuit with the voltage divider
supplying the base replaced with its
Thevenin equivalent.

2
1
2
1
2
1
2
R
R
R
R
R
V
R
R
R
V
B
CC
BB




The current IE can be determined by writing a Kirchhoff’s loop equation for the base-emitter-ground, labelled L, and by
substituting IB = IE /(β + 1):
)
1
/( 




B
E
BE
BB
E
R
R
V
V
I
…(3.1)
…(3.2)
…(3.3)

To make IE insensitive to temperature and β variations, we design the circuit to satisfy the
following two constraints:
1




B
E
BE
BB
R
R
V
V
Condition given above for VBB ensures that small variations in VBE (≈0.7 V) will be swamped by the
much larger VBB. There is a limit on how large VBB can be: for a given value of the supply voltage VCC,
the higher the value of VBB, the lower will be the sum of the voltage across RC and the collector base
junction (VCB). On the other hand we want the voltage across RC to be large in order to obtain high
voltage gain and large signal swing (before transistor saturation). As a rule of the thumb, one designs
for VBB about 1/3 VCC, VCB (or VCE) about 1/3 VCC and ICRC about 1/3 VCC.
Condition given by RE makes IE insensitive to variations in β and could be satisfied by selecting RB
small. This in turn is achieved by using low values of R1 and R2. Lower values of R1 and R2 will mean
higher current drain from the power supply, and will result in lowering of the input resistance of the
amplifier (if the input resistance is coupled to the base). Typically one selects R1 and R2 such that their
current is in the range of IE to 0.1IE.
…(3.4)
…(3.5)

A Two-Power-Supply Version of the Classical Bias Arrangement
A somewhat simpler bias arrangement is possible if the two power supplies are available, as
shown in figure below:
Biasing the BJT using two power supplies. Resistor RB is
needed only if the signal is to be capacitively coupled to the
base. Otherwise, the base can be connected directly to
ground, or to a grounded signal source, resulting in almost
total β -independence of the bias current.

Writing the loop equation for the loop L gives:
)
1
( 




B
E
BE
EE
E
R
R
V
V
I
This equation is identical to equation of IE given earlier except for VEE replacing VBB. Thus
the two constraints of the equations given before apply here also. Note that if the transistor is
to be used with the base grounded (i.e.) in the common-base configuration, then RB can be
eliminated altogether. On the other hand, if the input signal is to be coupled to the base, then
RB is needed.
…(3.6)

Biasing Using a Collector-To-Base Feedback Resistor
Figures given below shows a simple but effective alternative biasing arrangement suitable for
common-emitter amplifiers.
(a) A common-emitter transistor
amplifier biased by a feedback
resistor RB.
(b) Analysis of the circuit in (a).

BE
B
E
C
E
BE
B
B
C
E
CC
V
R
I
R
I
V
R
I
R
I
V







1

Thus the emitter bias current is given by
)
1
( 




B
C
BE
CC
E
R
R
V
V
I
…(3.7)
…(3.8)
…(3.9)

It is interesting to note that this equation is identical to equation given earlier,
which governs the operation of the traditional bias current, except that VCC
replaces VBB and RC replaces RE. It follows that to obtain a value of IE that is
insensitive to variation of β, we select RB / (β + 1) << RC. Note that the value of
RB determines the allowable signal swing at the collector since
1




B
E
B
B
CB
R
I
R
I
V …(3.10)

Biasing Using a Constant Current Source
The BJT can be biased using a constant current source I as indicated in the
circuit of Figure (a) below. This circuit has the advantage that the emitter
current is independent of the values of β and RB. Thus RB can be made large,
enabling as increase in the input resistance at the base without adversely
affecting bias stability. Further, current source biasing leads to significant design
simplification.
A simple implementation of the constant current source is shown in Figure (b)
below. The circuit utilizes a pair of matched transistors Q1 and Q2, with Q1
connected as diode by shorting its collector to its base. If we assume that Q1 and
Q2 have high β values, we can neglect their base currents. Thus the current
through Q1 will be approximately equal to IREF.

R
V
V
V
I
I
R
V
V
V
I
BE
EE
CC
REF
BE
EE
CC
REF








)
( Since Q1 and Q2
have the same
VBE, their
collector currents
will equal
resulting in I.
Neglecting the Early effect in Q2, the
collector current will remain constant at
the value given by equation above as
long as Q2 remains in the active region.
This can be guaranteed by keeping the
voltage in the collector, V, greater than
that of the base (-VEE + VBE). The
connection of Q1 and Q2 in the figure (b)
above is known as a current mirror.
…(3.11)
…(3.12)

Biasing In MOS Amplifier Circuits
An essential step in design of a MOSFET amplifier circuits is the establishment of an
appropriate dc operating point for the transistor. This is the step known as biasing or bias
design. An appropriate dc operating point or bias point is characterized by a stable and
predictable dc drain current ID and by a dc drain-to-source voltage VDS that ensures
operation in saturation region for all expected input-signal levels.
Biasing By Fixing VGS
The most straightforward approach to biasing a MOSFET is to fix its gate-to-source
voltage VGS to the value required to provide the desired ID. This voltage value can be
derived from the power supply voltage VDD through the use of an appropriate voltage
divider. Independent of how the voltage VGS may be generated, this is not a good
approach to biasing a MOSFET. To understand the reason for this statement, recall that

2
)
(
2
1
t
GS
ox
n
D V
V
L
W
C
I 
 
And recall that the values of the threshold voltage Vt, the oxide-capacitance Cox,
and the transistor aspect ratio W/L vary widely among devices of supposedly the
same size and type. Furthermore, both Vt and μn depend on temperature, with
the result that if we fix the value of VGS, the drain current ID becomes very much
temperature dependent. To emphasize the point that biasing by fixing VGS is not
good technique, we see in the figure given below that iD – vGS characteristic
curves representing extreme values in a batch of MOSFETs of the same type.
Observe that for the fixed value of VGS, the resultant spread in the values of the
drain current can be substantial.
…(3.13)

The use of fixed bias
(constant VGS) can result in
a large variability in the
value of ID. Devices 1 and 2
represent extremes among
units of the same type.

Biasing by Fixing VG and Connecting a Resistance in the Source
An excellent biasing technique for the discrete MOSFET circuits consists of fixing the dc
voltage at the gate VG, and connecting a resistance in the source lead, as shown in Figure (a)
Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS:
(a) basic arrangement; (b) reduced variability in ID;
(c) practical implementation using a single supply;

For the circuit in (a) above we can write
D
S
GS
G I
R
V
V 

Now if VG is much greater than VGS, ID will be mostly determined by the values
of VG and RS. However, even if VG is not much larger than VGS, resistor RS
provides negative feedback, which acts to stabilize the value of the bias current
ID.
Equation above indicates that since VG is constant, VGS will have to decrease, for
an increase in ID for whatever reason. This in turn results in decrease in ID, a
change that is opposite to that initially assumed. Thus the of RS works to keep ID
as constant as possible. This negative feedback action of RS gives it the name
degenerative resistance.
…(3.14)

Figure (b) above provides a graphical illustration of the effectiveness of this biasing scheme. Here we
show that iD – vGS characteristics for the two devices that represent the extremes of a batch of
MOSFETs. Superimposed on the device characteristics is straight line that represents the connection
imposed by the bias circuit as seen in the equation above. The intersection of this straight line with the
iD – vGS characteristic curve provide the coordinate (ID and VGS) of the bias point. Observe that
compared to the case of fixed VGS, here the variability obtained in ID is much smaller. Two possible
practical discrete implementation of the bias scheme are shown in Figure (c) and (e).
(d) coupling of a signal
source to the gate using a
capacitor CC1;
(e) practical implementation
using two supplies.

The circuit in (c) utilizes one power-supply VDD and derives VG through voltage divider (RG1,
RG2). Since IG = 0, RG1 and RG2 can be selected to be very large (in MΩ range), allowing the
MOSFET to present a large input resistance to a signal source that may be connected to the
gate through a coupling capacitor as shown in (d) above. When two power supplies are
available, the somewhat simpler bias arrangement of figure (e) can be utilized. This circuit is
an implementation of the Equation given above with VG replaced by VSS. Resistor RG
establishes a dc ground at the gate and presents a high input resistance to a signal source that
may be connected to the gate through a coupling capacitor.
Biasing Using a Drain - to - Gate Feedback Resistor
A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor
between the drain and gate is shown in the Figure below.

Biasing the MOSFET using a large drain-to-gate feedback
resistance, RG.
Here the large feedback resistance RG (usually in MΩ range)
forces the dc voltage at the gate to be equal to that at the drain
(because IG = 0). Thus we can write
D
D
DD
DS
GS I
R
V
V
V 


Which can be written in the form
D
D
GS
DD I
R
V
V 

…(3.15)
…(3.16)

Which is identical to the first equation, which describes the operation of the bias scheme
above. Thus, here too, if ID for some reason changes, say increases, then Equation above for
VDD indicates that VGS must decrease. The decrease in VGS in turn causes a decrease in ID, a
change that is opposite in direction to the one originally assumed. Thus the negative
feedback or degeneration provided by RG works to keep the value of ID as constant as
possible.

Biasing Using a Constant Current Source
The most effective scheme for biasing a MOSFET amplifier is that using a
constant current source. Figure (a) given below shows such an arrangement
applied to discrete MOSFET. Here, RG (usually in MΩ range) establishes a dc
ground at the gate and presents large resistance to an input signal source that
can be capacitively coupled to the gate. Resistor RD establishes an appropriate
dc voltage at the drain to allow for the required output signal swing while
ensuring that the transistor always remains in the saturation region.
A circuit for implementing the constant current source I is shown in Figure (b)
below. The heart of the circuit is transistor Q1, whose drain is shorted to its gate
and thus is operating in the saturation region, such that

2
1
'
1 )
(
2
1
t
GS
n
D V
V
L
W
k
I 






 …(3.17)

Where we have neglected channel-length modulation (i.e. assumed λ = 0). The
drain current of Q1 is supplied by VDD through resistor R. Since the gate currents
are zero,
R
V
V
V
I
I GS
SS
DD
REF
D




1
Where the current through R is considered to be the reference current of the
current source and is denoted as IREF. Given the parameter values of Q1 and is a
desired value for IREF, Equations (3.17) and (3.18) above can be used to
determine the value of R. Now consider transistor Q2: It has the same VGS as Q1;
thus we can assume that it is operating in saturation, its drain current, which is
the desired current I of the current source, will be
…(3.18)

2
2
'
2 )
(
2
1
t
GS
n
D V
V
L
W
k
I
I 








Where we have neglected channel-length modulation. Equations (3.17) and
(3.19) above enable us to relate the current I to the reference current IREF as
 
 1
2
L
W
L
W
I
I REF

Thus I is related to IREF by the ratio of the aspect ratios Q1 and Q2. This circuit
is known as the current mirror.
…(3.19)
…(3.20)

Single Stage BJT Amplifiers
There are basically three configurations for implementing the single-stage BJT amplifiers: The
common-emitter, The common-base, and the common-collector configurations. All three are
studied utilizing the same basic structure with the same biasing arrangement.
The Basic Structure
The figure given below shows the basic circuit that we shall utilize to implement the various
configurations of BJT amplifiers. Among the various biasing schemes possible for discrete BJT
amplifiers, we have selected, for simplicity and effectiveness, the one with constant current
source. Figure given below indicates the dc currents in all the branches and all the dc voltages at
all nodes. We should note that one would want to select a large value for RB in order to keep the
input resistance at the base large. However, we also want to limit the dc voltage drop across RB
and even more importantly the variability of this dc voltage resulting from the variation in β
values among transistors of the same type. The dc voltage VB determines the allowable signal
swing at the collector.

Basic structure of the circuit used to realize single-stage, discrete-circuit BJT amplifier
configurations.

The Common Emitter (CE) Amplifier
Figure (a) given below shows a CE amplifier implemented using the circuit of the above figure.
To stablish a signal ground at the emitter, a large capacitor CE usually in the μF or tens of μF
range, is connected between the emitter and the ground. This capacitor is required to provide a
very low impedance to ground (ideally zero impedance, i.e., in effect, short circuit) at all the
signal frequencies of interest. In this way, the emitter signal current passes through CE to
ground and thus bypasses the output resistance of the current source I. Hence, CE is called a
bypass capacitor. Obviously the lower the signal frequency, the less effective the bypass
capacitor becomes. Hence, we shall assume that CE is acting as a perfect short circuit and thus
is establishing a zero signal voltage at the emitter.

(a) A common-emitter amplifier using the structure of the previous figure

(b) Equivalent circuit obtained by replacing the transistor with its hybrid-π model.

In order not to disturb the dc bias currents and voltages, the signal to be
amplified shown as voltage source vsig with an internal resistance Rsig is
connected to the base through a large capacitor CC1. The Capacitor CC1 is known
as the coupling capacitor. This is required to act as a perfect short circuit at all
signal frequencies of interest while blocking dc.
The voltage signal resulting at the collector, vc, is coupled to the load resistance
RL via another coupling capacitor CC2. We shall assume that CC2 also acts as a
perfect short circuit at all signal frequencies of interest; thus the output vo = vc.
To determine the terminal characteristics of the CE amplifier, that is, its input
resistance, voltage gain, and output resistance, we replace the BJT with the
hybrid-π small-signal model. The resulting small-signal equivalent circuit of the
CE amplifier is shown in the Figure (b) above. We observe at the outset that this
amplifier is unilateral and thus Rin = Ri and Rout = Ro. Analysis of this circuit is
given as

ib
B
i
i
in R
R
i
v
R ||


Where Rib is the input resistance looking into the base. Since the emitter is grounded,

r
Rib 

r
Rin 
Normally, we select RB >> rπ, with the result that
…(3.21)
…(3.22)
…(3.23)

Thus, we note that the input resistance of the CE amplifier will typically be a few kilo ohms,
which can be thought as low to moderate. The fraction of source signal vsig that appears across
the input terminals of the amplifier can be found from
 
  sig
B
B
sig
sig
in
in
sig
i
R
r
R
r
R
v
R
R
R
v
v






||
||
sig
sig
i
R
r
r
v
v




Which for RB >> rπ becomes
…(3.24)
…(3.25)
…(3.26)

Next we note that vπ = vi. Hence, at the output of the amplifier we have
)
||
||
( L
C
o
m
o R
R
r
v
g
v 


Replacing vπ by vi we can write for the voltage gain of the amplifier as
)
||
||
( L
C
o
m
v R
R
r
g
A 

The open circuit voltage gain can be obtained by setting RL = ∞. Thus
)
||
( C
o
m
vo R
r
g
A 

…(3.27)
…(3.28)
…(3.29)

Typically, ro >> RC, resulting in
C
m
vo R
g
A 

The output resistance
Rout can be found from
the equivalent circuit of
Figure (b) above by
looking back into the
output terminal while
short-circuiting the
source vsig. Since this
will result in vπ = 0, we
see that C
out
C
o
o
C
out
R
R
implies
R
r
now
r
R
R


 ||
…(3.30)
…(3.31)

Recalling that for this unilateral amplifier Ro = Rout we can utilize Avo and Ro to
obtain the voltage gain Av corresponding to any particular RL,
o
L
L
vo
v
R
R
R
A
A


The overall volatge gain from source to the load, Gv, can be obtained by
multiplying (vi / vsig) from the equations (3.24, 3.25, 3.26) above by Av we get
 
 
)
||
||
(
||
||
L
C
o
m
sig
B
B
v R
R
r
g
R
r
R
r
R
G





…(3.32)
…(3.33)

For the case RB >> rπ, this expression simplifies to
 
sig
o
L
C
v
R
r
r
R
R
G




 ||
||
For this expression we note that if Rsig >> rπ, the overall gain will be highly dependent on β.
This is not at all desirable. On the other hand if Rsig << rπ, we see that the expression for the
overall gain reduces to
 
o
L
C
m
v r
R
R
g
G ||
||


…(3.34)
…(3.35)

Which is the gain Av. In other words, when Rsig is small, the overall voltage gain is almost equal
to the gain of the CE circuit, which is independent of β. The short circuit current gain Ais can be
found out by referring the Figure (b) above. When RL is short circuited, the current through it
will be equal to -gmvπ.

v
g
i m
os 

Since vπ is related to ii by
in
i
i R
i
v
v 


…(3.36)
…(3.37)

The short circuit current gain can be found as
in
m
i
os
is R
g
i
i
A 


Substituting Rin = RB || rπ we can see that in the case of RB >> rπ, |Ais| reduces to
β, which is to be expected since β is, by definition, the short-circuit current gain
of the common-emitter configuration.
In conclusion, the common-emitter configuration can provide large voltage and
current gains, but Rin is relatively low and Rout is relatively high.
…(3.38)

The Common-Emitter Amplifier with an Emitter Resistance
Including a resistance in the signal path between the emitter and ground, as
shown by Figure (a) below can lead to significant changes in the amplifier
characteristics. Thus such a resistor can be utilized by the designer as an effective
design tool for tailoring the amplifier characteristics to fit the design
requirements.

(a) A common-emitter amplifier with an emitter resistance Re.

(b) Equivalent circuit obtained by replacing the transistor with its T model.

the input resistance looking into the base is (β+1) times the total resistance in the
emitter. Multiplication by the factor (β+1) is known as the resistance reflection
rule.
…(3.39)
…(3.40)
…(3.41)
…(3.42)

Thus the circuit designer can use the value of Re to control the value of Rib and hence Rin. To
determine the voltage gain Av,
…(3.43)
…(3.44)
…(3.45)
…(3.46)

The voltage gain from base to collector is equal to the ratio of the total resistance
in the collector to the total resistance in the emitter. The open-circuit voltage
gain Avo can be found by setting RL = ∞
Which can be expressed as
  e
m
C
m
e
e
C
m
vo
e
e
C
e
vo
R
g
R
g
r
R
R
g
A
r
R
R
r
A










1
1
1

…(3.47)
…(3.48)
…(3.49)

We observe here that reducing the Re reduces the voltage gain by the factor (1 + gmRe) which
is the same factor by which Rib is increased. The output resistance Rout can be found out from
the Figure (b) above by inspection:
C
out R
R 
The short circuit current gain Ais can be found from the circuit in Figure (b) above as follows:
…(3.50)
…(3.51)
…(3.52)
…(3.53)

Which is the case with RB >> Rib, which is seen to be same value for the CE case. The overall
voltage gain from the source to the load can be obtained by multiplying Av by (vi / vsig)
 
e
e
L
C
sig
in
in
v
sig
i
v
R
r
R
R
R
R
R
A
v
v
G





||

Substituting for Rin by RB || Rib, assuming that RB >> Rib, and substituting for Rib from the
previous equation (3.42) results in
 
  
e
e
sig
L
C
v
R
r
R
R
R
G





1
||


…(3.54)
…(3.55)

We note that the gain is lower than the CE amplifier because of the additional term (β+1)Re in
the denominator. The gain. However, is less sensitive to the value of β, which is a desirable
result. From the circuit in Figure (b) above we see that
e
m
e
e
e
i R
g
R
r
r
v
v




1
1

To summarize, including a resistance Re in the emitter of the CE amplifier results in the
following characteristics:
1. The input resistance Rib is increased by the factor (1 + gmRe).
2. The voltage gain from base to collector, Av, is reduced by the factor (1 + gmRe).
3. For the same nonlinear distortion, the input signal vi can be increased by the factor (1 +
gmRe).
4. The overall voltage gain is less dependant on the value of β.
5. The high frequency response is significantly improved.
…(3.56)

The Common-Base (CB) Amplifier
By establishing a signal ground on the base terminal of the BJT, a circuit
configuration named as common-base or grounded-base amplifier is obtained.
The input signal is applied to the emitter, and the output is taken at the collector,
with the base forming a common terminal between the input and output ports.
Figure (a) given below shows a CB amplifier. Observe that since both the dc and
ac voltages at the base are zero, we have connected the base directly to ground,
thus eliminating resistance RB altogether. Coupling capacitors CC1 and CC2
perform the similar functions to those in the CE circuit.
The small-signal equivalent circuit of the amplifier is given in Figure (b) below.

From inspection of the equivalent circuit model in Figure (b) above, we see that the input
resistance is
e
in r
R  …(3.57)

This should have been expected since we are looking into emitter and the base is
grounded. Typically re is a few ohms to a few tens of ohms; thus CB amplifier has a low
input resistance. To determine the voltage gain, we write at the collector node
 
L
C
e
o R
R
i
v ||



And substituting for the emitter current from
e
i
e
r
v
i 

…(3.58)
…(3.59)

We obtain
   
L
C
m
L
C
e
i
o
v R
R
g
R
R
r
v
v
A ||
|| 



Which except for the positive sign is identical to the expression for Av for the CE amplifier.
The open circuit voltage gain Avo can be found out from the previous equation (3.60) by
setting RL = ∞;
C
m
vo R
g
A 
…(3.60)
…(3.61)

Again this is identical to Avo for the CE amplifier except that the CB amplifier is noninverting.
The output resistance from the circuit in (b) above is given as
C
out R
R 
Which is similar to the case of the CE amplifier. The short circuit current gain is given as









e
e
i
e
is
i
i
i
i
A
Which corresponds to our definition of α as the short-circuit current gain of the CB
configuration. The low input resistance of the CB amplifier can cause the input signal to be
severely attenuated. Neglecting ro Rin = Ri , Rout = Ro. Specifically
…(3.62)
…(3.63)

e
sig
e
i
sig
i
sig
i
r
R
r
R
R
R
v
v




The overall voltage gain Gv of the CB amplifier can be obtained by multiplying the ratio vi/vsig
by Av. Thus
 
 
e
sig
L
C
L
C
m
e
sig
e
v
r
R
R
R
R
R
g
r
R
r
G




||
||

…(3.64)
…(3.65)
…(3.66)

We see that since α is roughly equal to unity the overall voltage gain is simply the ratio of the
total resistance in the collector circuit to the total resistance in the emitter circuit. We also note
that the overall voltage gain is almost independent of the value of β which is a desirable
property. For Rsig of the same order as RC and RL, the gain will be very small.
In summary, the CB amplifier exhibits a very low input resistance (re), a short circuit current
gain that is nearly unity (α), an open-circuit voltage gain that is positive and equal in magnitude
to that of the CE amplifier (gmRC), and like CE amplifier, a relatively high output resistance
(RC).
Finally a very significant application of the CB circuit is a unity-gain current amplifier or
current buffer: It accepts an input signal current at a low input resistance and delivers a nearly
equal current at a very high output resistance at the collector (the output resistance excluding
RC and neglecting ro is infinite).

The Common-Collector (CC) Amplifier or Emitter Follower
The CC Amplifier is shown in Figure (a) below. Observe that the collector is to be at signal
ground, we have eliminated the collector resistance RC. The input signal is capacitively
coupled to the base, and the output signal is capacitively coupled from the emitter to a load
resistance RL. Unlike the CE and CB circuits, the emitter-follower circuit is not unilateral; that
is the input resistance depends on RL, and the output resistance depends on Rsig.
(a) An emitter-follower
circuit

(b) Small-signal equivalent circuit of the emitter follower with the transistor replaced by
its T model augmented with ro.

(c) The circuit in (b) redrawn to emphasize that ro is in parallel with RL. This simplifies the
analysis considerably.

Reference to Figure (CC) reveals that the BJT has a resistance (ro || RL) in series with the
emitter resistance re. Inspection of the circuit in (a) above shows that the input resistance at
the base, Rib, is
   
 
L
o
e
ib R
r
r
R ||
1 

 
From which we see that the emitter follower acts to raise the resistance level of RL (or RL ||
ro to be exact) by the factor (β + 1) and presents to the source the increased resistance. The
total input resistance of the follower is
ib
B
in R
R
R ||

From which we see that to realize the full effect
of the increased Rib, we have to choose as large
a value for the bias resistance RB as is practical.
Also, whenever possible, we should dispense
with RB altogether and connect the signal source
directly to the base.
…(3.67)
…(3.68)

(a) An equivalent circuit of the emitter follower
(b) The circuit in (a) after application of Thevenin theorem to the input circuit composed of
vsig, Rsig, and RB.

To find the overall voltage gain Gv, we first apply Thevenin theorem at the input side of the
circuit in Figure (a) above to simplify it to the form in Figure (b). From the latter circuit we
see that vo can be found by utilizing the voltage divider rule; thus,
 
L
o
e
B
sig
L
o
B
sig
B
v
R
r
r
R
R
R
r
R
R
R
G
||
(
)
1
(
)
||
(
)
||
)(
1
(








We observe that the voltage gain is less than unity; however, for RB >> Rsig and (β+1)[re + (ro
|| RL)] >> (Rsig || RB), it becomes very close to unity. Thus the voltage at the emitter (vo)
follows very closely the voltage at the input, which gives the circuit the name emitter
follower.
…(3.69)

Frequency Response of The Common-Emitter Amplifier
The Three Frequency Bands
The circuit of CE amplifier with coupling capacitors is given
below:
(a) A capacitively coupled common-emitter amplifier.
(b) The circuit prepared for small-signal analysis.

When the CE amplifier of the figure above was studied previously, it was assumed that the
coupling capacitors CC1 and CC2 and the bypass capacitor CE were acting as a perfect short
circuits at all the signal frequencies of interest. We also neglected the internal capacitances of
the BJT. That is Cπ and Cμ of the BJT high-frequency model were assumed to be sufficiently
small to act as open circuits at all the signal frequencies of interest. As a result, ignoring all the
capacitive effects, the gain expression derived in the previous sections were independent of
frequency. In reality, however, this situation only appears over a limited , though wide, band of
frequencies. This is illustrated in the figure below, which shows a sketch of the magnitude of
the overall gain , |Gv|, of the common-emitter amplifier versus frequency. We observe that the
gain is almost constant over a wide frequency band called the midband. The value of the
midband gain AM corresponds to the overall voltage gain Gv that we derived earlier namely,
𝐴𝑀 =
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐵||𝑟𝜋
𝑅𝐵||𝑟𝜋 + 𝑅𝑠𝑖𝑔
𝑔𝑚 𝑟𝑜| 𝑅𝐶 |𝑅𝐿 …(3.70)

Figure given above shows that the gain falls off at a signal frequencies below and above the
midband. The gain fall off in the low-frequency band is due to the fact that the coupling
capacitors have high impedances and they no longer behave as short circuits. On the other
hand, the gain falls off in the high-frequency band as result of the Cμ and Cπ, which though
very small, their impedances at sufficiently large frequencies decrease; thus they can no
longer be considered as open circuits.

The midband is obviously the useful frequency band of the amplifier. Usually, fL and fH are the
frequencies at which the gain drops by 3 dB below its value at the midband; that is, at fL and
fH, |gain| = 𝐴𝑀 / 2. The amplifier bandwidth or 3-dB bandwidth is defined as the difference
between the lower (fL) and the upper (fH) 3-dB frequencies.
𝐵𝑊 ≡ 𝑓𝐻 − 𝑓𝐿
A figure of merit for the amplifier is its gain-bandwidth product, defined as
𝐺𝐵 = 𝐴𝑀 BW
It will be shown at a later stage that in amplifier design, it is usually possible to trade off gain
for bandwidth.
…(3.71)
…(3.72)

The High-Frequency Response
To determine the gain, or the transfer function, of the amplifier of figure below, we replace
the BJT with the high frequency model as seen earlier in Unit II.

(a) Determining the high-frequency response of the CE amplifier : Equivalent circuit

The circuit of (a) simplified at both the input and the output side.

Equivalent circuit with Cμ replaced at the input side with the equivalent
capacitance Ceq

Sketch of the frequency-response plot, which is that of a low pass STC circuit.

Since Vo = Vce, equation above indicates that the gain from B’ to C is −𝑔𝑚𝑅𝐿
′
, the same value
as in the midband. The current Iμ can now be found from:
𝐼𝜇 = 𝑠𝐶𝜇 𝑉
𝜋 − 𝑉
𝑜
= s𝐶𝜇 𝑉
𝜋 − −𝑔𝑚𝑅𝐿
′
𝑉
𝜋 = s𝐶𝜇 1 + 𝑔𝑚𝑅𝐿
′
𝑉
𝜋
Now in the figure given above, the left-hand side of the circuit, at XX’, knows of the
existence of Cμ only through the current Iμ. Therefore, we can replace Cμ by an equivalent
capacitance Ceq between B’ and the ground as long as Ceq draws a current equal to Iμ. That is
𝑠𝐶𝑒𝑞𝑉
𝜋 = 𝐼𝜇 = 𝑠𝐶𝜇 1 + 𝑔𝑚𝑅𝐿
′
𝑉
𝜋
Which results in 𝐶𝑒𝑞 = 𝐶𝜇 1 + 𝑔𝑚𝑅𝐿
′
Thus we can express Vπ in terms of 𝑉𝑠𝑖𝑔
′
as 𝑉
𝜋 = 𝑉𝑠𝑖𝑔
′ 1
1 + 𝑠 𝜔𝑜
where 𝜔𝑜 = 1 𝐶𝑖𝑛𝑅𝑠𝑖𝑔
′
𝐶𝑖𝑛 = 𝐶𝜋 + 𝐶𝑒𝑞 = 𝐶𝜋 + 𝐶𝜇 1 + 𝑔𝑚𝑅𝐿
′
…(3.73)
…(3.74)
…(3.75)
…(3.76)
…(3.77)
…(3.78)

𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐵
𝑅𝐵 + 𝑅𝑠𝑖𝑔
𝑟𝜋𝑔𝑚𝑅𝐿
′
𝑟𝜋 + 𝑟𝑥 + 𝑅𝑠𝑖𝑔||𝑅𝐵
1
1 +
𝑠
𝜔𝑜
𝑉
𝑜
𝑉𝑠𝑖𝑔
=
𝐴𝑀
1 +
𝑠
𝜔𝑜
From which we deduce that the upper 3-dB frequency fH must be
𝑓𝐻 =
𝜔𝑜
2𝜋
=
1
2𝜋𝐶𝑖𝑛𝑅𝑠𝑖𝑔
′
Where AM is the midband gain
…(3.79)
…(3.80)
…(3.81)

Low Frequency Response
To show the low frequency gain (or transfer function) of the CE amplifier circuit, we show
the figure as (a) given below with the dc sources eliminated (current source I open circuited
and voltage source Vcc short circuited). We perform the small circuit analysis directly on this
circuit. We will ignore Cπ and Cμ since at low frequencies their impedance will be very high
and thus can be considered as open circuits. Also we will neglect ro . Finally, we also neglect
rx which is usually much smaller than rπ with which it appears in series.

Figure (a) above is to consider the effect of
the three capacitors CC1, CE, and CC2 one at
a time, considering the other two as a
perfect short-circuit.
Consider the Figure (b) above, shows that
CC2 and CE are replaced by short circuits.
The voltage Vπ at the base is of the
transistor can be written as
(d)
𝑉
𝑅𝐵||𝑟𝜋
𝑅𝐵||𝑟𝜋 + 𝑅𝑠𝑖𝑔 +
1
𝑠𝐶𝐶1
𝑉
𝑜 = −𝑔𝑚𝑉
𝜋 𝑅𝐶||𝑅𝐿
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐵||𝑟𝜋
𝑔𝑚 𝑅𝐶||𝑅𝐿
𝑠
𝑠 +
1
𝐶𝐶1 𝑅𝐵||𝑟𝜋 + 𝑅𝑠𝑖𝑔
…(3.82)
…(3.83)
…(3.84)

This factor is recognized as the transfer function of a single time constant (STC) network of
the high pass type with a -3 dB frequency 𝜔𝑃1 which is written as
𝜔𝑃1 =
1
𝐶𝐶1 𝑅𝐵||𝑟𝜋 + 𝑅𝑠𝑖𝑔
Next we consider the effect of CE. For this purpose we assume that CC1 and CC2 are acting as a
perfect short circuits and thus obtain the circuit in the Figure (c) above. Reflecting rπ and CE
into the base and utilizing Thevenin theorem we obtain the base current as
𝐼𝑏 = 𝑉𝑠𝑖𝑔
𝑅𝐵
1
𝑅𝐵||𝑅𝑠𝑖𝑔 + 𝛽 + 1 𝑟𝑒 +
1
𝑠𝐶𝐸
𝑉𝐵𝐵 = 𝑉𝑠𝑖𝑔
𝑅𝐵
𝑅𝐵𝐵 = 𝑅𝐵||𝑅𝑠𝑖𝑔 𝑉𝐵𝐵 = 𝑅𝐵𝐵𝐼𝑏 + (1 + 𝛽) 𝑟𝑒 +
1
𝑠𝐶𝐸
𝐼𝑏
…(3.85)
…(3.86)
…(3.87)

𝑉
𝑜 = −𝛽𝐼𝑏 𝑅𝐶||𝑅𝐿 = −
𝑅𝐵
𝛽 𝑅𝐶||𝑅𝐿
𝑅𝐵||𝑅𝑠𝑖𝑔 + 𝛽 + 1 𝑟𝑒 +
1
𝑠𝐶𝐸
𝑉𝑠𝑖𝑔
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐵
𝛽 𝑅𝐶||𝑅𝐿
𝑅𝐵||𝑅𝑠𝑖𝑔 + 𝛽 + 1 𝑟𝑒
𝑠
𝑠 + 1 𝐶𝐸 𝑟𝑒 +
𝑅𝐵||𝑅𝑠𝑖𝑔
𝛽 + 1
We observe that CE introduces the STC high-pass factor on the extreme right hand side. Thus
CE cause the gain to fall off at low frequencies, with the -3 dB frequency equal to the
frequency of the high-pass STC factor, that is
𝜔𝑃2 =
1
𝐶𝐸 𝑟𝑒 +
𝑅𝐵||𝑅𝑠𝑖𝑔
𝛽 + 1
…(3.88)
…(3.89)
…(3.90)

Finally, we consider the effect of CC2. The circuit with CC1 and CE assumed to be acting as
perfect short circuits is shown in the Figure (d) above, for which we can write
𝑉
𝑅𝐵||𝑟𝜋
𝑉
𝑜 = −𝑔𝑚𝑉
𝜋
𝑅𝐶
𝑅𝐶 +
1
𝑠𝐶𝐶2
+ 𝑅𝐿
𝑅𝐿
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐵||𝑟𝜋
𝑔𝑚 𝑅𝐶||𝑅𝐿
𝑠
𝑠 +
1
𝐶𝐶2 𝑅𝐶 + 𝑅𝐿
We observe that CC2 introduces the frequency-dependent factor which we recognize as the
transfer function of a high-pass STC network with a break frequency 𝜔𝑃3 given as
𝜔𝑃3 =
1
𝐶𝐶2 𝑅𝐶 + 𝑅𝐿
…(3.91)
…(3.92)
…(3.93)
…(3.94)

Now that we have determined the effects of each of CC1, CE, CC2 acting alone, the amplifier
low frequency gain can be expressed as
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −𝐴𝑀
𝑠
𝑠 + 𝜔𝑃1
𝑠
𝑠 + 𝜔𝑃2
𝑠
𝑠 + 𝜔𝑃3
From which we see that it acquires three break frequencies at fP1, fP2, fP3, all in the low
frequency band. If the three frequencies are widely separated, their effects will be distinct, as
indicated by the Figure below. The important point is that the -3 dB frequency fL is determined
by the highest of these break frequencies. This is usually the break frequency caused by the
bypass capacitor CE, simply because the resistance that it sees is usually quite small. Thus,
even if one uses a large value of CE, fP2 is usually the highest of the three break frequencies.
If fP1, fP2, and fP3 are close together, none of the three dominates, and to determine fL, we have
to evaluate 𝑉
𝑜 𝑉𝑠𝑖𝑔 in the equation given above. We can obtain a reasonably good estimate
for fL using the following formula.
…(3.95)

𝑓𝐿 ≡
1
2𝜋
1
𝐶𝐶1𝑅𝐶1
+
1
𝐶𝐸𝑅𝐸
+
1
𝐶𝐶2𝑅𝐶2
or 𝑓𝐿 = 𝑓𝑃1 + 𝑓𝑃2 + 𝑓𝑃3
Where RC1, RE, and RC2 are the resistances seen by CC1, CE, CC2, respectively, when Vsig is set to
zero and the other two capacitances are replaced with short circuits.
…(3.96)

Frequency Response of the Common Source Amplifier
Three Frequency Bands
When the circuit of Figure (a) below was studied earlier, it was assumed that the coupling
capacitors CC1 and CC2 and the bypass capacitor CS were acting as perfect short circuit at all
signal frequencies of interest. We also neglected the internal capacitances of the MOSFET,
that is Cgd and Cgs. We observe that the gain of the amplifier is almost constant over a wide
frequency band, called the midband. The value of the midband gain AM corresponds to the
overall voltage gain Gv namely,
𝐴𝑀 ≡
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐺
𝑅𝐺 + 𝑅𝑠𝑖𝑔
𝑔𝑚 𝑟𝑜| 𝑅𝐷 |𝑅𝐿
Figure (b) below shows that the gain falls off at signal frequencies below and above the midband. The
gain falloff in the low-frequency band is due to the fact that even though CC1, CC2, and CS are large
capacitors, as the signal frequency is reduced, their impedances increase, and they no longer behave as
short circuits. On the other hand, the gain falls off in the high-frequency band as a result of Cgs and
Cgd, which though very small, their impedances at high frequencies decrease and thus no longer be
considered as open circuits.
…(3.97)

The High-Frequency Response
To determine the gain, or transfer function of the amplifier given in Figure (a) above at high
frequencies, we replace the MOSFET with its high-frequency model. At these frequencies CC1,
CC2, and CS will behave as perfect short circuits. The result is the high frequency amplifier
equivalent circuit shown in Figure (a) below.

The equivalent circuit of Figure (a) above can be simplified by utilizing the Thevenin theorem
at the input side by combining the three parallel resistance at the output side. The resulting
simplified circuit is shown in Figure (b) below.

𝑅𝐿
′
= 𝑟𝑜| 𝑅𝐷 |𝑅𝐿 𝑎𝑛𝑑 𝑠𝑖𝑛𝑐𝑒 𝑉
𝑜 = 𝑉𝑑𝑠
𝐼𝑔𝑑 = 𝑠𝐶𝑔𝑑 𝑉
𝑔𝑠 − 𝑉
𝑜 = s𝐶𝑔𝑑 𝑉
𝑔𝑠 − −𝑔𝑚𝑅𝐿
′
𝑉
𝑔𝑠 = 𝑠𝐶𝑔𝑑 1 + 𝑔𝑚𝑅𝐿
′
𝑉
𝑔𝑠
𝑠𝐶𝑒𝑞𝑉
𝑔𝑠 = 𝑠𝐶𝑔𝑑 1 + 𝑔𝑚𝑅𝐿
′
𝑉
𝑔𝑠
𝐶𝑒𝑞 = 𝐶𝑔𝑑 1 + 𝑔𝑚𝑅𝐿
′
Vgs of the STC circuit can be written as
𝑉
𝑔𝑠 =
𝑅𝐺
𝑉𝑠𝑖𝑔
1
1 +
𝑠
𝜔𝑜
Where ωo is the corner frequency or the break frequency of the STC circuit
𝜔𝑜 = 1 𝐶𝑖𝑛𝑅𝑠𝑖𝑔
′
with 𝐶𝑖𝑛 = 𝐶𝑔𝑠 + 𝐶𝑒𝑞 = 𝐶𝑔𝑠 + 𝐶𝑔𝑑 1 + 𝑔𝑚𝑅𝐿
′
…(3.98)
…(3.99)
…(3.103)
…(3.101)
…(3.102)
…(3.100)

𝑅𝑠𝑖𝑔
′
= 𝑅𝑠𝑖𝑔||𝑅𝐺 Combining the above equations we get
𝑉
𝑜
𝑉𝑠𝑖𝑔
= −
𝑅𝐺
𝑔𝑚𝑅𝐿
′
1
1 +
𝑠
𝜔𝑜
…(3.104)

𝑉
𝑜
𝑉𝑠𝑖𝑔
=
𝐴𝑀
1 +
𝑠
𝜔𝐻
Where AM is the midband gain and ωH is the upper 3-dB frequency
𝐴𝑀 = −
𝑅𝐺
𝑔𝑚𝑅𝐿
′
𝜔𝐻 = 𝜔𝑜 =
1
𝐶𝑖𝑛𝑅𝑠𝑖𝑔
′
𝑓𝐻 =
𝜔𝐻
2𝜋
=
1
2𝜋𝐶𝑖𝑛𝑅𝑠𝑖𝑔
′

Power Amplifiers
A power amplifier is simply an amplifier with high power output stage. Output stages are
classified according to the collector current waveform that results when an input signal is
applied. Figures given below illustrates the classification for the case of a sinusoidal input
signal.
Class A: A class A amplifier is one in which the operating point and input signal are such
that the current in the output circuit(in the collector, or drain electrode) flows at all times. A
class A operates essentially over a linear portion of its characteristics.
Class B: A class B amplifier is one in which the operating point is at an extreme end of its
characteristics, so that the quiescent power is very small. Hence, either the quiescent current
or quiescent voltage is approximately zero.
Class AB: A class AB amplifier is one operating between the two extremes defined for class
A and class B. Hence the output signal is zero for part but less than one half of an input
sinusoidal signal.
Class C: A class C amplifier is one in which the operating point is chosen so that the output
current (or voltage) is zero for more than one half of an input sinusoidal signal cycle.

Collector Current waveforms for
transistors operating in:
(a)Class A
(b)Class B
(c)Class AB
(d)Class C
Amplifier Stages

Class A Output Stage
Transfer Characteristic
Figure given below shows an emitter follower Q1 biased with a current I supplied by transistor
Q2. Since the emitter current iE1 = I + iL, the bias current I must be greater that the largest
negative load current; otherwise, Q1 cuts off and class A operation will no longer be
maintained.

The transfer characteristic of the emitter follower of Figure above is described by
𝑣𝑜 = 𝑣𝐼 − 𝑣𝐵𝐸1
Where vBE1 depends on the emitter current iE1 and thus on the load current iL. If
we neglect the relatively small changes in vBE1, the linear transfer curve shown in
Figure above results. As indicated, the positive limit of the linear region is
determined by the saturation of Q1; thus
𝑣𝑂𝑚𝑎𝑥 = 𝑉𝐶𝐶 − 𝑉𝐶𝐸1𝑠𝑎𝑡
In the negative direction, depending on the values of I and RL, the limit of the linear
region is determined either by Q1 turning off or by Q2 saturation.
𝑣𝑂𝑚𝑖𝑛 = −𝐼𝑅𝐿
𝑣𝑂𝑚𝑖𝑛 = −𝑉𝐶𝐶 + 𝑉𝐶𝐸2𝑠𝑎𝑡
𝐼 ≥
−𝑉𝐶𝐶 + 𝑉𝐶𝐸2𝑠𝑎𝑡
𝑅𝐿
The absolute lowest output voltage is that
given by this equation and is achieved
provided the bias current I is greater than
the magnitude of the corresponding load
current
…(3.105)
…(3.106)

Power Dissipation
Maximum signal waveforms
in class A output stage of
Figure of the emitter follower
above under the condition that
𝐼 = 𝑉𝐶𝐶 𝑅𝐿, or, equivalently,
𝑅𝐿 = 𝑉𝐶𝐶 𝐼

Figure (d) above indicates that the maximum instantaneous power dissipation in Q1 is VCCI.
This is equal to the quiescent power dissipation in Q1. Thus the emitter-follower transistor
dissipates the largest amount of power when vO = 0. Since this condition (no input signal) can
easily prevail for prolonged periods of time, transistor Q1 must be able to withstand a
continuous power dissipation of VCCI.
The power dissipation in Q1 depends on the value of RL. Consider RL = ∞. In this case, iC1 = I
is constant and the instantaneous power dissipation in Q1 will depend on the instantaneous
value of vO. The maximum power dissipation will occur when vO = -VCC, for in this case vCE1 is
a maximum of 2VCC and pD1 = 2VCCI. With an open circuit load the average power dissipation
in Q1 is VCCI.
Consider the case when RL = 0. In the event of the output short circuit, a positive input voltage
would theoretically result in an infinite load current. In practice a very large current may flow
through Q1, and if the short circuit condition persists, the resulting large power dissipation in
Q1 can raise its junction temperature beyond the specified maximum, causing Q1 to burn up. To
guard against such a situation, output stages are usually equipped with short-circuit protection.

Power Conversion Efficiency
η ≡
𝐿𝑜𝑎𝑑 𝑃𝑜𝑤𝑒𝑟 (𝑃𝐿)
𝑆𝑢𝑝𝑝𝑙𝑦 𝑃𝑜𝑤𝑒𝑟 (𝑃𝑆)
𝑃𝐿 =
𝑉
𝑜 2
2
𝑅𝐿
=
1
2
𝑉
𝑜
2
𝑅𝐿
Since the current through Q2 is constant (I), the power drawn from the negative supply is
VCCI. The average current in Q1 is equal to I, and thus the average power drawn from the
positive supply is VCCI. Thus the total average supply power is
𝑃𝑆 = 2𝑉𝐶𝐶𝐼
η =
1
4
𝑉
𝑜
2
𝐼𝑅𝐿𝑉𝐶𝐶
=
1
4
𝑉
𝑜
𝐼𝑅𝐿
𝑉
𝑜
𝑉𝐶𝐶
Since 𝑉
𝑜 ≤ 𝑉𝐶𝐶 and 𝑉
𝑜 ≤ 𝐼𝑅𝐿 , maximum efficiency is
obtained when 𝑉
𝑜 = 𝑉𝐶𝐶 = 𝐼𝑅𝐿 . The maximum
efficiency attainable is 25%. Because this figure is
quite low, the class A output stage is rarely used in
high-power amplifications (>1 Watt). The efficiency
achieved is usually in the 10% and 20% range.
…(3.107)
…(3.108)

Class B Output Stage
Figure given below shows a Class B output stage. It consists of a complimentary pair of transistors (an npn or
pnp) connected in such a way that both cannot conduct simultaneously.
Circuit Operation
When the voltage vI is zero, both the transistors are cut off and the
output voltage vO is zero. As vI goes positive and exceeds about
0.5 V, QN conducts and operates as an emitter follower. In this
case vO follows vI (i.e. vO = vI – vBEN) and QN supplies the output
load current. Meanwhile, the emitter-base junction of QP will be
reversed biased by the VBE of QN, which is approximately 0.7 V.
Thus QP will be cut off.
If the input goes negative by more than about 0.5 V, QP turns on
and acts as an emitter follower. Again vO follows vI (i.e. vO = vI +
vEBP), but in this case QP supplies the load current and QN will be
cut off.
We conclude that the transistors in the Class B stage of this Figure
are biased at zero current and conduct only when the input signal
is present. The circuit operates in a push-pull fashion.

Transfer Characteristic
A sketch of the transfer characteristic of the Class B stage is shown in the Figure below. There exists a
range of vI centered around zero where both transistors are cut off and vO is zero. The dead band results
in the crossover distortion illustrated in the second Figure below for the case of an input sine wave.
Crossover distortion in audio power amplifiers gives rise to unpleasant sounds.

Power Conversion Efficiency
To calculate the power consumption efficiency, η , of the Class B stage, we neglect the crossover
distortion and consider the case of an output sinusoidal of the peak amplitude 𝑉
𝑜. The average load
power will be
𝑃𝐿 =
1
2
𝑉
𝑜
2
𝑅𝐿
The current drawn from each supply will consist of half-sine waves of peak
amplitude 𝑉
𝑜 𝑅𝐿 . Thus the average current drawn from each of the two power
supplies will be 𝑉
𝑜 π𝑅𝐿 . It follows that the average power drawn from each of
the two power supplies will be same,
𝑃𝑆+ = 𝑃𝑆− =
1
𝜋
𝑉
𝑜
𝑅𝐿
𝑉𝐶𝐶 And the total supply power will be 𝑃𝑆 =
2
𝜋
𝑉
𝑜
𝑅𝐿
𝑉𝐶𝐶
Thus the efficiency will be given by
η=
1
2
𝑉𝑜
2
𝑅𝐿
2
𝜋
𝑉𝑜
𝑅𝐿
𝑉𝐶𝐶
=
𝜋
4
𝑉𝑜
𝑉𝐶𝐶
η𝑚𝑎𝑥 =
𝜋
4
= 78.5 %
Maximum efficiency is obtained when
𝑉
𝑜 is maximum. This is limited by the saturation of QN and QP to VCC –VCEsat ≈ VCC.
Thus
𝑃𝐿𝑚𝑎𝑥 =
1
2
𝑉𝐶𝐶
2
𝑅𝐿

Power Dissipation
When an input signal is applied, the average power dissipated in the Class B stage is given by
𝑃𝐷 = 𝑃𝑆 − 𝑃𝐿 =
2
𝜋
𝑉
𝑜
𝑅𝐿
𝑉𝐶𝐶 −
1
2
𝑉
𝑜
2
𝑅𝐿
From the symmetry we see that half of PD is dissipated in QN and the other half in QP. Thus QN
and QP must me capable of safely dissipating
1
2
𝑃𝐷 Watts. In the worst case scenario we
differentiate the above equation with respect to 𝑉
𝑜 and equating the derivative to zero gives the
value of 𝑉
𝑜 that results in maximum average power dissipation as
𝑉
𝑜 𝑃𝐷𝑚𝑎𝑥 =
2
𝜋
𝑉𝐶𝐶
Substituting this value in the above equation we get
𝑃𝐷𝑚𝑎𝑥 =
2𝑉𝐶𝐶
2
𝜋2𝑅𝐿
𝑃𝐷𝑁𝑚𝑎𝑥 = 𝑃𝐷𝑃𝑚𝑎𝑥 =
𝑉𝐶𝐶
2
𝜋2𝑅𝐿
…(3.109)
…(3.110)
…(3.111)

Power Dissipation of the Class B stage versus amplitude of the output sinusoidal

Class AB Output Stage
Crossover distortion can be virtually
eliminated by biasing the complimentary
output transistors at a small nonzero
current. The result is a Class AB output
stage shown in this Figure. A bias voltage
VBB is applied between bases of QN and
QP. For vI=0, and vO=0, and a voltage
VBB/2 appears across the base-emitter
junction of each of QN and QP. Assuming
matched devices,
𝑖𝑁 = 𝑖𝑃 = 𝐼𝑄 = 𝐼𝑆𝑒𝑉𝐵𝐵 2𝑉𝑇
The value of VBB is selected to yield the
required quiescent current IQ
…(3.112)

Circuit Operation
When vI goes positive by a certain amount, the voltage at the base of QN increases by the same amount and the
output becomes positive at an almost equal value,
𝑣𝑂 = 𝑣𝐼 +
𝑉𝐵𝐵
2
− 𝑣𝐵𝐸𝑁
The positive vO causes a current iL to flow through RL, and thus iN must increase; that is,
𝑖𝑁 = 𝑖𝑃 + 𝑖𝐿
The increase in iN will be accompanied by a corresponding increase in vBEN (above the quiescent value of VBB/2).
However, since the voltage between the two bases remains constant at VBB, the increase in vBEN will result in an
equal decrease in vBEP and hence iP. The relationship between iN and iP can be derived as follows:
𝑣𝐵𝐸𝑁 + 𝑣𝐵𝐸𝑃 = 𝑉𝐵𝐵 → 𝑉𝑇𝑙𝑛
𝑖𝑁
𝐼𝑆
+ 𝑉𝑇𝑙𝑛
𝑖𝑃
𝐼𝑆
= 2𝑉𝑇𝑙𝑛
𝐼𝑄
𝐼𝑆
→ 𝑖𝑁𝑖𝑃 = 𝐼𝑄
2
Thus, as iN increases, iP decreases by the same ratio while the product remains constant. Combining above
equations we get a quadratic equation and which yields iN for a given iL as a solution to this equation
𝑖𝑁
2
− 𝑖𝐿𝑖𝑁 − 𝐼𝑄
2
= 0
…(3.113)
…(3.114)
…(3.115)
…(3.116)

Transfer Characteristic of the Class AB stage in the Figure above

From the above equations we can see that for positive output voltages, the load current is
supplied by QN, which acts as the output emitter follower. Meanwhile QP will conduct a current
which decreases as vO increase; for large vO the current in QP can be ignored altogether.
For negative input voltages the opposite occurs: The load current will be supplied by QP, which
acts as the output emitter follower, while QN conducts a current that gets smaller as vI becomes
more negative.
We conclude that the Class AB stage operates in much same manner as the Class B circuit, with
one important exception: For small vI, both transistors conduct, and as vI is increased or
decreased, one of the two transistors takes over the operation. Since the transition is a smooth
one, crossover distortion will be almost totally eliminated.
The power relationship in the Class AB stage are almost identical to those derived for the Class
B circuit. The only difference is that under quiescent conditions the class AB circuit dissipates a
power of VCCIQ per transistor. Since IQ is usually much smaller than the peak load current, the
quiescent power dissipation is usually small.

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