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lOEC/TE762
Dec.20l4lJan,2015
ot.. Ars d FIlEfu questiohs, kldnhg
al tust lwo qtestkks lo t.a.h pan.
Seventh Semester 8.tr. Degree Ex.mination,
Real Tirne Systems
5
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a. Clasit! RTS bosed on iine ron$Lainls.
b. Eplxi. rhe tullo*ing
il Clock brsed lasks ,i)Erentbased lasks
c. DifeEniars real time s)islens dd non Eal time slstcms.
d. Erflrin dre lollo*ingpngmm rtpes: il Mulralaskin!: ii)RealUne.
Dxplai scquence conrrollora single chemicalr.adorvd$el. sith near skcrh
uirh Nxl diasraD errlain loop ronrol and give rho adynnuges ol DDC
with Deft sketch, explar hi.Erchicrl synem.
NithncaldiaeraDexphinprionly nrucure' O?NhrkO
Erplain $hcdrling srdlegies (0s rLrkt
Give the basic lundiors ol lask darascmc.r Exflanr task stal€s Biih a qlical tlsk
diagran (oB rsrk,
a Eplxi. Yourdon Dre mdology (0slr,ikt
h Dr.$ Md cplain conte*diaamm lirr drling dlen nr case oltrard atrd Mellormedod.
3.  irh adiaElnr-cxpldn dlgilali.pul inrcdace
b. lxplain rirh a near diagan,nalog ouqrul slnen.
c Dra snrsE chip conpulerand explain.
d. Explxinconnrunicalions0ndlhcwrlsorcharacterizmgerillconnnunlclrion
r Eplain rhe tullowinsr i)se.!nrr. ii) Reddabililv, iii)Ponxblh]
b. Dxplain cxcepdon hardliirs.
i. wid a diaga'n, explain t6skchaining and swapping.
b. Dn* fie ngurc lor: ilnon prfrt,oned. ii) oanilioned merory.
d. {hrrrsLirenes:r ErFlai.
a. Lrpldnsoli$aEdesignincascolprelifrinarydesignolRTSSwirhdiagmn
b rilotr- Jre.o
'
roieso.ndo-.l'grud,ppo"h
c fxthinmuli-tulkingapnroach
Dillerdnriale ben.en $'id & l.llorand ll!rlcy & Pirbhai tucrhodologics.
Lrplaii, thc archirccrur toodel in ce ofHarleyand Pnbhni ndthod
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diasnm. Also rvite the liming
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an exanpl.. what.re rhe hde
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SemesterB.E. DesreeExamiration, De..2014/.Ian.2015
2
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Embedded System Design
Note: A,s4zr Fll/E la q
"srio's,
rele.ti,g
alleart TwO .laation! lro each Dan.
PAR'I' A
ni) Wdchdoglirnel (06 t,rrt
w a block diagra,n, explain biely rhe laious componcnh in a microprccesor based
eDrbedded slslcin. (0? NbrD
Briefl) descnbe rhe najor elenrenls olthe embedded sy$ctu developnent lilb cl.le.
(07 Nrsrk)
Explain diEd and rcsist$ rdirccl.ddre$ing ftodes rvith
dlaCram lorsenal wrile operarion si& an 3 bil regiler.
i) BisEndianMd lifrle lndian lonn s
ii) ltlscandclscregire^
iii) T'ucalion d iorndinAoma.
Erilain the direct mapplne cache hmagement slrdegy Nirh
o1lbetrveenvnG throush md delayed u e auonlhm?
Exrlain the iNemal dia8rafr oISRAM aid wile dninsdilgnrn
Wrno the inside lnd ouaidedhgmins lorDRAM along *nh Erd
Elplain Asocirtive mappi.g cichc i'npletuentation.
Write ihe llo* diagmms lbi wdoii,ll and V lifecycle models and brieflI explain waterlall
*cPs. (06M,r9
Wile a harduare architecruE dd daio and counter loy diagrar ola c.unter srsrcn and
cxplah briefly foR
'liagmm (03 Nrert ,
Erplatu the chancrerizing and ddnrii,ing the Equiiemenh oln system, wil]] rcspc.r ro a
dlgnal counrer 06 M!rk,
PARI B
Discuss l8skcontolblo.k 'lEnrion sonr ollhe mjor coinpo.ents oflask
i) Proarain andprcces
il) Pro.e$srandrhreadr
iii) Li$l weighted and healy wclghled rhreads
Explah the dillarenr tuncrions ofembedded opcLaling.
b. Descnbe vintral model a.d high lelelnodel lorOS architectures.
c wite lne algonfin lora simple OS kenel, usine C lansuage nolation
tasks usina TCBk only. The 3 tasks use a comon dila bufEr for
Discuss loresou. backgoun'i sysren. Mention
Descnb. the mlhods by Nhi.h wc cm perfom
lime coding dalysis ofan embedded lppticalior.
10EC7l
rhe difeEnce be een lbregrornd dd
a. Write the Amdahfs limitarion for perlbma..e improvenent/oprimization. Consid.r a
system wtu lne loilowins cnaEcleristics. Thc iasr 1o be analysed and nlproled.uftnrly
execuies in I00 timeunits, and the goaln b reduce exe.ution line to 50 unirs. ihe alsornnm
10 be imprcved uses 40 rinre unils. Detemile de unknom peanreler and wnre Ge
c, wnte'C tuncrions io delemi.e Ihe sun orrhe elemenls in an amr aod dallze it iincby
line ror ih inne conpGdy. (06 M.*,
(06lurI,
a tine coding analysis olan enrbedded a
DiscBs fie advulaaes and dradvdagcs
(03 M.rk,
a. Doscribe bedory loading wi1n equado., ligue md an example.
b. wrile shonnotes on lhs lollowi.g '
i) Tricks ofthe nade
ii) Perrdft dce oplinizalion.
l0Ec73
Seventh Semester B.E. D€qree Examination!
Power Electronics
Dec.20l4lJrn..2015
lor.t AhlMt an! FMJi qr.stiohst szl..rit*
anea:t TwO 4uestioi! ftotu ea.h Dart.
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PART - A
d McntionanylbNpropeftiesofasuperpowerdeviceshouldposses- (0?usrk,
b. wh0t isa convefter? Hor' ,re a.r'er conveneB cla$,fied? Explainbiien) (mn,rk,
c. l'lention sonie ituporraDi advlrtages and disaduDtages olp (0a ]r!rt,
d whlt arc rhe pedpheral e flf cts oapowerelecnoDicsconvcneN a.dhowrhey are overcomel
(06II!rl,
, The collector clanrping circuir of liig.Q.lG) has thc lollowjne paramctNr vuB = l4v.
Rtr = lO. P = 15, vuF = 0.7V, VD: = 0.9V, Vr,:2 LV. P:2O. V.r = 120V, Find
n Co lle r tor curen.vithou r clampnrsi ii) Collearor emittcrclampi.g loltaeci ili) Colle or
curent Nnh clampinr (0s lr,rl,
Fig.Q2(a)
b. Dra the $rilching nrodel ofMoSFET a.d erplai. s switching
c. Whxr is an IGBT? Compare IGBT $ith B.,T lnd MOSFET.
d. why isolaljon h rc.ded?Explain the t*omethodsofholarion
 ith a neat figurc oaplai. rhe dynamic rum-on and tum offcharacteriti. ora th)nstor
(03 irl! ,
Bieflycxplain drdt and drdiprotccrionolSCR (06m!.k,
Design a UJT relaxation oscillator lor triescrnrg an SCR. sith UJT havi4 lhe tbllo$ine
p,r,heter rt = 0 72. h = 60f A.  = 4mAj v! = 2.5v, vBB = 15v, RBB = 5KO, leakage
cuneDl with enitter open N lnrA. Also calculate ninimtrn rnd maxnnum valuc of RC
variablc rcsisrance). (o6Nr*k,
w irh a cncuit diagran a.d $avclorns explain the workingorasrgle phase senn.onr.lled
rcctifier. Derivc an cxprc$ion lor rhe aknge voltage acrcss rhe R-L load. (03rvlrrk,
Forasinglethae tullycontrolled bridse rectifier Bith hig|ly inducrilc load and coDtnruous
curcnt..btain avcrae. )oad lolrage and cure il rhe load reshtance k l0O and firing anglc
is .15". and is fed fion 230v. 50112 supply Dmx the load volrage waleaorm and supply
curcnt Faveiirrm. (06 Mark,
Lhat is a dual.o.veter? Explain nsopera.onurrh a neat circu dirgmm. (06 Nt{rk,
'':
t0EC73
PART' B
Statcthe.o.dnionsrobesaxsfiednrrpmpertum-ofofscR (0:rhrk,
with rhe heh orcituit diasranr aod wareform cxplain rhs operurionofselfcommurarion
rn rhe hg.Q.5(c) rhe source vortage v, = l00v a.d rhe .uren.t.",gt n,
",,a
l-1"r1'i!?
The tu6 ofl tlme ofbofi rhe SCRS n 4otrsec. Find the lalue ofcapa.ndr fo.succo$ful
commuration andhencc sho rhd cncuil tunoiltine is 0.693 RC. (03 ]hrrtt
Iie Q st)
cncuit shown in FigQs(d) the balt€ry lohdgd $ l00V
and thynstor tum otl titue s 4oBsec. Asume 5O9l rolerancc
ofrhe commutniion ci(un. (o{nrrkn
In tu auxiliary conrmutalion
Maxinun load curent is 40A
on nm.ffiime Find ! ,nd a
a. Disringnish beiqeen o. ofconm!a.d nhasecontrclofAColrlge coDnolter. (01M$r,
b. lxplain the opraion otsingle plase bidiiectioDal AC louage conrollcr lor nrductive bad
t h the help ofcncuit diaeEmand $avelbms.
c An AC lolragc controlE nas a resistiYe load oI R = too, and RVS mput lolrase is
v = 120v. 50Hz The thrrnror switch n on for n = 2t cycles lnd oJI fom:75 cvctes
Findr i) rDs ouqur ioltagei ii) Input porer factor iii) Ale.age and RUS dlrisror cuncnr
and heDce derive the above expre$ions for VmandtF. (lontrrk,
a. Explain the working princille olstep donn chopper a.d derive expesion lnr i) Arera[c
outpnt loltage; ,i) Output po'{ rn) Efcctive nrpur rcsisrahce tu tehb ofchopper dnry
b wnnthe helpof a cncun diasraD.explanrfouquadrantr$e! ohoppcn. Osrrrrk,
c. A step up choppcr has i.pnt lollage or220v and output vohagc ol660v. lfdre non
conducting heofthe tbrntor is loo|rsec. compurc rhe pulse widrh olth.ourpur!.lta!e lt
rhcpuhewidth is halved forconsta ncqucn.y operatio n, furd ney ourtul loltage
04MrdO
rixplaln a si.gle phase rull bidge inveiler nnh relela cnclir dirganr and Nalcfom!
A$udeR I load. (0r jrlrkt
with the helpolcncun diasraD and Nave tnrms cxplain rhe opeBtion oftransisrorized CSI
(.urenr source i.vdre, ftar ae the dva.ta8es anddnadvamagcs oICSI?
c. The inglephase halfbridEe nrlerrcr bas thcDC input ol48v Tne bad resistan.e n 4 31)
Determi.c: l) RMs lalue oa ihe ourFur voh4ei ii) RMS laluc ol rhc lrnnamentat
cornponertri ii)ToL.lha.montr d.r,'ri r
'.
ri!.Q.5(d)
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Sevenah Semester B,E. Degree
Optical Fiber
' .16 $'-
Examination, Dec.201:l/Jan.201s
Coftmunication
?
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3:
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a with near sketchcs ol Rl protle aid *ave propagarion i. oprical
cotuparc diileient twes ortbe6l
b. wil r € .NeLJhe. cpa1 F.t-r-p'J. .1oor'".i,-.dEe.
lpl.n. 4, Dp'o,r.. i{ '
rr
5
Note. A"swer FM lull qrcsliohs, set .line
att.ast Two qaestions fron each Dart.
Explain different typcsofafienulhon inopticalfib(. (06 Nr.rk,
Cla$ily and cxplain.hmtutE d[perion wirhin a si.gle mode fiber. (0srrrrk,
Consider a l0 kn long
"rultirode
in whicb nr = 1.,183 and d = o 0l Calcuhrc nr a.dpuhe
bruadning aner krclling l0 km (06 N{,rk,
a Exphin $irh schemarican LED whicbis hlghly dneciionaland skei.hrhe
b. Comparc op ed ting pam mercrs olc", S, ard IncdAsofPlN and APD
c. with ne skerch. explain &$D srucure rnd rhe elcctrical tields
b. Explain expanded be,h fiberoptic courecror.
c. Lnr selcral po$ible leDsing s.hcme xrd e{plai. bricfly non nMsing lensing schene
(07IIrrkt
PART -B
a. Dra* a signalpath lhtuugh a dignal li.k snh retcvant conponenh and oprtcaL/elcoriical
a. Eaplain dilleEnr qpes offiber spli.ing nElhod used loroprical libeE. Explain
savefoims at ersy saae (06
'rrrktwhdt aF the noisc so!(e anddntudances thatarisc inoldcalpulse derectior mechanismt,
Erphi', drcm in dcrail, {06 ivre,
DBw and capla,n eye pattemerd mark rhc tundatunral mea$yclne.r Faranere. (0sNrr.k,
a. what is nse rime budecr? Expla its sisninca.ce Denve an exprcssion for rhe sy cm risc
'iroebJdo". en,o r"L11r.r I'b ldre(e.e r.c in"
b. laplanr subcanier multipleai.g. rvith neat block diasram t0srerkt
c Denre an expressiotr tbr d1e CNR oaan analog con'nuricanon sFtem urdcr limiring
co.dilionofnote sources involved. (0? lrl,
i i,Y#I'HIT#ii],.trff Dc q'ioB r*ec or@dc!, anp,ine^
c. lxphrn d,ehctric rhD 6t; fi,teraDd tusapplicatioN
t0ECnE72
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'7d,. , ] nh kor eGrgy hvet diasEd, erDlain EDFA / r. wflteaioEoo.
L Baic a6rm:r
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a - STS N -SONET md
, ,sTM-N SD}I fam.
iD Hipsp.ed risht w,r liDks.
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SeveDth Semester B.E. Degree Examinatior, Dec.20r.r/Jan.2015
Computer Communication Networks
Nore. Ats||o a,! FIVE full qwslions, selednta
.n.ast TwO qkstions Jiott each pan.
PART A
a D,scu$ rhe TCP,IP Dodel wnh EncrioDahies of eaclr la_ver. Corider sourca deln.anon
ard nrcr cdirte nodes tnrdiscussion. (10)r{rk,
b. ExDhnr the diflcrcntscniccsprorldcd by re lep ho.c ncisorks. tor!*k,
. Des.nbe tuu lerclsoladdrc$in-q used in intemct (TCPilP) withexanrplcs. (06!rkt
'|
z;
1-
i.]
'.4
1a
.
whar is HDLC? Explai. diifeE.r name lbmts $ith controlfield used byHDLC
110:rr3rk9
A system uses eop-and{van ARQ froto.ol lfea.h tx.ket carEs 2000b s ofdata ho{
long does it take to scnd I nnllion bits of dara rf tbe speed is 2 t lor Drsecl JsDore
fiansmission. aitiDC 0nd proccsing dclars. wc 0sume .o dala or co.hl nam. n los or
danra-qed Repeat aor ga back nwiin wiMow) ste = 7 (i0lrrkt
whal is cbainelizallon in dre context ofnrultiple acces? what are v lois channelizarion
tedDiqresl Extlain CDMAtcch.iquc OoM$ks)
Tso sirti.ns A a.d C a.e connectdd to a $ared channel with data raie to4bps. Thc
distance betrveen A and C is 2s()()n and the proposarion speed is 2 : lor ns. Starron
A stans s.ndinC a bng naEe at rime r = 0i sarion C rMs sending a lone filme at tinre
rr = lUs.c Tbe size ofdre lia.r is long e.ough to guaniree rhe detedi.n ol.ollisionby
bothstations.Ftud i) TIc timc w[cn station C heas thc collh]oi (tr)i ii)-limerhenstation
A hcas dre collhion t1): iii) The trtrmber ol6its A bas senr betnE det.ctinE the colhrof:
PART.B
a. tsriefly cxplain ihe nfte cnierla sotat3.spare.i
b. Erphnr thc nilbwing connc.rin! dcli.cs i)
i!) Router; v)GftcwaI
bridge wnhexreple (r0[I*[t
Passivc hub: ii) Rcticarfr iii) tsridsc:
00 Nturl)
iv) Thentrnberolb sChas sedt beturedetechg thec.llnDn
a Ertl,in rhc MAC nam. formatoll!EE802.3 Write 0 note on name Ien:th.
b. ErphinthefeaturesofvACsublalcrandphtsi.allayerofCieabitEthe.r.t.
a. Uhrt is NA-Il laphnr hos addres rralsl.rion is donc in NAT. (0qllirl6)
b. ![y lPv4 to lPv6 tansitio. is iequncd] what are various te.h.iques nsed i. tansllionl
Explain !hem. (ot rt,rln
c Bnn!duianyld,fere.cesbeNeenlPV4&dlP!6addressingschenes Or^t,rkr)
l0Ec/Tn7l
':L
,u4,
Fie.Q.?&).
a. Explair distece veclor rcrting with an oxample.
b. With a @t loq chafi explain Dijksta algorithn ftr the ret*ork shoM in
Assune 'A' as rcot node. Mention the rculilg lable for Dot A. Refer Fie.Q.7(bl.
o.cv
"?.,
,,,a,
Fis.Q.7(b)
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9
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is TCP better rhan LrDP? Explai, sivics olferEd !y TCP.
h Name SnacE? HYd:ir n .la(sined'l Wnat
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Seventh Semester
DSP
B.E. Degree Examination, Dec.20l4lJan.20ls
Algorithms & Architecture
otet Aas||d l:IvE ful questioas, setedihg
at leasl TWO qrcslio s lro,t oath pan
. ExplainadigitalsignalprocessinesysremN h the help ola block diasrer. (07Nlrrk,
b. Lin the @joi unique architeclural lealrcs implemcntcd ina.y prosanbable DSP dcvi.es
(01Nlrr$
Derire lhe relationship between DrT and lrcqDency response abd also deline liequency
resolutiotr and signal rec. lengd {06 M,rk,
An FF-I is employed rir derernring the liequenq conDonents ofa randon signal lt is
.equncd ihar lh. rssolurion oflFT to be <=5 Hz. rir a slgnal wnh i,," = 1.25 kHz.
DeErnine i) Samplirg intc al.Ts.
ii) rFT lcngrh (N) as a po*erol2.
ii)Minimdtu sig.alEcord length. @1M!rk,
r Dra$thenructureola,l,4Braunmnltiplicrabdahoexplainitsopenrion. (0Brkrkt
b F,rplanl the ponner updarins aLsonrhm for crcular addre$ing node (0sMrrk,
c. Compute thc s.quence iD rvhich rhe input dara should be ordered irr a 16 point DIT r_FT
!si.8 Br revered addr.$i.g mode. Otiu.rr,
Describe thc lolloN e units ofTMsi2oc54xx pro.e$o. i) tsaml sh,ftc. ii) C.Drml
DroccssiDgunit (03 ]larr,
what is nleant by addresine flodel, Eaplain the absolltc. accunrulator. dtect and nrdn€cr
addressing nrodes ofTMs3zocs4xx DSP proce$or. (l2tr3rkt
Dcscibe thc opcration oltne followins instrucrions:
il 4Ac 'AI{3-.
+AIl4+. ts, A
]D MAS lAR].. *AR+. B.A
!ASI=-B
wha. n drc sigrific.uce of Q {o rxrion in DSP?
Rcpresent e Bch of the folLowingnutube^ in desned Q-notarlon tbmat:
iii) tsDAFh iiQ,lndQ j nuNber.
l!) 0.160121as Qr. number
v) 4.100h Rs Qr nuDrbf
lxpl.in $nh rhe help ol block diagrrD and oarheMticat equalions
dccim.rio. tiltcr or TMS320C54xx processor
lxplain thc had$ard ri'nerofTUS320C5]XX DSP siih logical block dragram.
Fp.. r rp.p!l'eo|e1 ono lVs.o_iatrolc.--.
a. What minimum size FFT nust be led.o coipute 50(]poinls DFrt W[ar musr
r0EC751
lhe enples before the choen FFI is applied?
b. Dqiw tne optimum scaling frctor for tbe DIT FFT bure.fly
c wrre ar assmbly ldn"irge pograr ro|mpl.ren-Dg
i) Bit Evmed addre$ eeiemrioi
ii) Spectrum ofthe transformcd dola.
W[at is an intempt? With a nea! flow cbart cxplain handlins of intcmpr by
TMs32oc54xxprccesso. o0lvrkr)
How does DMA help in incEasing lhe speed ofa DSP prccesor and alro explain regnrer
sub addrssing tccnnique for conigui.g DMA. (t0 Mlrks)
a wilh 6eat block diag.ln explain the DSP b6sed biorelcmeny receiver.
b. With neat block diagram explain rne CODEC inrdface cncuir.
tollosine on TMSl.20C54xX

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7th Semester (December; January-2014 and 2015) Electronics and Communication Engineering Question Papers

  • 1. f g- rne, lOEC/TE762 Dec.20l4lJan,2015 ot.. Ars d FIlEfu questiohs, kldnhg al tust lwo qtestkks lo t.a.h pan. Seventh Semester 8.tr. Degree Ex.mination, Real Tirne Systems 5 a ig 2i .Z 2; '.a " !ABf=-A a. Clasit! RTS bosed on iine ron$Lainls. b. Eplxi. rhe tullo*ing il Clock brsed lasks ,i)Erentbased lasks c. DifeEniars real time s)islens dd non Eal time slstcms. d. Erflrin dre lollo*ingpngmm rtpes: il Mulralaskin!: ii)RealUne. Dxplai scquence conrrollora single chemicalr.adorvd$el. sith near skcrh uirh Nxl diasraD errlain loop ronrol and give rho adynnuges ol DDC with Deft sketch, explar hi.Erchicrl synem. NithncaldiaeraDexphinprionly nrucure' O?NhrkO Erplain $hcdrling srdlegies (0s rLrkt Give the basic lundiors ol lask darascmc.r Exflanr task stal€s Biih a qlical tlsk diagran (oB rsrk, a Eplxi. Yourdon Dre mdology (0slr,ikt h Dr.$ Md cplain conte*diaamm lirr drling dlen nr case oltrard atrd Mellormedod. 3. irh adiaElnr-cxpldn dlgilali.pul inrcdace b. lxplain rirh a near diagan,nalog ouqrul slnen. c Dra snrsE chip conpulerand explain. d. Explxinconnrunicalions0ndlhcwrlsorcharacterizmgerillconnnunlclrion r Eplain rhe tullowinsr i)se.!nrr. ii) Reddabililv, iii)Ponxblh] b. Dxplain cxcepdon hardliirs. i. wid a diaga'n, explain t6skchaining and swapping. b. Dn* fie ngurc lor: ilnon prfrt,oned. ii) oanilioned merory. d. {hrrrsLirenes:r ErFlai. a. Lrpldnsoli$aEdesignincascolprelifrinarydesignolRTSSwirhdiagmn b rilotr- Jre.o ' roieso.ndo-.l'grud,ppo"h c fxthinmuli-tulkingapnroach Dillerdnriale ben.en $'id & l.llorand ll!rlcy & Pirbhai tucrhodologics. Lrplaii, thc archirccrur toodel in ce ofHarleyand Pnbhni ndthod
  • 2. l0EC7.l t,. diasnm. Also rvite the liming (06 lllirk$ (06M!rkt an exanpl.. what.re rhe hde (03 ]llark, 106lrrkt (0nvr, (06virk, SemesterB.E. DesreeExamiration, De..2014/.Ian.2015 2 ! i'a :; n€ :; 2: iL iE i Embedded System Design Note: A,s4zr Fll/E la q "srio's, rele.ti,g alleart TwO .laation! lro each Dan. PAR'I' A ni) Wdchdoglirnel (06 t,rrt w a block diagra,n, explain biely rhe laious componcnh in a microprccesor based eDrbedded slslcin. (0? NbrD Briefl) descnbe rhe najor elenrenls olthe embedded sy$ctu developnent lilb cl.le. (07 Nrsrk) Explain diEd and rcsist$ rdirccl.ddre$ing ftodes rvith dlaCram lorsenal wrile operarion si& an 3 bil regiler. i) BisEndianMd lifrle lndian lonn s ii) ltlscandclscregire^ iii) T'ucalion d iorndinAoma. Erilain the direct mapplne cache hmagement slrdegy Nirh o1lbetrveenvnG throush md delayed u e auonlhm? Exrlain the iNemal dia8rafr oISRAM aid wile dninsdilgnrn Wrno the inside lnd ouaidedhgmins lorDRAM along *nh Erd Elplain Asocirtive mappi.g cichc i'npletuentation. Write ihe llo* diagmms lbi wdoii,ll and V lifecycle models and brieflI explain waterlall *cPs. (06M,r9 Wile a harduare architecruE dd daio and counter loy diagrar ola c.unter srsrcn and cxplah briefly foR 'liagmm (03 Nrert , Erplatu the chancrerizing and ddnrii,ing the Equiiemenh oln system, wil]] rcspc.r ro a dlgnal counrer 06 M!rk, PARI B Discuss l8skcontolblo.k 'lEnrion sonr ollhe mjor coinpo.ents oflask i) Proarain andprcces il) Pro.e$srandrhreadr iii) Li$l weighted and healy wclghled rhreads Explah the dillarenr tuncrions ofembedded opcLaling.
  • 3. b. Descnbe vintral model a.d high lelelnodel lorOS architectures. c wite lne algonfin lora simple OS kenel, usine C lansuage nolation tasks usina TCBk only. The 3 tasks use a comon dila bufEr for Discuss loresou. backgoun'i sysren. Mention Descnb. the mlhods by Nhi.h wc cm perfom lime coding dalysis ofan embedded lppticalior. 10EC7l rhe difeEnce be een lbregrornd dd a. Write the Amdahfs limitarion for perlbma..e improvenent/oprimization. Consid.r a system wtu lne loilowins cnaEcleristics. Thc iasr 1o be analysed and nlproled.uftnrly execuies in I00 timeunits, and the goaln b reduce exe.ution line to 50 unirs. ihe alsornnm 10 be imprcved uses 40 rinre unils. Detemile de unknom peanreler and wnre Ge c, wnte'C tuncrions io delemi.e Ihe sun orrhe elemenls in an amr aod dallze it iincby line ror ih inne conpGdy. (06 M.*, (06lurI, a tine coding analysis olan enrbedded a DiscBs fie advulaaes and dradvdagcs (03 M.rk, a. Doscribe bedory loading wi1n equado., ligue md an example. b. wrile shonnotes on lhs lollowi.g ' i) Tricks ofthe nade ii) Perrdft dce oplinizalion.
  • 4. l0Ec73 Seventh Semester B.E. D€qree Examination! Power Electronics Dec.20l4lJrn..2015 lor.t AhlMt an! FMJi qr.stiohst szl..rit* anea:t TwO 4uestioi! ftotu ea.h Dart. 2E 9. == ii ,-e Z PART - A d McntionanylbNpropeftiesofasuperpowerdeviceshouldposses- (0?usrk, b. wh0t isa convefter? Hor' ,re a.r'er conveneB cla$,fied? Explainbiien) (mn,rk, c. l'lention sonie ituporraDi advlrtages and disaduDtages olp (0a ]r!rt, d whlt arc rhe pedpheral e flf cts oapowerelecnoDicsconvcneN a.dhowrhey are overcomel (06II!rl, , The collector clanrping circuir of liig.Q.lG) has thc lollowjne paramctNr vuB = l4v. Rtr = lO. P = 15, vuF = 0.7V, VD: = 0.9V, Vr,:2 LV. P:2O. V.r = 120V, Find n Co lle r tor curen.vithou r clampnrsi ii) Collearor emittcrclampi.g loltaeci ili) Colle or curent Nnh clampinr (0s lr,rl, Fig.Q2(a) b. Dra the $rilching nrodel ofMoSFET a.d erplai. s switching c. Whxr is an IGBT? Compare IGBT $ith B.,T lnd MOSFET. d. why isolaljon h rc.ded?Explain the t*omethodsofholarion ith a neat figurc oaplai. rhe dynamic rum-on and tum offcharacteriti. ora th)nstor (03 irl! , Bieflycxplain drdt and drdiprotccrionolSCR (06m!.k, Design a UJT relaxation oscillator lor triescrnrg an SCR. sith UJT havi4 lhe tbllo$ine p,r,heter rt = 0 72. h = 60f A. = 4mAj v! = 2.5v, vBB = 15v, RBB = 5KO, leakage cuneDl with enitter open N lnrA. Also calculate ninimtrn rnd maxnnum valuc of RC variablc rcsisrance). (o6Nr*k, w irh a cncuit diagran a.d $avclorns explain the workingorasrgle phase senn.onr.lled rcctifier. Derivc an cxprc$ion lor rhe aknge voltage acrcss rhe R-L load. (03rvlrrk, Forasinglethae tullycontrolled bridse rectifier Bith hig|ly inducrilc load and coDtnruous curcnt..btain avcrae. )oad lolrage and cure il rhe load reshtance k l0O and firing anglc is .15". and is fed fion 230v. 50112 supply Dmx the load volrage waleaorm and supply curcnt Faveiirrm. (06 Mark, Lhat is a dual.o.veter? Explain nsopera.onurrh a neat circu dirgmm. (06 Nt{rk, '':
  • 5. t0EC73 PART' B Statcthe.o.dnionsrobesaxsfiednrrpmpertum-ofofscR (0:rhrk, with rhe heh orcituit diasranr aod wareform cxplain rhs operurionofselfcommurarion rn rhe hg.Q.5(c) rhe source vortage v, = l00v a.d rhe .uren.t.",gt n, ",,a l-1"r1'i!? The tu6 ofl tlme ofbofi rhe SCRS n 4otrsec. Find the lalue ofcapa.ndr fo.succo$ful commuration andhencc sho rhd cncuil tunoiltine is 0.693 RC. (03 ]hrrtt Iie Q st) cncuit shown in FigQs(d) the balt€ry lohdgd $ l00V and thynstor tum otl titue s 4oBsec. Asume 5O9l rolerancc ofrhe commutniion ci(un. (o{nrrkn In tu auxiliary conrmutalion Maxinun load curent is 40A on nm.ffiime Find ! ,nd a a. Disringnish beiqeen o. ofconm!a.d nhasecontrclofAColrlge coDnolter. (01M$r, b. lxplain the opraion otsingle plase bidiiectioDal AC louage conrollcr lor nrductive bad t h the help ofcncuit diaeEmand $avelbms. c An AC lolragc controlE nas a resistiYe load oI R = too, and RVS mput lolrase is v = 120v. 50Hz The thrrnror switch n on for n = 2t cycles lnd oJI fom:75 cvctes Findr i) rDs ouqur ioltagei ii) Input porer factor iii) Ale.age and RUS dlrisror cuncnr and heDce derive the above expre$ions for VmandtF. (lontrrk, a. Explain the working princille olstep donn chopper a.d derive expesion lnr i) Arera[c outpnt loltage; ,i) Output po'{ rn) Efcctive nrpur rcsisrahce tu tehb ofchopper dnry b wnnthe helpof a cncun diasraD.explanrfouquadrantr$e! ohoppcn. Osrrrrk, c. A step up choppcr has i.pnt lollage or220v and output vohagc ol660v. lfdre non conducting heofthe tbrntor is loo|rsec. compurc rhe pulse widrh olth.ourpur!.lta!e lt rhcpuhewidth is halved forconsta ncqucn.y operatio n, furd ney ourtul loltage 04MrdO rixplaln a si.gle phase rull bidge inveiler nnh relela cnclir dirganr and Nalcfom! A$udeR I load. (0r jrlrkt with the helpolcncun diasraD and Nave tnrms cxplain rhe opeBtion oftransisrorized CSI (.urenr source i.vdre, ftar ae the dva.ta8es anddnadvamagcs oICSI? c. The inglephase halfbridEe nrlerrcr bas thcDC input ol48v Tne bad resistan.e n 4 31) Determi.c: l) RMs lalue oa ihe ourFur voh4ei ii) RMS laluc ol rhc lrnnamentat cornponertri ii)ToL.lha.montr d.r,'ri r '. ri!.Q.5(d)
  • 6. 6 qt - '. l:lt togclrE72 ...": Sevenah Semester B,E. Degree Optical Fiber ' .16 $'- Examination, Dec.201:l/Jan.201s Coftmunication ? v 2! i2 a3 3: ,, ; ? a with near sketchcs ol Rl protle aid *ave propagarion i. oprical cotuparc diileient twes ortbe6l b. wil r € .NeLJhe. cpa1 F.t-r-p'J. .1oor'".i,-.dEe. lpl.n. 4, Dp'o,r.. i{ ' rr 5 Note. A"swer FM lull qrcsliohs, set .line att.ast Two qaestions fron each Dart. Explain different typcsofafienulhon inopticalfib(. (06 Nr.rk, Cla$ily and cxplain.hmtutE d[perion wirhin a si.gle mode fiber. (0srrrrk, Consider a l0 kn long "rultirode in whicb nr = 1.,183 and d = o 0l Calcuhrc nr a.dpuhe bruadning aner krclling l0 km (06 N{,rk, a Exphin $irh schemarican LED whicbis hlghly dneciionaland skei.hrhe b. Comparc op ed ting pam mercrs olc", S, ard IncdAsofPlN and APD c. with ne skerch. explain &$D srucure rnd rhe elcctrical tields b. Explain expanded be,h fiberoptic courecror. c. Lnr selcral po$ible leDsing s.hcme xrd e{plai. bricfly non nMsing lensing schene (07IIrrkt PART -B a. Dra* a signalpath lhtuugh a dignal li.k snh retcvant conponenh and oprtcaL/elcoriical a. Eaplain dilleEnr qpes offiber spli.ing nElhod used loroprical libeE. Explain savefoims at ersy saae (06 'rrrktwhdt aF the noisc so!(e anddntudances thatarisc inoldcalpulse derectior mechanismt, Erphi', drcm in dcrail, {06 ivre, DBw and capla,n eye pattemerd mark rhc tundatunral mea$yclne.r Faranere. (0sNrr.k, a. what is nse rime budecr? Expla its sisninca.ce Denve an exprcssion for rhe sy cm risc 'iroebJdo". en,o r"L11r.r I'b ldre(e.e r.c in" b. laplanr subcanier multipleai.g. rvith neat block diasram t0srerkt c Denre an expressiotr tbr d1e CNR oaan analog con'nuricanon sFtem urdcr limiring co.dilionofnote sources involved. (0? lrl,
  • 7. i i,Y#I'HIT#ii],.trff Dc q'ioB r*ec or@dc!, anp,ine^ c. lxphrn d,ehctric rhD 6t; fi,teraDd tusapplicatioN t0ECnE72 <, '7d,. , ] nh kor eGrgy hvet diasEd, erDlain EDFA / r. wflteaioEoo. L Baic a6rm:r ^f a - STS N -SONET md , ,sTM-N SD}I fam. iD Hipsp.ed risht w,r liDks. 1i. '.rj. ',)(, ' t.,, .C, ) )4' '/) _ . i,{' .. )' . ir' >.<. l (r' ) (i <). ir ^
  • 8. IOEC/TE?1 SeveDth Semester B.E. Degree Examinatior, Dec.20r.r/Jan.2015 Computer Communication Networks Nore. Ats||o a,! FIVE full qwslions, selednta .n.ast TwO qkstions Jiott each pan. PART A a D,scu$ rhe TCP,IP Dodel wnh EncrioDahies of eaclr la_ver. Corider sourca deln.anon ard nrcr cdirte nodes tnrdiscussion. (10)r{rk, b. ExDhnr the diflcrcntscniccsprorldcd by re lep ho.c ncisorks. tor!*k, . Des.nbe tuu lerclsoladdrc$in-q used in intemct (TCPilP) withexanrplcs. (06!rkt '| z; 1- i.] '.4 1a . whar is HDLC? Explai. diifeE.r name lbmts $ith controlfield used byHDLC 110:rr3rk9 A system uses eop-and{van ARQ froto.ol lfea.h tx.ket carEs 2000b s ofdata ho{ long does it take to scnd I nnllion bits of dara rf tbe speed is 2 t lor Drsecl JsDore fiansmission. aitiDC 0nd proccsing dclars. wc 0sume .o dala or co.hl nam. n los or danra-qed Repeat aor ga back nwiin wiMow) ste = 7 (i0lrrkt whal is cbainelizallon in dre context ofnrultiple acces? what are v lois channelizarion tedDiqresl Extlain CDMAtcch.iquc OoM$ks) Tso sirti.ns A a.d C a.e connectdd to a $ared channel with data raie to4bps. Thc distance betrveen A and C is 2s()()n and the proposarion speed is 2 : lor ns. Starron A stans s.ndinC a bng naEe at rime r = 0i sarion C rMs sending a lone filme at tinre rr = lUs.c Tbe size ofdre lia.r is long e.ough to guaniree rhe detedi.n ol.ollisionby bothstations.Ftud i) TIc timc w[cn station C heas thc collh]oi (tr)i ii)-limerhenstation A hcas dre collhion t1): iii) The trtrmber ol6its A bas senr betnE det.ctinE the colhrof: PART.B a. tsriefly cxplain ihe nfte cnierla sotat3.spare.i b. Erphnr thc nilbwing connc.rin! dcli.cs i) i!) Router; v)GftcwaI bridge wnhexreple (r0[I*[t Passivc hub: ii) Rcticarfr iii) tsridsc: 00 Nturl) iv) Thentrnberolb sChas sedt beturedetechg thec.llnDn a Ertl,in rhc MAC nam. formatoll!EE802.3 Write 0 note on name Ien:th. b. ErphinthefeaturesofvACsublalcrandphtsi.allayerofCieabitEthe.r.t. a. Uhrt is NA-Il laphnr hos addres rralsl.rion is donc in NAT. (0qllirl6) b. ![y lPv4 to lPv6 tansitio. is iequncd] what are various te.h.iques nsed i. tansllionl Explain !hem. (ot rt,rln c Bnn!duianyld,fere.cesbeNeenlPV4&dlP!6addressingschenes Or^t,rkr)
  • 9. l0Ec/Tn7l ':L ,u4, Fie.Q.?&). a. Explair distece veclor rcrting with an oxample. b. With a @t loq chafi explain Dijksta algorithn ftr the ret*ork shoM in Assune 'A' as rcot node. Mention the rculilg lable for Dot A. Refer Fie.Q.7(bl. o.cv "?., ,,,a, Fis.Q.7(b) "" f,b" 9 .o q-, is TCP better rhan LrDP? Explai, sivics olferEd !y TCP. h Name SnacE? HYd:ir n .la(sined'l Wnat '( DNS? 'i ,. s Q -.i! ,o',-- 'o- ,g dr*
  • 10. ,i' l0Ec75r i? i;i a, .1 a= iZ ;i; ; Seventh Semester DSP B.E. Degree Examination, Dec.20l4lJan.20ls Algorithms & Architecture otet Aas||d l:IvE ful questioas, setedihg at leasl TWO qrcslio s lro,t oath pan . ExplainadigitalsignalprocessinesysremN h the help ola block diasrer. (07Nlrrk, b. Lin the @joi unique architeclural lealrcs implemcntcd ina.y prosanbable DSP dcvi.es (01Nlrr$ Derire lhe relationship between DrT and lrcqDency response abd also deline liequency resolutiotr and signal rec. lengd {06 M,rk, An FF-I is employed rir derernring the liequenq conDonents ofa randon signal lt is .equncd ihar lh. rssolurion oflFT to be <=5 Hz. rir a slgnal wnh i,," = 1.25 kHz. DeErnine i) Samplirg intc al.Ts. ii) rFT lcngrh (N) as a po*erol2. ii)Minimdtu sig.alEcord length. @1M!rk, r Dra$thenructureola,l,4Braunmnltiplicrabdahoexplainitsopenrion. (0Brkrkt b F,rplanl the ponner updarins aLsonrhm for crcular addre$ing node (0sMrrk, c. Compute thc s.quence iD rvhich rhe input dara should be ordered irr a 16 point DIT r_FT !si.8 Br revered addr.$i.g mode. Otiu.rr, Describe thc lolloN e units ofTMsi2oc54xx pro.e$o. i) tsaml sh,ftc. ii) C.Drml DroccssiDgunit (03 ]larr, what is nleant by addresine flodel, Eaplain the absolltc. accunrulator. dtect and nrdn€cr addressing nrodes ofTMs3zocs4xx DSP proce$or. (l2tr3rkt Dcscibe thc opcration oltne followins instrucrions: il 4Ac 'AI{3-. +AIl4+. ts, A ]D MAS lAR].. *AR+. B.A !ASI=-B wha. n drc sigrific.uce of Q {o rxrion in DSP? Rcpresent e Bch of the folLowingnutube^ in desned Q-notarlon tbmat: iii) tsDAFh iiQ,lndQ j nuNber. l!) 0.160121as Qr. number v) 4.100h Rs Qr nuDrbf lxpl.in $nh rhe help ol block diagrrD and oarheMticat equalions dccim.rio. tiltcr or TMS320C54xx processor lxplain thc had$ard ri'nerofTUS320C5]XX DSP siih logical block dragram. Fp.. r rp.p!l'eo|e1 ono lVs.o_iatrolc.--.
  • 11. a. What minimum size FFT nust be led.o coipute 50(]poinls DFrt W[ar musr r0EC751 lhe enples before the choen FFI is applied? b. Dqiw tne optimum scaling frctor for tbe DIT FFT bure.fly c wrre ar assmbly ldn"irge pograr ro|mpl.ren-Dg i) Bit Evmed addre$ eeiemrioi ii) Spectrum ofthe transformcd dola. W[at is an intempt? With a nea! flow cbart cxplain handlins of intcmpr by TMs32oc54xxprccesso. o0lvrkr) How does DMA help in incEasing lhe speed ofa DSP prccesor and alro explain regnrer sub addrssing tccnnique for conigui.g DMA. (t0 Mlrks) a wilh 6eat block diag.ln explain the DSP b6sed biorelcmeny receiver. b. With neat block diagram explain rne CODEC inrdface cncuir. tollosine on TMSl.20C54xX