The document discusses ways to improve throughput on Agilent 3070 test systems. It describes optimizations that can speed up analog tests like capacitors and inductors using features of the ASRU-N card. Test generation algorithms were improved to group nodes logically and optimize settling delays. Enabling features like auto-optimization after debugging can further reduce test times. Ensuring tests are regenerated when converting from Unix to PC and optimizing testplans, statements, and inhibited safeguards can also yield significant throughput improvements. A large board test case showed over 45% faster runtimes when optimizing an initial Series 5 testplan.

1. 3070 User Group IMPROVING THROUGHPUT
Meeting 2012 ON THE 3070
Agilent Measurement System
Division
Rodrigo Cantu
Applications Engineer
September 14, 2012
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2. Agenda
1. What takes time on the 3070.
2. Analog test time improvements
3. ASRU-N
4. BT-Basic testplan synchronisation
5. Series 5 Digital throughput
6. PC and Icap card
7. Large Board Example
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3. Pins Test
•Pins test or Chekpoint verifies that there is good contact between the
Board under Test and the test fixture.
•To improve throughput it should only be run on failures.
•If the board passes then Pins Test does not need to be run.
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4. Shorts Test
•Original Shorts test algorithm is inefficient.
•A very simple algorithm is used to generate the test.
•There is no logical grouping of the nodes tested
•Settling delays are not optimized.
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5. New Shorts Test
•At software revision 7.20 the test generation algorithm was rewritten.
•Nodes are now placed in logical groups in the shorts test.
•Settling delays are optimized.
•Debug is minimized.
•Test time is improved.
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6. Revised Capacitor test
Capacitor test generation modified to reduce the use of the
fr128 option and therefore the ed option.
If fr1024 is used more often, ed is not required, tests run faster.
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7. ASRU N
•ASRU N speeds up test time for analog tests
•Capacitor and inductor tests run faster
•Wait statements in other tests are optimized to run faster
•ASRU N uses a Digital Measurement Circuit
•Tests using „as‟ option should be regenerated to ensure the correct test
options are selected to maximize analog throughput.
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8. Effect of "en" & "ed" options on Analog Unpowered Test Time: up to 25x slower
tests
1. FETs, Jumpers, etc.
(There is no adaptive algorithm applied for these tests)
ASRU-N MCU (2nd
Asru C(2nd run)
run)
No en, no ed 5.9ms 3.8ms
En only 17ms 3.8ms
Ed only 23ms 20.5ms
En, ed 155ms 20.5ms
En/ed effect 25x 6x
2. Resistors
ASRU-N MCU (2nd
Asru C (2nd run)
run)
No en, no ed 3.57ms 3.8ms
En only 4.3ms 3.8ms
Ed only 21.3ms 20.5ms
En, ed 21.5ms 20.5ms
En/ed effect 6x 6x
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9. 3. Capacitors
128Hz (this frequency always comes with ED option)
Asru C(2nd run) ASRU-N MCU (2nd run)
Ed only 35.8 20.6ms
En, ed 53.5 20.5ms
En/ed effect 1.5x 1x
Capacitor – 1024Hz
Asru C (2nd run) ASRU-N MCU (2nd run)
No en, no ed 5.7 5.6ms
En only 7.1 5.6ms
Ed only 24.3 12.9ms
En, ed 44.3 12.9ms
En/ed effect 7.5x 2x
Capacitor – 8192Hz
Asru C (2nd run) ASRU-N MCU (2nd run)
No en, no ed 5.4 4ms
En only 7.3 4ms
Ed only 24 12ms
En, ed 44.3 12ms
En/ed effect 8x 3x
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10. Auto Optimizer
•Available from software revision 7.00.
•Should be used after Auto Analog debug to optimize analog test time
•Rules based optimizer configured by user
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11. I3070 GUI – Testtime column
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12. Testplan Optimization
•All statements except for „test‟ are inefficient
•BT-Basic commands force a testhead sync
•Parallel DUT supplies should use the “optimize” statement
•Powered tests should NOT be safeguard inhibited
•Safeguard cool enforces delays between tests
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13. Series 5 Digital Speedup
•Series 5 allows 12Mbit/s digital testing
•Default digital vector cycle time is 2MBits/s
•Large Boundary Scan and Silicon nail tests run quicker
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14. PC Hardware and Icap card
•Latest testhead hardware has benefits for large tests
•Large Boundary Scan tests, silicon nails, run faster
•Device programming tests (Flash, ISP) run faster
•Flash/ISP software will bring maximum throughput.
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15. Unix to PC conversion
•Converting from Unix to PC is just the first step
•For best results test should be regenerated
•Old tests use old test methods and are not optimized
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16. Large Board Test Time Pareto Analysis
250 120%
100%
200
82% 80%
150
60%
100
40%
50
20%
0 0%
Time (seconds)
Acc %
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17. Large Board Test Time Comparison
Series5
Series5
Section Series 3
Initial Optimized
Test
Pins 12.625 12.625 0
PreShorts 35.8 19.016 7.782
Shorts 5.97 5.984 8.671
VTEP 3.81 4.063 4.047
Aunpowered 154.89 111.937 29.531
Stage Ch to FCT 6.828 5.453 5.375
PS1 4.55 3.86 3.875
BS Interconnect 0 0 8.125
Stage Ch to ICT 14.532 13.453 15.969
Psupply 4.77 3.703 3.844
Bscan ICT 32.11 26.469 29.078
Digital ICT 14.47 9.718 12
Analog FCT 4.332 0.985 1.062
High Freq Osc 8.212 8.212 8.172
LED 35.656 35.656 22.313
EEPROM 13.06 10.297 10.125
Total (Seconds) 351.615 271.431 169.969
Total (Minutes) 05:51.6 04:31.4 02:50.0
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