The document describes the process and structure of a power MOSFET transistor. It involves growing an N- doped epitaxial layer on an N+ substrate to support high voltages between 1000V-500V. For lower voltages below 100V, a thinner N- layer is used. The structure also includes a P+ body region, N+ source regions, and a polysilicon gate. Key parameters that determine the transistor's current capability and on-resistance include the channel width and length, gate oxide thickness, and doping concentrations. The on-resistance is made of several parasitic resistances and increases with temperature.

1. POWER MOS TEC H NOLOGY PROCESS

2. X ~ 600  m N + EPY Substrate N +  ~ 10 m  • cm N +

3. N + N - BUFFER LAYER N - X ~ 10  m  ~ 5  • cm Low Voltage ~ 100 V N - X ~ 80  m  ~ 50  • cm Hight Voltage ~ 1000 V N -

4. N + N - X oxide ~ 1  m OXIDE GROWTH SiO 2

5. N + N - Mask and chemical attach Photoresist Photolitografy

6. N + N - P - Ring Creation Ionic Implantation P (B o Al) and Diffusion

7. N + N - P - P + Ionic Implantation P + Deep-body (P + ) x j ~ 3 ÷ 6  m C s ~ 10 19 at/cm 3

8. N + N - P + P - Growth gate oxide Polysilicon deposition Oxide etching Gate Creation

9. P + N - N + Gate Creation Polysilicon Gate oxide

10. P P + N - N + Implantation and diffusion B Photo-technic Channel Creation

11. Source Implantation N ++ P P + N - N + Diffusion Channel Creation

12. Dielectric Deposition N ++ P P + N - N + Contact Metallization Metal Dielectric

13. PMOS Structure N ++ P P + N - N + Metal Dielectric Polysilicon Gate Oxide

14. N ++ P P + N - N + W c L c

15. N ++ P P + N - N + 3D PMOS Structure

16. G S Layout PMOS

17. 2D Simulation PMOS Cell 10 20 10 17 10 14 1  m at/cm 3

18. Parasitic Elements in PowerMOS Structure

19. D G S PowerMOS Structure S G D

20. D G N - P + S Parasitic Elements in PowerMOS Structure S G D

21. G D N - P + N + S Parasitic Elements in PowerMOS Structure S G D

22. G D C R p N - P + N + S Parasitic Elements in PowerMOS Structure S G D

23. Parasitic ON conditions i · R p  V be Static Conditions Dynamic Conditions D C R p S dt dV i = C dt dV = R p · C V be

24. PowerMOS Current capability

25. G S D + + - 0< V GS < V T V DS > 0 I D = 0

26. G S D + + - V GS  V T V DS > 0

27. V GS > V T V DS > 0 I D > 0 G S D + + -

28. V DS [V] I D [A] R ON V G Current capability: I D On State: R ON Output Caracteristics PMOS 10 20 30 10 20 30 0 40 0

29. V DS [V] I DS [A] T=25 o C T=125 o C Current - Temperature 5 0 10 15 0 40 80 120  T  I D = f ( , )  T  V T  T 

30. The PMOS structure contain inside parasitic Bipolar elements. The current flow vertically The current capability depends from geometric parameters (W C ) and physical ones (X ox , L C , V T ) Ron increasing with temperature

31. PMOS Ron

32. G D S N - P + N + j-fet parasitic S G D

33. R epy R c R acc R jf R front R back R DSon = R c + R acc + R jf + R epy + R front + R back

34. R epy R epy R epy =  N  X N A - k -

35. R c Channel resistance L c L c Channel Length W c Channel Perimeter L c d  Q N 1 W C L C R c = =  C ox (V G -V T ) 1 W C L C

36. Channel resistance R c R c =  (V G -V T ) 1 W C L C X ox L c d

37. R acc =  (V G -V T ) k 2 W C d X ox Channel resistance R acc d L c d d Distance cell to cell

38. R j-fet = f( ) j-fet Resistance d, Wc  , X j N - L c d R j-fet X j N -

39. R ON of high voltage PMOS (> 500 V) Depends from epitaxial layer R epy R ON of low voltage PMOS (< 100 V) decrease with: high integration density

40. BV DSS [ V ] 10 100 1000 10000 R ON AREA [m  cm 2 ] 100 1 10 0.1 1000 PMOS Ron PMOS

41. PMOS VLSI tecnology metal gate