1. FPGA implementation of a multi-channel HDLC
protocol transceiver
GAO Zhen-Bin LIU Jian-Fei
School of Information Engineering
Hebei University of Technology
Tianjin, China
Email: paozhenbin@ismail.hebut.edu.cn
I .
Abstract-An HDLC protocol transceiver was designed, which frames etc.. The HDLC controller in some system are
contains two full-duplex channels, a build-up 4K-bytes dual- implemented in FPGA or ASIC[3-61, but they have less
port RAM and an interrupt management unit. On principle of functions or aren't flexible, such as working only at quire
Top-Down design, the VHDL modeling of the main modules, mode or having no inner memory. Some of them are aimed
such as transmitter, receiver, memory management unit were at special applications, and only transmitter or receiver was
discussed. The design was implemented in a Virtex FPGA. It designed for single-channel.
has the characteristics of simple, flexible, and easy in use.
In this paper a HDLC transceiver is designed and
implemented with FPGA for general applications, it has
I. INTRODUCTION double full-duplex channels, a build-up dual port RAM
High-level data link control (HDLC) is a bit oriented (DPRAM), and an interrupt controller. Controlled by the host
protocol developed by the Intemational Organization for CPU with a few of commands, the chip can receive or
Standardization (ISO)[l]. It has been so widely used because transmit HDLC frame structure automatically, and provide
it supports both half duplex and full duplex communication the status when the operation is finished, The control-
lines, point to points (peer to peer) and multipoint networks, registers, that dominate the work mode of the transceiver,
and switched and non-switched channels. The procedures may easily be set, and the baud rate of each channel also can
outlined in HDLC are design to permit synchronous, code- be changed.
transparent data transmission, Other benefits of HDLC are
that the control information is always in the same position 11. SYSTEM DESCRIPTION
and specific bit patterns used for control differ dramatically
The HDLC protocol transceiver consists of the following
from those in representing data, which reduces the chances
main blocks as shown in Fig2
of error; [2].
HDLC uses the term "frame" to indicate an entity o f data Control unit, Registers and Bus buffers;
(or a protocol data unit) transmitted. Fig.] below is a Two channels: channel A and channel B;
graphical representation of an HDLC frame with an
information field [l]. Each frame starts and ends with a flag Dual port RAM and RAM management unit;
sequence (01111 llO), which is used for frame
Interrupt controller;
synchronization.,The frame is transmitted from left to right,
least significant bit first. Transparency (Zero stuffing) is
performed whenever five contiguous "I " bits are transmitted. Interrupt
controller
The Standard Interface Chips (SIC) such as 8273/8274 or
82530 are usually used in system with HDLC controller. But Control
unfortunately, due to complicated peripheral circuit and unit
software program of SIC, some problems appear in actual
applications based on SIC, which include dead halt, drop-out
1 Flag [ Station Address I Data 1 FCS [ Flag 1 Registers
I
Dual port RAM
I
Figure I . HDLC Frame Snucture Figure 2. The diagram ofthe iransceiver
Corresponding author: CA0 Zhen-Bin
0-7803-901 5-6/05/$20.00 02005 IEEE. 1300

2. A. Cuntrol unit and Registers
The control unit has the functions such as address
decoding, command decoding and so on. The chip uses this
block to communicate with CPU for instructions and status.
Data shift
register
4 P
stuffer
Bit
CRC shift Ciock
CPU can also retrieve the data that has been received from or Stan Controller reg,ster
store the data that is to be transmitted to the build-up
DPRAM through this unit.
There are 16 registers in the chip, 8 for each channel,
f
Data apply . 1 Baud rate
including status registers and configuration registers as listed Figure 3 The diagram of transmitter . .
in .Table I. CPU can identify these registers with 4-bit
address A3A2A1 AO, which points to the registers ofchannel The CRC shift register is a 16-bit linear feed back shift
A when A3 is 'U, to channel E.
else register, used for computing the FCS, which is a 16-bit
Cyclic Redundancy Check (CRC). The bit stuffer inserters
B. Channel A and Channel E: extra zeros into the bit stream to avoid transmission of the
They are identical, each composed with a transmitter and control flag sequences within the frame data. The clock
a receiver for full duplex data transition. generator generates the clock signal used for the transmitter,
whose frequency is determined by the data value in baud rate
1)The transmitter register and the frequency o f the transceiver's main clock.
The transmitter is in charge of transmitting data through
common data link, and doing transparency operation and The station address in the frame is set by the CPU, which
FCS operation. Its block diagram was illustrated in Fig.3. is stored in RAM and can be any arbitrary address, .or
The operation flow of the transmitter is like the following: broadcast of "all-stations'' Address, which are all ories. :
After system initialization, it transmits the flag sequence 2) The wceiver
(01 1 I 1 1 IO) continuously. When the "start" signal was assert The receiver receives the data of a frame, in which the
by the CPU, the transmitter will apply to the RAM address field is identical with the receiver's station address or
management unit for the data, and loading it into the data is all-stations address, then, aRer discards the "0"s for
buffer at first, then issue the appropriate flag sequence transparency operation, stores data into build-up DPRAM
(01 I 1I 110) and transmit the data, applying for the next data through the RAM management unit. Its structure is shown in
at the same time. The FCS is calculated along with the Fig.4.
transmitting of the data. When the "finish" signal was assert When the "start" signal was assert by the CPU, the flag
by the R A M management unit, the FCS is transmitted, detector searches for the beginning of a frame, while the
followed by a closing flag (0111 IIlO). When all the address identifier will decide if the frame is aimed at this
operation is finished, the transmitter gives a signal to the station, and restart frame searching process if not. The zero
interrupt controller, and the status is latched. discarder, CRC shifi register, invalid frame detector, bit
At anytime during the transmitting, when the abort signal counter and byte counter works altogether when receiving a
is assert by the CPU, the transmission of this frame is frame. Under whichever of the following three conditions,
aborted by sending the Abort flag, which is (01 I 1 1 I 1 1). the receiving operation is stopped:
The controller is responsible for generating all the e The synchronization flag is detected again;
necessary internal control signals required by the different The abort flag is detected by the invaIid frame
modules. It is implemented using a Finite State Machine detector.
approach.
TABLE 1. REGISTERS IN THE C H I P
1-1 Register 1 Description I
The beginning address of the DPRAM for thc
TxDataAddr
t a l a 10 be transinitted
I 0 0 1 ITxDataNum ]The number ofthe data to bc transmitted 1
1 ,
o,
(kx,,ataAddr
The beginning address of the DPRAM for the
/data should be received
1 0 I 1 IMaxDataNum IThe maximum data number of a frame 1
detector
1 '
renisler
-
buffer
I I I
Command/Stalus Operation command when CPU writing; Zero
I discard
Channel status when reading
I I Work mode/ work mode when CPU writing; Flame
Interrupt Status lnterruot status of the channel when reading error
1 I 0 Baud rate The baud rate factor of the clianncl
1 I I Starion address The slation address of the channel Figure 4. The diagram of receiver
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3. exceeds the maximum data number of a frame. Resource Used Available Utiliralion
Then the receiver gives the status that marks the results ~
4 input LUTs 854 1,536 55%
of the operation, such as if there’s any error occurred. lOBs $1 98 52?6
Block RAMS 18 18 I 100%
C. The DPRAMand the memory managemenl ml i Slice Flip Flops 1610 I1,536 I 39%
The DPRAM stores the data to be transmitted or the data
The reason for using Virtex FPGA i s its various built-in
have been received, one of its ports connects to CPU and the
other connects to the RAM manage unit. It is shared by both features that solve designer’s challenge throughout the
channels, through a RAM management unit, for data change system. This family provides a broad capability for chip-to-
with CPU. chip communications through programmable support for the
latest U 0 standards, digital Delay-Locked Loops (DLLs) for
The RAM management unit takes order of the RAM-
clock signal synchronization on the FPGA and on the board,
accessing requirements of the two channels for both
transmitting and receiving operation. It contains four address and a memory hierarchy to manage fast access to RAM on
pointer counters for each operation of each channel. It offers and off chip[7]. Table I1 summarizes the device utilization
the proper data to the transmitter and stores the data from the for Virtex FPGA with a speed grade o f -4. The controlling
receivers to the RAM with proper addresses. Using data part of the HDLC protocol transceiver is found to be running
number counter to record that how many data has been at a frequency of 40 MHz, and each channel may work at a
transmitted, it can also determine if the transmitting should frequency up to I O MHz.
be finished.
The main part of the RAM management is a finite state 1V. CONCLUSION
machine, as shown in Fig.5. When a requirement appears, it In this project, HDLC protocol transceiver with double
does the RAM accessing operation, and then resets the full duplex channels has been successhlly implemented in
requirement. Because it is driven by a higher frequency clock Xilinx Virtex series FPGA. Using FPGA gives you the
than the transmitter or receiver, all the requirements can be flexibility, upgradeability and customization benefits of
responded in time. programmable logic devices. The transceiver can be used for
bit-oriented packet transmission, and is suitable for Frame
D. The interrupt controller Relay switches, Cable Modem, Private packet data networks
There are four resources of interrupt in the transceiver: an and switches etc.
intempt requirement may come in to being when either of
the two channels finished transmitting or receiving. The ACKNOWLEDGMENT
interrupt controller handles these requirements, and informs
This work was supported by Chinese Hebei Natural
the CPU with interrupt status.
Science Foundation(No.F2004000072).
The interrupt status include if the operation is finished
successhlly and the error status such as FCS error, frame REFERENCES
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Figure 5. The finite state machine ofthe RAM management unit
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