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Cell Verification Metrics Sanjay Gupta Cell Verification Lead STI Design Center 6/27/2006
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object]
Background ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Overview ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Architecture SPU LS MFC SPE0 PPE SPU LS MFC SPE7 … Bus (EIB) Bus Interface Controller (BIC) Memory Interface  Controller (MIC) To Main Memory To Southbridge Chip or to another Cell Chip
Verification  Process
Verification Planning ,[object Object],[object Object],[object Object],[object Object],[object Object]
Verification Phases SYSTEM PARTITION CHIP ISLAND UNIT Phase1 PH2 PH3 PH4 PH5 Phase3 Phase4 Phase5 Phase1 Phase2 Phase3 Phase4 PH1 PH2 PH3 PH4 PH5 PH1 PH2 PH3 PH4 PH5 PH1 PH1 PH2 PH3 PH4 PH5 PH1 PH2 PH3 PH4 PH5 Time
Statistics ,[object Object],[object Object],[object Object],SPU MFC EIB MIC BIC PU Unit/Island Environments Found 95% of Bugs SPE, PPE Partitions: 0.2% of Bugs Full Chip: 3.5% of Bugs Cell, 4 SPE Cell ,[object Object],[object Object],[object Object],30 Simulation  Environments Verification Environment Hierarchies
Metrics ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Metrics – cont… ,[object Object],[object Object],[object Object]

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Cell verification dv club

  • 1. Cell Verification Metrics Sanjay Gupta Cell Verification Lead STI Design Center 6/27/2006
  • 2.
  • 3.
  • 4.
  • 5. Architecture SPU LS MFC SPE0 PPE SPU LS MFC SPE7 … Bus (EIB) Bus Interface Controller (BIC) Memory Interface Controller (MIC) To Main Memory To Southbridge Chip or to another Cell Chip
  • 7.
  • 8. Verification Phases SYSTEM PARTITION CHIP ISLAND UNIT Phase1 PH2 PH3 PH4 PH5 Phase3 Phase4 Phase5 Phase1 Phase2 Phase3 Phase4 PH1 PH2 PH3 PH4 PH5 PH1 PH2 PH3 PH4 PH5 PH1 PH1 PH2 PH3 PH4 PH5 PH1 PH2 PH3 PH4 PH5 Time
  • 9.
  • 10.
  • 11.

Editor's Notes

  1. Today I would like to talk about some of the trends we see in microprocessor development. As you’ve heard, IBM and my organization is now the major developer for game processors. Many people expect a next wave of innovation in processor and system design to come out of this space. This is a reasonable expectation, since gaming hardware, and particularly networked gaming hardware, occupies an increasingly central place in the home. The business models around content delivery on these platforms, now primarily games, but in the future most likely a much wider array of educational and entertainment (and perhaps even business!) applications, creates immense value and allows for a significant investment to be made in the development of these processors. And to innovate, you need two things primarily, innovative people, and money!
  2. Ideals: The verification process has been created using a top down specification, bottom up implementation. The process strives to be modular and automated, with a focus on reproducibility, performance, and commonality.