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Unit2 control unit


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Unit2 control unit

  1. 1. Computer organization
  2. 2. Organization of control units
  3. 3. Basic concepts <ul><li>To execute a program, the will fetch the contents of memory location pointed to by the PC and they are loaded to IR </li></ul><ul><li>Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered </li></ul><ul><li>After loading instruction to IR, PC is incremented. </li></ul><ul><li>Carry out actions specified by instruction in IR </li></ul><ul><li>The above phases can be considered as fetch phase and execution phase </li></ul>
  4. 4. Basic concepts <ul><li>An instruction can be executed by performing one or more of the following operations </li></ul><ul><ul><li>Transfer a word of data from one processor register to another or to the ALU </li></ul></ul><ul><ul><li>Perform an arithmetic or a logic operation and store the result in a processor register </li></ul></ul><ul><ul><li>Fetch the contents of a given memory location and load them into a processor register </li></ul></ul><ul><ul><li>Store a word of data from a processor register into a given memory location </li></ul></ul>
  5. 5. Basic concepts <ul><li>The registers, the ALU and interconnecting bus are collectively referred to as the datapath </li></ul><ul><li>There are certain registers which are used by the processor for temporary storage during execution for some instructions </li></ul>
  6. 6. Basic concepts <ul><li>Transferring data between registers </li></ul><ul><li>The input and output of the a register are connected to the bus through switches controlled by the signals R in and R out . </li></ul><ul><li>In order to transfer contents of R1 to R4, </li></ul><ul><ul><li>Enable output of register R1 by setting R1 out to 1.This places contents of R1 on the processor bus </li></ul></ul><ul><ul><li>Enable the input of register R4 by setting R4 in to 1.This loads data from the processor bus into register R4 </li></ul></ul>
  7. 7. Basic concepts <ul><li>Performing arithmetic instruction </li></ul><ul><li>E.g. add contents of register R1 to those of register R2 and store the result to R3 </li></ul><ul><ul><li>R1 out ,Y in </li></ul></ul><ul><ul><li>R2 out ,SelectY,Add,Z in </li></ul></ul><ul><ul><li>Z out ,R3 in </li></ul></ul>
  8. 8. Performing arithmetic and logic operation Ri Y mux A B ALU z Processor bus select Constant 4
  9. 9. Basic concepts <ul><li>Fetching a word from memory ; move (R1),R2 </li></ul><ul><ul><li>MAR  [ R1] </li></ul></ul><ul><ul><li>Start a read operation on the memory bus </li></ul></ul><ul><ul><li>Wait for MFC response from the memory </li></ul></ul><ul><ul><li>Load MDR from the memory bus </li></ul></ul><ul><ul><li>R2  [MDR ] </li></ul></ul><ul><li>To accommodate the variability in response time, the processor waits until it receives an indication that the requested read operation is completed ,such a signal is the MFC signal </li></ul>
  10. 10. Basic concepts <ul><li>R1 out , MAR in , Read </li></ul><ul><li>MDR inE , WMFC </li></ul><ul><li>MDR out , R2 in </li></ul>
  11. 11. Basic concepts <ul><li>Storing a word in memory ;move R2,(R1) </li></ul><ul><ul><li>The desired address is loaded into MAR </li></ul></ul><ul><ul><li>Data to be written is loaded into MDR </li></ul></ul><ul><ul><li>Write signal is initiated </li></ul></ul><ul><ul><li>R1 out , MAR in </li></ul></ul><ul><ul><li>R2 out , MDR in , Write </li></ul></ul><ul><ul><li>MDR outE , WMFC </li></ul></ul>
  12. 12. Execution of a complete instruction <ul><li>Various steps are involved in executing a complete instruction (e.g. Add (R3),R1 </li></ul><ul><li>Fetch the instruction </li></ul><ul><li>Fetch the first operand </li></ul><ul><li>Perform the action </li></ul><ul><li>Load the result </li></ul>
  13. 13. Execution of a complete instruction <ul><li>Add (R3),R1 </li></ul>Z out ,R1 in , End 7 MDR out , Select Y , Add, Z in 6 R1 out , Y in , WMFC 5 R3 out , MAR in , Read 4 MDR out , IR in 3 Z out , PC in , Y in , WFMC 2 PC out , MAR in ,Read, Select 4, Add, Z in 1 Action Step
  14. 14. Execution of a complete instruction <ul><li>In step 1 , the contents of PC are loaded to MAR and a read request is send. The select signal is set to select 4. </li></ul><ul><li>This value is added to operand at input B, which is the contents of the PC and the result is stored in Z. </li></ul><ul><li>The updated value is moved from register Z to PC during step 2, while waiting for the memory to respond </li></ul><ul><li>In step 3, the word fetched from the memory is loaded into IR </li></ul><ul><li>Step 1 to 3 is the instruction fetch phase </li></ul>
  15. 15. Execution of a complete instruction <ul><li>The instruction decoding circuit interprets the contents of the IR at the beginning of step4 </li></ul><ul><li>Step4 to 7 is the execution phase </li></ul><ul><li>The contents of register R3 are transferred to the MAR in step 4 and a memory read operation is initiated </li></ul>
  16. 16. Execution of a complete instruction <ul><li>The contents of R1 are transferred to register Y in step 5,when read operation is completed, the memory operand is available in register MDR </li></ul><ul><li>The addition is performed in step 6 </li></ul><ul><li>The result is stored in step 7 </li></ul>
  17. 17. Execution of a complete instruction <ul><li>The end signal causes a new instruction fetch cycle to begin by returning to step1 </li></ul><ul><li>In step 2 , it is not necessary to transfer contents of PC to register Y </li></ul><ul><li>But if any branching occurs, the updated value of PC is required to calculate the branch target address </li></ul>
  18. 18. Execution of a complete instruction <ul><li>Branch instructions </li></ul><ul><li>Branch instruction replaces the contents of the PC with target address </li></ul><ul><li>This address is usually obtained by adding an offset X, which is given in the branch instruction to the updated value of PC </li></ul><ul><li>If the branch instruction is at location 2000 ,if the branch target address is 2050 offset must be 46 </li></ul><ul><li>If it is a conditional branch , the status must be checked before branching </li></ul>
  19. 19. Execution of a complete instruction <ul><li>branching </li></ul>Z out ,PC in , End 5 Offset of IR out , Add, Z in 4 MDR out , IR in 3 Z out , PC in , Y in , WMFC 2 PC out , MAR in ,Read, Select 4, Add, Z in 1 Action Step
  20. 20. Control <ul><li>Two main approaches used for implementing the control unit of a processor are </li></ul><ul><li>Hardwired control and </li></ul><ul><li>Micro programmed control </li></ul>
  21. 21. Hardwired control <ul><li>Each step in a sequence of control signal is completed in one clock period </li></ul><ul><li>A counter may be used to keep track of the control steps </li></ul><ul><li>Each state or count of this counter corresponds to one control step </li></ul>
  22. 22. Hardwired control <ul><li>Each state or count of this counter correspond to one control step </li></ul><ul><li>The required control signals are determined by </li></ul><ul><ul><li>Contents of the control step counter </li></ul></ul><ul><ul><li>Contents of the Instruction register </li></ul></ul><ul><ul><li>Contents of the condition code flags </li></ul></ul><ul><ul><li>External input signals, such as MFC and interrupt requests </li></ul></ul>
  23. 23. Hardwired control Control step counter Step counter External inputs Condition codes Encoder Instruction decoder IR clock End Run INS1 INS n T1
  24. 24. Hardwired control <ul><li>The step decoder provides a separate signal line for each step or time slot, in the control sequence </li></ul><ul><li>The output of the instruction decoder consists of a separate line for each machine instruction </li></ul><ul><li>For any instruction loaded in IR, one of the output lines INS1 is set to 1and all other lines are set to 0 </li></ul><ul><li>The input signals to the encoder block are combined to generate the individual control signals </li></ul>
  25. 25. Hardwired control <ul><li>E.g. Z in = T1+T6.Add+T4.Br+……… </li></ul><ul><li>The end signal starts a new instruction fetch cycle by resetting the control step counter to its starting values </li></ul><ul><li>When Run signal is set to 1 the counter is incremented at the end of every clock cycle </li></ul>
  26. 26. Hardwired control <ul><li>The sequence of operations carried out by the wiring of the logic elements ,hence the name hardwired </li></ul><ul><li>A controller that uses this approach can operate at high speed </li></ul><ul><li>It has limited flexibility and complexity of the instruction set it can implement is limited </li></ul>
  27. 27. Micro programmed control <ul><li>Here the control signals are generated using program similar to machine language programs </li></ul><ul><li>A control word is a word whose individual bits represent various control signals </li></ul><ul><li>Each of the control steps in the control sequence of an instruction defines a unique combination of 1’s and 0 s. </li></ul>
  28. 28. Micro programmed control <ul><li>A sequence of CW s corresponding to the control sequence of a machine constitutes the micro routine or micro program for the instruction </li></ul><ul><li>The individual control words in the micro routine are referred to as microinstructions </li></ul>
  29. 29. Micro programmed control <ul><li>The micro routines for all instructions in the instruction set of a computer are stored in a special memory called the control store </li></ul><ul><li>The control unit can generate the control signals for any instruction by sequentially reading the CW’s of the corresponding microroutine from the control store </li></ul>
  30. 30. Microprogrammed control 3. 1. PC out, MAR in, Read,Select,Add,Zin 2. 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 1. E nd WMFC R3 out R1 in R1 out Z out Z in Add select Y in IR in MDR out Read MAR in PC out PC in Micro instruction
  31. 31. Basic organization of a Micro programmed control unit Starting address generator IR μ PC Control store Clock CW
  32. 32. Micro programmed control <ul><li>To read the control words sequentially from the control store, a micro program counter is used </li></ul><ul><li>Every time a new instruction is loaded into the IR, the output of the block labeled “starting address generator’ is loaded into the microPC </li></ul><ul><li>The microPC is then automatically incremented by the clock, causing successive microinstructions to be read from the control store </li></ul>
  33. 33. Micro programmed control <ul><li>Sometimes the control unit has to check the external signals or condition codes </li></ul><ul><li>So branching may be necessary </li></ul><ul><li>In order to incorporate branching, the circuit is modified </li></ul>
  34. 34. Micro programmed control Starting address generator IR μ PC Control store Clock CW External inputs Condition codes
  35. 35. Micro programmed control <ul><li>When a new instruction is loaded into the IR , the micro PC is loaded with the starting address of the micro routine for that instruction </li></ul><ul><li>When a branch micro instruction is encountered , and the branch condition is satisfied, the micro PC is loaded with the branch address </li></ul>
  36. 36. Micro programmed control <ul><li>When an End microinstruction is encountered, the micro PC is loaded with the address of the first CW in the micro routine for the instruction fetch cycle </li></ul>
  37. 37. Micro programmed control – address sequencing –micro instruction sequencing <ul><li>Incrementing of the control address register </li></ul><ul><li>Unconditional branch or conditional branch , depending on status bit conditions </li></ul><ul><li>A mapping process from the bits of the instruction to an address of the control memory </li></ul><ul><li>A facility for sub routine and return </li></ul>
  38. 38. Microinstructions with next address field <ul><li>The increase in branch instruction may create problems if we are using incrementable μ PC </li></ul><ul><li>An alternative is to use an additional address field which indicate the address of next instruction to be fetched </li></ul><ul><li>So separate branch instruction is not necessary </li></ul><ul><li>So there is no need to use a counter for sequencing </li></ul>
  39. 39. Micro instruction sequencing organization μ AR Control store Next address OR gate μ IR Microinstruction decoder Decoding circuit IR Condition codes External inputs Control signals
  40. 40. Microinstructions with next address field <ul><li>So μ PC is replaced with micro instruction address register μ AR </li></ul><ul><li>The next address bits are fed through the OR gates to the μ AR </li></ul><ul><li>Any modification required for the address can be done on the basis of data in the IR , external inputs and condition codes </li></ul><ul><li>The decoding circuits generate the starting address on the basis of the output code in IR </li></ul>