This document presents a study on accelerating the computation of the Pearson Correlation Coefficient, a statistical algorithm used to model functional connections between clusters of neurons in the human brain. The study designs an FPGA-based system to compute the Pearson Correlation Coefficient and compares its performance to a multi-threaded CPU and GPU implementation. Experimental results found that the FPGA solution guarantees the lowest energy consumption while the GPU achieves the best execution time. The FPGA was concluded to provide the best trade-off between performance and energy efficiency for this application.

1. Enrico Reggiani
enrico2.reggiani@mail.polimi.it
Eleonora D'Arnese
eleonora.darnese@mail.polimi.it
Andrea Purgato
andrea.purgato@mail.polimi.it
Marco D. Santambrogio
marco.santambrogio@polimi.it
Pearson Correlation Coefficient acceleration for
modeling and mapping of neural interconnections
June 08th, 2017 @ Xilinx

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A more precise comprehension of human brain is of
great interest in many fields
Medical Research Neuromarketing
Context

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Huge improvements have been done thanks to:
Biomedical Technologies Analysis Methodologies
Context

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• FPGA-based system computing a statistical algorithm
used in the biomedical field
• Compare the FPGA-based system results against:
• Multi-threaded CPU
• GPU
Contributions

5. The human brain interactions are usually described by:
• nodes: cluster of neurons
• edges: functional connections
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Case Study

6. r (𝒙𝒊 𝒚𝒊)
The Pearson’s Correlation Coefficient represents the degree
of relation between clusters of neurons
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Case Study

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Proposed Implementation

23. Experimental Setup:
• Xilinx Virtex 7 FPGA
• Intel Xeon 5650 with 24
hyper-threads
• Nvidia GeForce 1080
GPU
4 different DataSets have
been evaluated
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Results

24. Experimental Setup:
• Xilinx Virtex 7 FPGA
• Intel Xeon 5650 with 24
hyper-threads
• Nvidia GeForce 1080
GPU
4 different DataSets have
been evaluated
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Results

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• GPU achieves the best execution time
• Proposed FPGA solution guarantees the lowest energy
consumption, being the best device in terms of
efficiency
• This work demonstrates that an FPGA-based hardware
accelerator can be considered as the best trade-off
between performances and energy consumption.
Conclusions

26. Enrico Reggiani
enrico2.reggiani@mail.polimi.it
Eleonora D’Arnese
eleonora.darnese@mail.polimi.it
Andrea Purgato
andrea.purgato@mail.polimi.it
Marco Domenico Santambrogio
marco.santambrogio@polimi.it
Thanks
Pearson Correlation Coefficient acceleration for
modeling and mapping of neural interconnections