Mike Dang has extensive experience in wafer sort tooling process and technology development for leading edge memory and logic device testing. As a Technical Supplier Chain Manager at Intel, he managed supplier selection and developed technical strategies to evaluate technologies for high volume wafer testing of 10-20K wafers per week. Previously, he developed the first high volume manufacturing Mems sort process for Flip Chip interconnects and defined process and product reliability risk matrices. He has a BS in Mechanical Engineering from UC Davis and an MS in Engineering from Cal Poly San Luis Obispo.

1. Mike Dang
www.linkedin.com/in/mike-dang-5313613
Cell (408) 315-3030 mhdang@hotmail.com
Hands-on problem solver with extensive experience in wafer sort tooling process and technology
development for leading edge memory full wafer test and logic high pin count and high power device
test. Lead cross-functional team to deliver cost saving for wafer test process across world-wide factory
network. Partnered with senior leaders to define wafer test tooling roadmap, specification and strategy.
Possesses diverse technical experience in the following disciplines:
• Supplier Chain Management, Focus on Quality, Cost, On Time Delivery and, Sustainability.
• Technology Development for Mems Wafer Test Probecard & Printed Circuit Boards.
• Process and Module Development for Wafer Sort.
• High Volume Manufacturing Deployment of Newly Developed Wafer Test Technologies.
Possesses strong problem solving, written and oral communication skills, and experience leading cross-
functional working groups.
Professional Experience
Intel Corporation 2010 – 2016
Wafer Test Tooling Technical Supplier Chain Manager
Managed Supplier Selection for high volume manufacturing to provide best in class wafer sort solution:
• Developed technical and commercial strategy to evaluate multiple technologies for development and
deliver multi-generations solution for high volume manufacturing to test 10-20K wafers per week.
• Negotiated collaboration agreement with suppliers to establish intellectual properties agreement,
scope of work, deliverables, schedule, and cost.
• Managed supplier quality and delivery performance during high volume manufacturing ramp from
100K probes per week to 200K probes per week in 1 quarter.
• Developed should cost model and monitored line yield metrics to drive continuous improvement for
cost and lead time reduction.
• Performed onsite audits to assess and monitor quality system, manufacturing process capability,
metrology process capability and factory capacity.
• Conducted market intelligence to document industry wide technology pipeline.
• Synthesized industry trend and supplier base capability to influence the development of silicon
design rule for wafer sort process, leveraging off the shelf solution avoided development cost and
time.
Intel Corporation Oct 1997 – 2010
Sort Process Development Engineer
Developed best in class sort process for Flip Chip interconnect:
• Developed and certified the first high volume manufacturing Mems sort technology & process for
tight pitch solder bumps array to meet best in class contact resistance, current capacity and lifetime.
• Collaborated with supplier to design Mems micro spring for multiple process generations.
• Designed experiments to characterize micro spring/probe reliability, lifetime and process run rate.

2. • Lead the virtual factory joint engineering team that managed wafer sort silicon design rule and
module operating specification for copy exact proliferation to worldwide fab network.
• Conducted path-finding to enable first Full Wafer Contact wire bond sort process for Nor Flash:
• Developed full wafer 200mm Flash memory parallel sort technology to improve productivity by 5X.
• Developed 85 degree Celsius sort soak process to increase module throughput time by 15% and
improve positioning accuracy to attain defect free process.
• Innovated the redistribution layer with the implementation of aluminum cap extension to relax first
level interconnect pitch and enabled the removal of the space transformer from probecards to reduce
cost by 20% and lead time by 30%.
• Defined process and product reliability risk matrix, designed reliability experiments to qualify sort
on active die area for high volume manufacturing.
• Lead team to develop virtual factory web based SPC sort process health indicator tool.
Sanmina (Hadco) Corporation, Watsonville, CA 1995 - 1997
Printed Circuit Board Process Engineer
Qualified thin film photo resist process for high volume manufacturing of inner and outer layer printed
circuit board:
• Delivered 2 mils line & space resist process of inner layer conductors.
• Characterized and optimize dry film application, exposure and development process parameters with
statistical process control to optimize yield to 90%.
• Qualified environmentally friendly process from solvent based to water based.
• Managed chemical recycling programs to minimize hazardous waste generation.
• Lead cross-functional teams to drive continuous improvement on process yield.
EDUCATION & TRAINING:
• BS Mechanical Engineering, UC Davis, Davis CA
• MS Engineering, Cal Poly, San Luis Obispo CA
• Model based problem solving (7 steps problem solving)
• FMEA
• Design Of Experiment
• Statistical Process Control/Taguchi SPC method
• JMP
• Monte Carlo Simulation
• Weibull analysis
• Gage Repeatability and Reproducibility
• AutoCAD/SolidWorks
• ISO 9000 quality system
• Intellectual Property Management Tools: CNDA, RNDA, Collaboration Agreement
• Hazardous waste management training