50120130406023

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50120130406023

  1. 1. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING & ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME TECHNOLOGY (IJCET) ISSN 0976 – 6367(Print) ISSN 0976 – 6375(Online) Volume 4, Issue 6, November - December (2013), pp. 204-211 © IAEME: www.iaeme.com/ijcet.asp Journal Impact Factor (2013): 6.1302 (Calculated by GISI) www.jifactor.com IJCET ©IAEME AN APPROACH TO SOLVE GRAPH PARTITIONING PROBLEM USING GENETIC ALGORITHM Prof. Sharadindu Roy, Prof. Samar sen Sarma University of Calcutta ABSTRACT This paper addresses the problem of partitioning a graph and particular the use of the genetic algorithms for graph partitioning. It is a NP hard problem. The solution of a graph (circuit) partitioning problem is global optimum. In this practical paper solution is easy and we can easily apply genetic operator in this type of problem. One of the application of Graph partitioning in chip designing. The target of our approach is to design modular chip which can be realized with self standard IC chip if VLSI circuit can be converted into a graph and obviously we have taken into account minimum power consumption. Our approach to partition the Graph into sub Graphs and minimization of the number of cuts is our main objective. Our approach with Genetic algorithm calculates the fitness (number of cuts) and discard the solution with low fitness value. Multi way partitioning can be easily implemented if we increase number of crossover point. Fitness value achievement depends on crossover and mutation probability. We can change crossover boundary when fitness value is low in previous generation and continue until optimum result is found. keywords: Genetic Algorithm, NP-Hard, Net List, Crossover, Mutation, Cut Size, Partitioning. INTRODUCTION Graph partitioning consist of dividing a graph into parts(sub graph) each of which can be implemented as a separate component(e.g. a chip) that satisfies certain design constraints one search constraints is the area of the component. The limited area of a component forces the designer to lay out a graph (circuit) on several components. There has been a larger amount of work done in the area of graph partitioning and clustering. In graph partitioning, the graph is divided into two (Bi-partitioning) or more (Multi-way partitioning) parts. A chip may contain several million transistors. Due to the limitations of memory space and computation power available it may not be possible to lay out the entire chip in the same step. Therefore the chip is normally partitioned into sub-chips. These sub-portioned are called blocks. The 204
  2. 2. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME actual partitioning process considers many factors such as the size and of the blocks and number of interconnection between blocks. The output of partitioning is a set of blocks and the interconnections required between blocks. Minimization of delay due to inter connection between partitions and ratiocut minimization. Efficient easily applied algorithms for optimal clustering to minimize delay in digital networks were developed by Lawler at al.kernighan and lin proposed heuristic for two way partitioning which was the first iterative algorithm based on swapping of vertices. PARTITIONING IS REQUIRED TO MINIMIZE THE NUMBER OF CUTS The number of inter-connection among partitioning has to be minimized. Reducing the interconnection not only reduce the delay but also reduce the interface between the partitioned making it easier for independent design and fabrication. It is also called min-cut problem. Area of each partition is used as a constraint to reduce the fabrication cost with minimum area or as a balance constraint so that partitions are of all most equal size. Various researchers have achieved varying level of success using various optimization techniques. The current work attempts to use simple genetic algorithm for multi way graph partitioning. Because genetic algorithm is an emerging technique. This technique has been applied to several problems, most of which are graph related because the genetic metaphor can be most easily applied to these types of problems. Genetic requires more memory but take less time. PARTITIONING MEANS WE CAN Divides the circuit into smaller partition that can be efficiently handled Start with initial partition Count cut size Find best partitioning (minimum cut size). THE GENETIC ALGORITHM INVOLVES THE FOLLOWING BASIC STEPS Evaluation( evaluating the fitness value) Crossover(Part of the first parent copied rest is copied from second parent. Two crossover points are selected, binary or octal string from beginning of chromosome to the first crossover point is copied from parent 1. The part from the first to the second crossover point is copied from the second parent and the rest is copied from the first parent. crossover point is copied from parent 1. The part from the first to the second crossover point is copied from the second parent and the rest is copied from the first parent Mutation rate is the probability of mutation which is used calculates number of bits to be muted. The mutation operator preserves the diversity among the population which is also very important for the search. Mutation probabilities are smaller in natural population leading us to conclude that mutation is appropriately considered a secondary mechanism of genetic algorithm adoption. Individual 1101011101110100 and mutation probability, Pm = 0.375 Then we say, 6 bit will be inverted. Cut size Cut size is number of edge between partitions 205
  3. 3. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME SOLUTION METHODOLOGY Graph will be partitioned initially with the cut. It is pointless to consider the cut cost of such nitially nets, since no matter how the graph circuit is partitioned and the net-list is traversed in a breadth list breadthfirst-search order and the nodes are assigned to the chromosome in this order. If two nodes are directly connected to each other, there is a high probability that there partition bits will be closed to part each other in the chromosome. The BFS sequence of the net-list will be parent 1 and any sequence of the net net list net-list will be parent. The genetic algorithm are not guar guaranteed to find the minimum cost (optimum), but able to find very good solutions for a wide range of problem. Each generation choice to best chromosome (Best fitness) from previous generation for parent. Best parent Chromosome representation For binary encoding B A Total node 6 Total edge 7 Cut size 5 D C F E Parent 1 A E B Parent 2 E B A F D C (BFS sequence) D C F (Any order) Encoded Parent 1 1 1 0 0 0 1 Encoded Parent 2 1 0 1 0 1 0 206
  4. 4. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME Algorithm Step1: Start step2: Input the graph (with Initial partition) step3: Traversed the graph (In BFS and Any sequence) Step4 Encode sequence(traversing) as partition number. Step5: Select parent1 and parent 2 Step6: Define crossover type and mutation probability Step7: Apply crossover operator on parents (Created child1 and child2) Step8: Apply mutation operator on offspring (on child1 and child2) (created muted1 and muted 2) Step9: Count fitness for each individual (calculate cut size) Step10: If optimum result is found then go to step14 else go to step11 Step 11: Chose two best fitness chromosomes for next generation (choice1 for 1st choice, choice 2 for 2nd choice) Step12: If choice1 & choice2 are not equal with previous generation then go to step 7 else go to step 13 Step13: Change crossover boundary and mutation probability and go to step 7 Step 14: stop Consider the graph with block number is assigned as in the following. A B E G C D H F 0 1 2 3 O P K L Q R M N 207
  5. 5. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME Some sequence with cutsize(fitness) and average cut is given as tabular form in the following. BFS sequence: A C D B O E Q R P H F G K M N L INDIVIDUAL CUT 0011020112332233 19 0001123233112031 19 0011123233112233 19 0 0 0 1 0 20 1 1 2 3 3 2 0 3 1 18 0011231233112233 19 0001 200112332031 AVG_CUT 23 19 EXPERIMENTAL RESULT AND DISCUSSION The above algorithm has been coded and run in MATLAB(7.3 version). The following graph contain 16 vertex and apply algorithm on the graph. This method has been used to minimize the interconnections that are the min cut problem with a balance constraint. Consider the graph with block number is assigned as in the following. A B E G C D H F 0 1 2 3 O P K L Q R M N 208
  6. 6. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME In this code we calculate minimum cut, maximum cut and average cut(mean cut).Some iteration wise result is given in tabular form in the following. Number of Generation MIN FITNESS 1 10 18 14 2 10 16 12 21 10 14 11 40 10 13 11 80 10 13 11 91 10 14 11 100 MAX FITNESS 10 13 We get mean fitness value = 11 AVG_CUT 11 This code also produce the following graph. This is “GENERATION VS FITNESS” graph. “GENERATION” is plot in the X-axis(0-100) and “MEAN FITNESS” plot in Y-axis(0-20). According to the graph we see that mean fitness value is 14 in generation 1 and reduced to 11 in generation 10 and continues to 21.If we see all the generation ,Fitness value is 11 in most of the generation. The optimum result is heavily depends on cross over and mutation probability. From the graph We see that mean fitness value = 11 209
  7. 7. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME CONCLUSION “Genetic Algorithms are good at taking large, potentially huge search spaces and navigating them, looking for optimal combinations of things, solutions you might not otherwise find in a lifetime.” According to the Charles Darwin’s theory –Choose the best ,Discard the rest is followed in this paper. We have followed to Holland regarding Genetic algorithm. The algorithm can partition graph into a number of sub-graph. Our method calculates the fitness value and discards solutions with low fitness value. Increasing the number of crossover points does not necessarily increase the fitness, as the fitness achieved depends on crossover and mutation probability. If the graph size will increase ,Binary encoding is less promising method .In those case Other method like octal encoding is used.In the above case we use octal encoding. We have followed survival of fittest of Charles Darwin’s theory. Main philosophy of genetic algorithm is followed to Holland. Circuit partition is one of the key areas in chip designing. The algorithm can partition circuit into a number of sub-circuits. Our method calculates the fitness value and discards solutions with low fitness value. The increase in number of crossover points does not necessarily the fitness, as the fitness achieved depends on crossover as well as mutation probability. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] P.Mazumdar and K. Shahookar. “Genetics algorithms for VLSI design” G.A.Vijaylakshmi Pai and S.Rajasekarna - “Genetic algorithms synthesis and application “ Dr.Ashwani Chandel, Dr.Rajeevan Chandel, Sandeep Sing Gill- “Genetic algorithms based circuit partitioning” B.W.Kernighan and S-lin “ An efficient heuristic procedure for partitioning Graph”. G. Wang, R.Kastner, W. Gang - “Application Partitioning on programmable platforms using Ant Colony Optimization”, journal of Embedded Computing Vol.2 Issue 1, 2006. Naveed Sherwani, “Algorithms for VLSI Physical Design and Automation”, third edition, Springer (India) Private Limited, New Delhi, 2005 E. Mirhard, M.Anis, M. Elmary, P. Ghafari, S. Areibi- “ A low power partitioning methodology by maximizing sleep time and minimizing cut nets”, IWSOC, Bauf, Alberta,Canada,pp368-371, July,2005. D. Kolar, Ivan Branica and J. Divokovic Puksec “ VLSI Circuit partitioning using Simulated annealing Algorithm”, IEEE Melecon, Dubrovnik, Croatia,May 12-15,2004. D.E. Goldberg, “Genetic Algorithms in Search, Optimization and Machine learning”, Pearson Education, 2004. Frank Vahid, Greg Stitt, Roman Lysecky “Dynamic Hardware software Partitioning: A First Approach” ACM/IEEE Design Automation Conference 2003, Anaheim, California, USA,pp 250-255, June 2-6, 2003. Maurizio Palesi,Tony Givargis, “Multi-Objective Design Space Exploration Using Genetic Algorithms”, Proceedings of the 10th international symposium on Hardware/software code sign, ACM Press, Estes Park, Colorado , .pp 67-72 ,2002. C. Ababei, G. Karypis, K. Bazargan and S.Navaratnasothie “Multi-objective Circuit partitioning for Cutsize and path-base delay Minimization”, IEEE International Conference on Computer aided Design, 2002. S. Areibi, “Memetic Algorithms for VLSI Physical Design: Implementation Issues”, Genetic and Evolutionary computation Conference, San Fransisco, California, pp140-145, July, 2001. H.Youseff and S.M.Sait, “VLSI Physical Design Automation”, McGraw Hill Publishers, New Jersey, 1995. 210
  8. 8. International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-6367(Print), ISSN 0976 - 6375(Online), Volume 4, Issue 6, November - December (2013), © IAEME [15] Davis, L (1991), Handbook of genetic algorithms, New York Van Nostrand, Reinhold. [16] Jenkins, W.M. (1991), Towards structural optimization via the genetic Algorithms, Computers and Structures, Vol. 40, No. 5, pp. 1321-1327. [17] José Ignacio Hidalgo, Juan Lanchares, Roman Hermida - Graph partitioning methods for Multi-FPGA systems and Reconfigurable Hardware based on Genetic Algorithms, Computer Architecture Department, Spain. [18] D.E. Goldberg, “Genetic Algorithms in Search, Optimization and Machine learning”, Pearson Education, 2004. [19] P. Subbaraj K. Sivasundari P. Siva Kumar 2007 An Effective Mementic Algoruthm for VLSI Partitioning Problem” Internatinal conference on ICTES Chennai India pp 667-670. Dec 2007 [20] F.M Johannes, “Partitioning of VLSI Circuits and Systems”, Proceedings of 33rd design Automation Conference, USA June 1996, pp 83-87. ISBN: 0-7803-3294-6 [21] A. Cincotti, V. Cuttelo, M. Pavone, Graph Partitioning using Genetic Algorithms with OPDX”. Proceedings of World Congresson Computational Intelligence IEEE 0-78037282.2002. pp 402 – 406 [22] Kernighan, B.W., Lin S 1970. An Efficient Heuristic Procedure for Partitioning Graphs, the Bell Sys. Tech. Journal, pp 291-307. http://www.cs.princeton.edu/~bwk/bt l.mirror/new/partitioning.pdf. [23] Shameem Akthar, Dr. D Rajaylakshmi and Dr. Syed Abdul Sattar, “A Modified Pso Based Graph Cut Algorithm for the Selection of Optimal Regularizing Parameter in Image Segmentation”, International Journal of Advanced Research in Engineering & Technology (IJARET), Volume 4, Issue 3, 2013, pp. 273 - 279, ISSN Print: 0976-6480, ISSN Online: 0976-6499. [24] Jayanta Kr. Choudhury, Anupam Dutta and Bichitra Kalita, “Decomposition of Complete Graphs into Circulant Graphs and its Application”, International Journal of Computer Engineering & Technology (IJCET), Volume 4, Issue 6, 2013, pp. 25 - 47, ISSN Print: 0976 – 6367, ISSN Online: 0976 – 6375. [25] M.Siva Parvathi and B.Maheswari, “Minimal Dominating Functions of Corona Product Graph Of A Cycle with a Complete Graph”, International Journal of Computer Engineering & Technology (IJCET), Volume 4, Issue 4, 2013, pp. 248 - 256, ISSN Print: 0976 – 6367, ISSN Online: 0976 – 6375. 211

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