Digital Design Session 24

Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2
Session 24: Focus
 Finite State Machine (FSM)
◦ Example: Turnstile
 Types of Clocked Sequential Circuits
◦ Moore Model
◦ Mealy Model
◦ Example circuits
 Analysis of Clocked Sequential Circuits
◦ Example 1: Moore Machine (partial)

Finite State Machine

Example: Turnstile
4
 Allows people to enter through only on one side. It can also have
controlled access (coin) to let people in.

Operation of Turnstile Operation Explained
 Operation is modeled with a State Machine or State
Diagram
 Turnstile can be in one of these two states
◦ Locked
◦ Unlocked
 Initially it is in a Locked condition
 Dropping a coin changes the state of the machine from
Locked to Unlocked
Inputs are:
1. Coin
2. Push

Turnstile Operation Explained
 In the unlocked state, when the cross bar is pushed
◦ One person can move in through the gate
◦ Turnstile changes back to Locked state
◦ The cross bar cannot be moved in the locked state even if it
gets pushed
 There by allowing only maximum one person to enter
for every coin dropped

Finite State Machine (FSM)
 A Finite-State Machine (FSM) or Finite-state
Automaton (FSA, plural: automata), finite automaton,
or simply a state machine, is a mathematical model
of computation.
 It is an abstract machine that can be in exactly one of
a finite number of states at any given time.
 The FSM can change from one state to another in
response to some external inputs; the change from
one state to another is called a transition.
 A FSM is defined by a list of its states, its initial
state, and the conditions for each transition.

FSM of Turnstile
 List of states
◦ Locked
◦ Unlocked
 Initial State: Locked
 External Inputs: Coin and Push
 Transitions:
◦ Locked to Unlocked (Condition: Dropping of coin)
◦ Unlocked to Locked (Condition: Pushing the bar)
Dark dot here
Shows the
Initial state

Types of
Clocked Sequential Circuits

What are Clocked Sequential Circuits?
 A logic diagram is recognized as a clocked
sequential circuit
◦ If it includes flip-flops with clock inputs.
 The flip-flops may be of any type, and the logic
diagram may or may not include combinational
logic gates.
10

Types of Clocked Sequential Circuits
Sequential Circuits
are built with
Combinational
circuits and flip-
flops
Clocked
Sequential
Circuits are also
called as
Synchronous
Sequential
Circuits
Flip-flops hold
the internal states
of the circuit
There are Two types of them
b) Outputs are driven by both internal
states and also by the inputs to the circuit
a) Outputs are driven only by the internal states
Flip-flops
Flip-flops
Outputs change only
At clock edges
Outputs may change
whenever inputs change

a) Moore Model
 In the Moore model, the output is a function of only the
present state.
◦ Present states are in tern driven by the inputs

b) Mealy Model
 In the Mealy model, the output is a function of
both the present state and the inputs.
 A circuit may also have both types of outputs.
 i.e., both Mealy and Moore type of outputs

Examples of

Example A: Sequential Circuit
 Which are the inputs?
 Which are the outputs?
 How many states can this circuit be in?
 Does the output (Z) change while the inputs change?
 The output is driven by?
 Is it a Moore or Mealy machine?
 How many flip-flops are needed to maintain two states?
15
X and Y
Z (same as A, the present state)
2 (D F-F can be a 0 or 1)
No
By A, is same as the internal state (A)
Moore Machine
1
Logic Diagram

Example B: Sequential Circuit
 Inputs:
 Outputs:
 No of states:
 Is Output a
Function (inputs
and internal
states)?
 Mealy or Moore?
16
X
Y
4
Yes
Mealy Machine
A
B
A
B
X
Y
X
Y
Logic Diagram

Mealy and Moore Machines
 These two models of sequential circuits are
commonly referred to as a Finite State Machine,
abbreviated FSM.
 The Mealy model of a sequential circuit is referred to
as a Mealy FSM or Mealy machine.
 The Moore model is referred to as a Moore FSM or
Moore machine.

Analysis of

Analysis of Clocked Sequential Circuits
 Analysis describes what a given circuit will do under
certain operating conditions.
 The behaviour of a clocked sequential circuit is
determined from
◦ Inputs,
◦ Outputs, and
◦ States of its flip-flops.
 The outputs and the next state are both a function of
◦ Inputs and the present state
 The analysis of a sequential circuit consists of
obtaining a table or a diagram for the time sequence
of inputs, outputs, and internal states

Example 1.2: State Equations
 The behaviour of a clocked sequential circuit can be
described algebraically by means of state equations.
 A state equation (also called a transition equation)
specifies the next state
◦ As a function of the present state and inputs.
Moore Machine
1.1 Logic Diagram

Session 24: Summary
 Finite State Machine (FSM)
◦ Example: Turnstile
 Types of Clocked Sequential Circuits
◦ Moore Model
◦ Mealy Model
◦ Example circuits
 Analysis of Clocked Sequential Circuits
◦ Example 1: Moore Machine (partial)

References
Ref 1 Ref 2

Digital Design Session 24

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Digital Design Session 24