THE supplementary information for the paper:” Pseudo DC-link EV Home Charger with a High Semiconductor Device Utilization Factor” [1] is presented in this document. [1] H. Heydari-doostabad, S. H. Hosseini, R. Ghazi, and T. O’Donnell, “Pseudo DC-link EV Home Charger with a High Semiconductor Device Utilization Factor,” IEEE Trans. Ind. Electro., vol. 1, no. 1, p. 1, 2021.

1. See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/350819142
Supplementary material for the article: “Pseudo DC-link EV Home Charger with
a High Semiconductor Device Utilization Factor”
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2. Supplementary material for the article: “Pseudo DC-
link EV Home Charger with a High Semiconductor
Device Utilization Factor”
Hamed Heydari-doostabad, Member IEEE, Seyed Hossein Hosseini,
Reza Ghazi, Member IEEE, and Terence O’Donnell, Senior Member IEEE
I. INTRODUCTION
THE supplementary information for the paper:” Pseudo DC-
link EV Home Charger with a High Semiconductor Device
Utilization Factor” [1] is presented in this document.
II. APPENDIX A
INDUCTOR RESISTANCE AND VOLTAGE GAIN RATIO
The conflict between the ideal voltage gain and the
operational principle of the converter can be resolved when
the non-ideal characteristics of the circuit components are
incorporated. Fig. A. 1 shows the proposed converter along
with its on-time and off-time sub-circuits, where the winding
resistance rL is included to a practical inductor, while the other
circuit components are still assumed ideal. The voltage gain
expression of the converter with the presence of rL is now
derived to investigate the behavior of the non-ideal proposed
converters.
V
bat1
+
Q1 Q2 S1
S2
L1 L2 L3
C2
C1
C4 C3
V
out
+
R
out
rL rL rL
(a)
V
bat1
+
Q1 Q2 S1
S2
L1 L2 L3
C2
C1
C4 C3
V
out
+
R
out
rL rL rL
(b)
Fig. A. 1. Proposed converter with inductor winding resistance,
ON-state (left) and OFF-state (right) sub circuits.
The volt-sec balance condition of the inductor is formulated as
L1 bat L1 L1
L2 C1 L2 L2
L3 C2 out L3 L3
L1 bat C1 L1 L1
L2 C2 L2 L2
L3 out L3 L3
ON-state: ,
OFF-state:
V V r I
V V r I
V V V r I
V V V r I
V V r I
V V r I
 


 

   

  


  

   

(A 1)
The desired expression for the voltage gain is now obtained
by solving (A 1) to obtain voltage gain. The resulting voltage
gain is arranged as the product of the voltage gain of the ideal
converter and the correction factor that accounts for the effect
of the winding resistor rL as follow
2
out
2 3
L L L
bat
out out out
1
( )
1
1 ( ) ( )
1 1
V D
r r r
D D
V D
R R D R D


  
 
(A 2)
The key parameter in the correction factor is the ratio of the
winding resistance to the load resistance, rL / Rout. Fig. A. 2
shows the voltage gain curves, calculated using (A 2) with
different values for rL / Rout. The voltage gain curves reveal
substantial deviations from the ideal case. The deviation
intensifies as the rL / Rout ratio increases, showing a wide gap
between the actual voltage gain and the ideal voltage gain
when the duty cycle is large. In particular, all the voltage gain
curves merge to zero as the duty ratio approaches unity, rather
than growing boundlessly. This phenomenon is actually
consistent with the operation of the converters.
0.6 0.7 0.8 0.9 1
0
2
4
6
8
10
12
14
16
18
20
Duty cycle (D)
Voltage
gain
ratio
rL / Rout = 0,ideal
rL / Rout = 0.002
rL / Rout = 0.004
rL / Rout = 0.006
rL / Rout = 0.008
rL / Rout = 0.010
Fig. A. 2. Voltage gain ratio of non-ideal proposed converters.
III. APPENDIX B
COMPARISON OF VOLTAGE AND CURRENT STRESS AND COST
OF THE PROPOSED CONVERTER TO THE STATE OF ART
The general information of all competitors are listed in
Table A 1, including the voltage and current stresses,
normalized total voltage stress of power switches (ΣjVSj / Vout
= TVS) and normalized total current stress of power switches
(ΣjISj / Iout = TCS).
Based on the information provide in Table A 1, the voltage
and current stress curves are plotted, which are shown in Fig.
A. 3.
Evidently, as the voltage gain ratio increases, the proposed
converter offers lower TVS than that of given in [2][3][4].
Furthermore, by increasing the voltage gain ratio, the TCS
of the proposed converter becomes lower than that of all given
competitors demonstrated in [2][3][4][5][6][7][8].

3. Table A 1
Information of Voltage Stress and Current Stress
Ref.
Voltage Stress
of Switches
ΣjVSj / Vout
Current Stress
of Switches
ΣjISj / Iout
[2]
VS1=VS2=Vout/D
VQ1=VQ2=Vout/D
4/D
IS1=IS2=IoutD/(1-D)
IQ1=IQ2=Iout
2/(1-D)
[3]
CIM
VS1=VS2=VS3=Vout/D
VQ1=VQ2=VQ3=Vout/D
6/D
IS1=IQ1=IoutD/(1-D)
IS2=IS3=IQ2=IQ3=Iout
(4-2D)/(1-D)
[3]
IIM
VS1=VS2=VS3=Vout(1-D)/D
VQ1=VQ2=VQ3=Vout
3/D
IS1=IS2=IS3=
IQ1=IQ2=IQ3= Iout/(1-D)
6/(1-D)
[4]
VS1=VQ2=Vout/D2
VS3=VQ1=Vout(1-D)/D2
VS2=VQ3=Vout/D
4/D2
IS2=IQ1=IoutD2
/(1-D)2
IS1=Iout(D2
-D+1)/(1-D)2
IS3=IQ3=Iout
IQ2=IoutD/(1-D)
(4D2
-4D+3)
/(1-D)2
[5]
VS1=VS2=Vout(1-D)/D
VQ1=VQ2=Vout
2/D
IS1=IS2=Iout/(1-D)
IQ1=IQ2=Iout/(1-D)
4/(1-D)
[6] VQ1=VQ2=VQ3=0.5Vout/D 1.5/D
IQ1=2Iout/(1-D)
IQ2=IQ3= Iout/(1-D)
4/(1-D)
[7]
VS1=VQ1=Vout(1-D)/D2
VS2=VQ2=Vout/D
2/D2 IS1=IQ1=IoutD/(1-D)2
IS2=IQ2=Iout/(1-D)
2/(1-D)2
[8]
VS1=VQ1=Vout(1-D)/D2
VS2=VQ2=Vout/D
2/D2 IS1=IQ1=IoutD/(1-D)2
IS2=IQ2=Iout/(1-D)
2/(1-D)2
Pro.
VS1=VQ2=Vout(1-D)/D2
VS2=Vout/D2
VQ1=Vout/D
(3-D)/D2
IS2=IQ1=IoutD/(1-D)2
IS1=Iout(1-2D)/(1-D)2
IQ2=Iout/(1-D)
(2-D)/(1-D)2
0 10 20 30 40 50 60 70 80 90 100
1
2
3
4
5
6
7
Voltage gain ratio (Vout/Vbat)
Total
voltage
stress
j
V
sj
/V
out
(TVS)
[5]
[2]
[3]CIM
[3]IIM
[6]
[7]
[8]
[4]
Proposed
(a)
0 5 10 15 20 25 30
0
5
10
15
20
25
30
35
40
45
50
Voltage gain ratio (Vout/Vbat)
Total
current
stress
j
I
sj
/I
out
(TCS)
[5]
[2]
[3]CIM
[3]IIM
[6]
[7]
[8]
[4]
Proposed
(b)
Fig. A. 3. Voltage and current stress comparison.
(a) Normalized curves of total voltage stress (TVS) versus voltage gain ratio
(b) Normalized curves of total current stress (TCS) versus voltage gain ratio
For providing a reasonable cost comparison, Ref [9] offers
an approach to calculate the active semiconductor cost vs.
semiconductor device utilization factor, which can be
expressed as:
F
T
U
P


 (A 3)
PT = Total semiconductor cost per output power;
α = Voltage de-rating factor: To attain a reliable operation,
typical voltage de-rating factors are chosen as 0.5 - 0.75
(for the worst case 0.5 and for the best case 0.75).
β = Current de-rating factor: To achieve a reliable operation,
typical current de-rating factors are chosen as 0.5 - 0.75
(for the worst case 0.5 and for the best case 0.75).
γ = Semiconductor device cost per rated output power of the
device, for which typical values are approximately
$1/1000VA or less.
UF = Semiconductor device utilization factor.
For a fair comparison, the IPW60R099 power MOSFET for
all competitors with a drain-source breakdown voltage (Vds) of
600 V, and the maximum current stress tolerance of 31 A at
the minimum operating temperature of -40°C and the
maximum operating temperature of +150°C is chosen. Each
power switch has the price of $6.64. The required number of
power switches for each converter must be substituted to γ.
Assuming a 1 kW output power and a voltage transfer ratio of
40 V to 400 V for all converters, the values of α, β and γ, are
considered for the worst and the best cases.
Based on these values Fig. A. 4 shows the cost of
semiconductors employed in competitive structures in the
proposed converter. In this figure, the worst (red series) and
the best cases (blue series) situations for the proposed
converter and the relevant structures are considered. The
vertical axis shows the cost in dollar per kilowatts ($/kW) that
must be allocated to the power switches.
Accordingly, the cost of implementing semiconductors (per
kilowatts) in the proposed converter is relatively lower than
the competitive structures in [3][4][5][7][8][10] in both the
best and the worst cases. It is worth noting that, the proposed
converter has four power switch, while [6] has 3 switches.
Despite this the cost of semiconductor implementation in the
proposed converter is approximately equal to that in [6], along
with offering the advantage of a higher voltage gain ratio.
0
10
20
30
40
[5],[10] [8] [3]CIM [3]IIM [6] [7],[8] [4] Proposed
6.75 7.27
1.2
17.71
0.34 0.7
3.2
0.43
15.2 16.35
2.67
39.9
0.76 1.6
7.25
0.97
$
/
kW
Converters
Best case Worst case
Fig. A. 4. Cost comparison of main bidirectional converters.
IV. APPENDIX C
EXPERIMENTAL TEST OF PROPOSED CONTROL SYSTEM
AGAINST DISTURBANCES
The performance of the proposed converter and control
system has now been tested for the load and source
disturbances and the results are provided in this section as
shown in Fig. A. 5.
As shown in Fig. A. 5, the performance of the proposed
control system against grid voltage (from 55 Vrms to 110
Vrms) and battery voltage (from 40 V to 80 V) disturbances
validates the fast and accurate dynamic response of proposed
pseudo dc-link approach.

4. vac,[100V/div.]
Vbat,[20V/div.]
iac,[5A/div.]
Ibat,[10A/div.]
[10ms/div]
vac = 55 [Vrms] vac = 110 [Vrms]
vac,[100V/div.]
Vbat,[20V/div.]
iac,[5A/div.]
Ibat,[10A/div.]
[10ms/div]
Vbat = 40 [V] Vbat = 80 [V]
(a)
vac,[100V/div.]
Vbat,[20V/div.]
iac,[5A/div.]
Ibat,[10A/div.]
[10ms/div]
vac = 55 [Vrms] vac = 110 [Vrms]
vac,[100V/div.]
Vbat,[20V/div.]
iac,[5A/div.]
Ibat,[10A/div.]
[10ms/div]
Vbat = 40 [V] Vbat = 80 [V]
(b)
Fig. A. 5. Transient waveforms of ac grid disturbance (up) and battery side
disturbance (down) during: (a) V2G and (b) G2V.
V. APPENDIX D
BATTERY SIDE REFERENCE CURRENT CALCULATION
Based on average power balance [11][12][13][14][15][16]
one can calculate the estimated ac side current as follow
*
*
ac ac,rms
ac,rms ac,rms bat bat
ac bat
*
*
bat bat
ac,rms ac ac,rms
ac,rms
( ) 2 sin
( ) 2 sin
v t V t
V I V I
P P
V I
I i t I t
V


 

  




  
(A 4)
Therefore, it can be based on the instantaneous power
balance, the battery side reference current can be obtained as
* * *
ac bat ac ac bat bat
* * *
bat ac ac bat
( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) /
p t p t v t i t V i t
i t v t i t V
     
 
 
 
(A 5)
REFERENCES
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Semiconductor Device Utilization Factor,” IEEE Trans. Ind.
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