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INPUT/OUTPUT ORGANIZATION
INTERRUPTS
CS147
Summer 2001
Professor: Sin-Min Lee
Presented by: Jing Chen

Topics Covered
¨ Transferring Data Between the CPU and I/O Device
¨ Types of Interrupts
¨ Processing Interrupts
¨ Interrupts Hardware and Priority
¨ Implementing Interrupts Inside the CPU

What is Interrupts ?
¨ Interrupts is a mechanism for alleviating the delay
caused by this uncertainty and for maximizing
system performance.

Transferring Data
Between the CPU and I/O Device
Polling:
One method used in small system to alleviate the problem of
I/O devices with variable delays.
In polling, the CPU sends a request to transfer data to an I/O
device. The I/O device processes the request and sets a device-ready
signal when it is ready to transfer data. The CPU reads in
this signal via another I/O address and checks the value. If the
signal is set, it performs the data transfer. If not, it loops back,
continually reading the value of the device ready signal.

Transferring Data
(continue)
Wait States:
When wait states are used, the processor requests data from an
I/O device, which then asserts a wait signal that is sent to the
CPU via the control bus. As long as the signal is asserted, the
CPU stays in a wait states, still outputting the address of the I/O
device and the value of the control signal needed to access the
device, but not doing anything else.The I/O device continues to
assert this wait signal until it is ready to send or receive data.
Once it is ready, the I/O device de-asserts it’s wait signal and
the CPU completes the data transfer.

Transferring Data
(continue)
wait states simplifies the job of the programmer. Unlike
polling , we need no additional code to accommodate the
variability of the timing of the I/O device; like polling, the
CPU does not perform any useful work while waiting for the
I/O device to become ready to transfer data. To make use of this
wasted CPU time, interrupts are developed.

Transferring Data
(continue)
Interrupts
Unlike polling or wait states, they do not waste time waiting for
the I/O device to become ready.
--When interrupts are used with I/O devices, the CPU may
output a request to the I/O device and, instead of polling the
device or entering a wait state, the CPU then continues
executing instructions, performing useful work.
--When the device is ready to transfer data, it sends an interrupts
request to the CPU; this is done via a dedicated signal on the
control bus.
--The CPU then acknowledges the interrupt, typically by
asserting an interrupt acknowledge signal, and completes the
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Types of Interrupts
¨ External interrupts
¨ Internal interrupts
¨ Software interrupts

External Interrupts
¨ External interrupts: are used by the CPU to interact with
input/output devices.
External interrupts improve system performance by allowing
the CPU to execute instructions, instead of just waiting for the
I/O device, while still performing the required data transfers.

Internal Interrupts
¨ Internal interrupts: occur entirely within the CPU; no
input/output devices play any role in these interrupts.
Internal interrupts could be used to allocate CPU time to
different tasks in a multitasking operating system. This
interrupts can also be used to handle exceptions that occur
during the execution of valid instructions.

Software Interrupts
¨ Software interrupts: are generated by specific interrupt
instructions in the CPU’s instruction set.

Processing Interrupts
Who services the interrupt?
¨ An interrupt triggers a sequence of events to occur
within the computer system. These events
acknowledge the interrupt and perform the actions
necessary to service the interrupt. These events only
occur if the interrupt is enabled.
¨ Interrupt is also serviced by software which is
written by the user, is called the handler, essentially a
subroutine.

Sequence of Events
¨ Do nothing(until the current instruction has been
executed)
¨ Get the address of the handler routine.(vector
interrupts only)
¨ Invoke the handler routine

Sequence of Events
(1)
¨ Do nothing (until the current instruction has been
executed)
If an execute routine is interrupted part way through, we would
have to save the contents of many of the internal registers of
the CPU, as well as the state information within the control
unit. In contrast, it is not necessary to save this information if
the execute routine has been completed.

Sequence of Events
(2)
¨ Get the Address of the Handler Routine
(Vectored interrupts only)
Vectored interrupts supply the CPU with information, the
interrupt vector, which is used to generate the address of the
handler routine for that interrupt.
Vectored interrupts are useful for CPUs that receive interrupt
requests from several devices via the same control line.

Sequence of Events
(3)
¨ Invoke the handler Routine
When the CPU accesses the handler routine, it pushes the
current value of the program counter into the stack and loads
the address of the handler routine into the program counter. The
handler routine then performs its tasks. When it is finished, it
returns to the correct location by popping the value of the
program counter off the stack.

Interrupt Hardware and Priority
Three hardware samples for interrupts:
¨ Hardware and Timing of a non-vectored interrupt for a single
device.
¨ Hardware and Timing of a vectored interrupt for a single
device.
¨ Hardware of multiple non-vectored interrupts

(a)Hardware of a non-vectored interrupt for a single device
An external device sent an interrupt to the CPU by asserting its interrupt
request (IRS) signal. When the CPU is ready to process the interrupt request,
it assert the its interrupt acknowledge signal (IACK), thus informing the I/O
device that is ready to proceed.
(b)Timing of a non-vectored interrupt for a single device
The device set the IRQ low, which cause the CPU set the IACK low. As
the handler routine proceeds, it transfers data between the CPU and the
interrupting device.
(a)
(b)
CPU
IRQ
IACK
Data
Device
valid
IRQ
IACK
Data
Interrupt Request
Interrupt Acknowledge
Data bus

(a)Hardware of a vectored interrupt for a single device
A vector interrupt is more complex. After acknowledge the interrupt,
the CPU must input an interrupt vector from the device and call an
interrupt service routine(handler); the address of this routine is a
function of the vector.
(b)Timing of a vectored interrupt for a single device
CPU
IRQ
IACK
Data
Device
Interrupt Request
Interrupt Vector
valid
IRQ
IACK
Data
(a)
(b)

Hardware for multiple non-vectored interrupts
In addition to enabling and disabling interrupts, we must also consider
the priority of the interrupts. In general, the second interrupt is processed
if its priority is higher than that of the interrupt currently being processed.
If not, it remains pending until the current handler routine is complete.
CPU
IRQ 0 IACK 0
IRQ 1
IACK 1
IRQ n
IACK n
Data
Device #0
Device #1
Device #n

Two methods used for prioritizing
multiple interrupts
• Daisy Chaining
• Parallel Priority

Daisy Chaining:
The interrupt request signals from the devices are wire-ORed
together. When the CPU receives an active IRQ input, it cannot know
which device generated the interrupt request. It sends out an
acknowledge signal and leaves it to the devices to work that out
among themselves.
CPU
IACKin
IRQ Device #n D
IACKout
IACKin
IACKout
IRQ Device#n-1D
IACKin
IRQ Device#0 D
IACKout
IACK
IRQ
Data
Interrupt Request
Vector

Possible values of IACKin and IACKout and their states
The invalid state (IACKin = 0 and IACKout = 1) is shown
to account for all possible value of IACKin and IACKout,
but a device should never be in this state.
IACKin IACKout State
1 0 Device interrupts CPU
0 1 Invalid state
Device is blocked from from
interrupting by a device with
higher priority(device may
not may not be issuing an
interrupt request
0 0
Device has priority to
interrupt but does not
1 1

Implementing priority interrupts in parallel
The IRQ input to the CPU ids generated as in the daisy chain configuration, using a
wired-OR of the IRQ signals from the devices. Note that buffers are needed to
prevent the signals from the values input to priority encoder. Unlike daisy chaining,
however, the IACK signal simply enables a priority device requesting an interrupt.
This value is placed on the data bus as the interrupt vector and is read in by the
CPU, which then proceeds as before.
CPU
Priority
encoder IRQ Device #1
IRQ Device #n
IRQ
Data
IACK
0 IRQ Device #0
1
n
Interrupt request
Vector

The most difficult part of handling the interrupt is
recognizing it and accessing the states to process the
interrupt. This is done every execute cycle, and could
be done in one or two ways.
1. Using separate FETCH1 and INT1 states
2. Modifying FETCH1 to support interrupts

1. Using separate FETCH1 and INT1 states
The branches that go to state FETCH1 are broken into two
branches. If interrupts are enabled (IE=1) and an interrupt is
pending (IP=1), these states branch to the beginning of the
interrupt handler routine, state INT1, rather than to FETCH1.
If either the IE or IP is 0, no interrupt is processed and the
CPU proceeds to FETCH1 to continue processing
instructions.
execute
routines FETCH1
execute
routines
IE’VIP’
IE^IP
FETCH1
INT1

2.Modifying FETCH1 to support interrupts
The micro-operations associated with the state can be
modified.
State FETCH1 would consist of two sets of micro-operations.
The CPU could branch to either FETCH2 or INT2.
FETCH 1 FETCH 2 Modified
FETCH
INT 2
IE’VIP’
IE^IP
FETCH 2

How to Access the Interrupt Handler?
1. CPU pushes the return address on to the stack
2. Reads in the interrupt vector
3.Jumps to the address corresponding to this vector,
1111(vector) 0000.

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