1. I YEAR M.TECH - I SEMESTER (REGULATION PVP12)
PRASAD.V.POTLURI SIDDHARTHA INSTITUTE
OF TECHNOLOGY (AUTONOMOUS)
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
(CSCS1T3) COMPUTER ORGANIZATION AND ARCHITECTURE
MODELPAPER
Time: 3 hours 5 X 14=70M
Answer any five questions
Q 1). a). Explain the different floating point representations in systems with suitable examples
7M
b). Simplify the Boolean function F together with the don’t care conditions in
i) Sum-of-Products form and ii) Product-of-Sums form.
F(w,x,y,z) = Σ ( 0,1,2,3,7,8,10), d(w,x,y,z) = Σ ( 5,6,11,15)
Draw the logic diagrams with NAND/NOR gates. 7M
Q 2). a). Explain the concept of bidirectional shift register with parallel load with circuit
diagram. 7M
b). Explain the hardware implementation of addition and subtraction operations with signed
magnitudes 7M
Q 3). a). Explain the mapping procedures in cache memory 7M
b). Explain the relation between address space and memory space in virtual memory with
suitable diagram 7M
Q 4). a). What are the differences between Programmed I/O and Interrupt-initiated I/O 5M
b). Explain the concept of DMA Transfer with appropriate diagram 9M
Q 5). a). Explain the Booth algorithm for multiplication of signed-2’s complement numbers.
Consider the given two numbers are -8 and -14. 8M
b). Draw the flow chart for addition and subtraction operations for two signed-2’s
complement data 6M
Q 6). a). Explain the different addressing modes available in x86 7M
b). Discuss the pipelining strategy with necessary timing diagram 7M
Q 7). a). Discuss CISC Vs RISC 7M
b). Write about the characteristics of Reduced Instruction Set Architecture 7M
Q 8). a). Explain the approaches available for Vector Computation 7M
b). Discuss Intel x86 Core Duo multicore organization 7M