This document presents a new adaptive phase locked loop (PLL) scheme that controls the loop bandwidth according to the locking status. It has two modes - a wide bandwidth mode for fast locking and a narrow bandwidth mode for minimizing output jitter. It achieves this by adaptively controlling the charge pump current, increasing it for wide bandwidth and decreasing it for narrow bandwidth. Simulation results show the adaptive PLL locks faster than a standard PLL and has lower phase noise. The adaptive scheme provides benefits of both fast locking and low noise with a simple design.

1. A New Adaptation Scheme For Low Noise and Fast
Settling Phase Locked Loop
Julien Roche∗ , Wenceslas Rahajandraibe† , Lahkdar Zad† and Gaetan Bracmard∗
∗ Atmel, Zone industriel Rousset,13106 Rousset, FRANCE
† IM2NP-CNRS, IMT Technopole de Chteau Gombert
13451 Marseille, France
Abstract— This paper presents a salient analog phase-locked
loop that adaptively controls the loop bandwidth according to
the locking status. An extended loop bandwidth enhancement is
achieved by the adaptive contol on the charge pump current.
First of all, when the phase error is large, such as in the locking
mode, the PLL increases the loop bandwidth and achieves fast
locking. On the other hand, when the phase error is small, this
PLL decreases the loop bandwidth and minimizes output jitters. Fig. 1. Block diagram of the adaptive phase locked Loop.
The relationships of performance aspects to design variables
are presented and the basic tradeoffs of the new concept are
discussed. A circuit implementation of the adaptive PLL is
prohibitively large. Thus, it is important that each circuit be
described in detail and simulation result of a 50M Hz PLL in a
designed for minimum power dissipation. Section II presents
0.15µm CMOS technology is presented.
analytical models that connect settling time, phase noise and
Index terms—PLL, loop bandwidth, frequency synthesis, clock the design variables. Section III introduces the adaptive PLL
recovery, adaptive systems, low jitter, fast locking time, timing architecture and discusses the advantages and tradeoffs of the
jitter.
concept. Section IV describes the circuit implementation, and
I. INTRODUCTION Section V presents a summary of estimated and simulated
results..
PLL have been widely used in comunication systems be-
cause PLL’s efficiently perform clock recovery and clock
II. DESIGN ISSUES
generation with relatively low implementation cost. In nearly
Random fluctuations in the output frequency of the PLL,
all the PLL applications, it is required to generate low noise
expressed in terms of jitter and phase noise, have a direct
and low spur signal while achieve fast setling. Conventional
impact on the timming accuracy where phase alignement is
analog PLL designs are focused on individual component op-
required and on the signal to noise ratio where frequency
timization to reduce noise and jitter. It is not well emphasized
translation is performed. Reference spurs are unwanted noise
that the overall noise performance of the PLL not only depends
sidebands that can occur at multiples of the comparison
on the design of the individual components, but also heavily
frequency, and can be translated by a mixer to the desired
depends on the choice of the loop bandwidth. And in order
signal frequency. They can mask or degrade the desired signal.
to improve the locking-time characterictics and PLL noise,
Lock time is the time that it takes for the PLL to change
digital or hybrid analog/digital PLL’s with loop bandwidth
frequencies, which depend on the size of the frequency step
stepping capability have been studied, [1], [2], at the expense
and what frequency error is considered acceptable. When the
of an increase of power consumption and die area. Some
PLL is switching frequencies, no data can be transmitted, so
other design solutions are proposed in the literature, [3], [4]
lock time of the PLL must lock fast enough as to not slow the
and use adaptive bandwidth method. For this adaptive PLL in
data rate. This section of the paper,briefly reviews the jitter
literature, the loop bandwidth enhancement is achieved by the
sources of a PLL and presents the bandwidth optimization
adaptive control on the reference frequency, the divide ratio,
method based on jitter analysis in the case of a charge-pump-
the charge pump current and time constant of the loop filter.
based PLL.
This paper presents a new enhancement to a conventional PLL.
The system illustrated in Fig.1 is a simple, low power and
A. Noise and Loop Bandwidth
low cost PLL, with the proposed adaptive bandwidth control.
In addition to low power, an important concern has been to There is a well-known trade-off in the design of a PLL
achieve a relatively wide capture range so that the circuit can [5] between the loop bandwidth, jitter performance and the
lock to the input in the presence of temperature and process locking speed. On Fig. 2, we can see that if we can control
PLL bandwidth, ωC , we can control noise transfer from one
variations. While cost, reliability, and performance issues make
source (phase detector noise, N divider noise, reference noise,
it desirable to integrate the system of Fig.1 on a single chip, the
total power dissipated in the high-speed blocks often becomes VCO noise) of the system to the output of the system. With

2. G(s)
CL(s) = (4)
1 + G(s)/N
It is assumed that the higher order terms are small relative
to the lower order terms so
Kφ ·KV CO
N ·Ctot )(1 + s · N · τ2 )
(
CL(s) = (5)
K ·KV ·τ
Fig. 2. (a) Transfer function multiplying all noise sources except the vco,
s2 + s · ( φN ·CCO 2 )
(b) Transfer function multiplying the vco noise tot
In which Ctot = C1 + C2 + C3 , τ2 is the second time
constant of the filter such as τ2 = R2 C2 . Defining the natural
this somewhat accurate model we know how to predict phase pulsation ωn and the damping factor ς as
noise. Within the loop bandwidth, the PLL phase detector
and reference signal are typically the dominant noise source,
Kφ · KV CO Kφ · KV CO
R2 C 2
and outside the loop bandwidth, the VCO noise is often the
·
ωn = ς=
N (C1 + C2 + C3 ) 2 N (C1 + C2 + C3 )
dominant noise source. Moreover, by controlling charge pump
gain, Kφ, we can control spur gain ewpressed in equation 1. (6)
Now consider a PLL, which is initially locked at frequency
There are several types of these spurious outputs with many
f 1, and then the N counter is changed such to cause the PLL
different causes. However, by far, the most common type of
to switch to frequency f 2. It should be noted that the value for
spur is the reference spur. These spurs appear at multiples
N that is used in all of these equations should be the value of
of the comparison frequency. Larger charge pump gains yield
N corresponding to f 2. This event is equivalent to changing
lower leakage dominated spurs at the critic frequency, Fspur ,
the reference frequency from f 1/N to f 2/N . The first term in
which is generally the comparaison frequency.
the numerator of equation 5 shows the primary effects, and the
second expression shows the secondary effects due to the zero.
Kφ · Z(2πF spur) · KV CO
SpurGain(Fspur ) = 20 log( ) The zero in the transfer function has a lot of effects on the
2πFspur
overshoot and the rise time, but has little effect on the lock
(1)
time. Using inverse Laplace transforms, the time frequency
When the charge pump is in the tri-state state, it is ideally
response is obtained from which the lock time of the PLL is
high impedance. However, there will be some parasitic leakage
derived as:
through the charge pump, VCO, and loop filter capacitors.
√
Of these leakage sources, the charge pump tends to be the
− ln( f2tol 1 1 − ς 2 )
dominant one. To predict the reference spur levels based on −f
Locktime = (7)
ς · ωn
leakage, let us adopt the following general rule 2:
Where f2 − f1 is the frequency step and tol corresponds
Ileakage to the maximum tolerance of the frequency at which the
Leakagespur = BaseLeakageSpur + 20 log( +
PLL is considered to be locked. The settling time is largely
Kφ
+SpurGain(F spur))(2) determined by the loop bandwidth, ωC , whose maximum is
approximately 1/10 of the reference frequency for stability
These results imply the fundamental constant for leakage- considerations [5]. In equation 7 we can see that Lock time
dominated spurs BaseLeakageSpur = 16dBc. Note that this is inversely proportional to the natural pulsation ωn and the
constant is universal, not part specific, and should apply to any damping factor ς. Refer to equations 8 and 9, Lock time
integer PLL. is inversely proportional to loop bandwidth, ωC , which is
So the loop bandwidth, ωC , is the most critical parameter of proportional to Kφ and so proportional to charge pump
the loop filter. current.
B. Settling Time and Loop Bandwidth
ωC = 2 · ωn · ς (8)
For the purposes of this chapter, calculations are simplified
by introducing the following open loop transfer functions and
Kφ · KV CO
ωC = R2 · C2 ·
the feedback transfer function: (9)
N (C1 + C2 + C3 )
Kφ · KV CO · Z(s) 1 To resume, if the loop bandwidth is large, the PLL takes
G(s) = and H = (3)
s N little time for locking and has large jitter reduction of the
With Kφ the charge pump/Phase detector gain, KV CO internal VCO noise, but cannot have a good suppression of the
the VCO gain, Z(s) the third order filter impdance and N external input noise. If, on the other hand, the loop bandwidth
the divider ratio. We can write that the closed-loop transfer is small, the PLL can have large input jitter reduction, but
function of the system in Fig. 1 can be expressed as [9]: takes longer time for locking and leaves much of the internal

3. VCO noise unreduced. Therefore, it is desirable to optimize
the loop bandwidth such that the PLL has sufficient noise
reduction of both the external input and the VCO. So, we
have a wide mode bandwidth during the acquisition time and
a narrow mode bandwidth for phase noise improvement.
III. CIRCUIT DESCRIPTION AND ADAPTIVE BANDWIDTH
IMPLEMENTATION
Each parameter of the PLL has to be chosen optimally in
order to achieve short lock time, low phase noise, low power
consumption, and fully integration of the loop filter capacitors.
Third order passive loop filter has been adopted in order to
minimize the spurious gain. A VCO gain of 55M Hz/V , a
charge pump current ICP = 160µA in Wide-Band mode, a Fig. 4. Modulated current source for the charge pump
loop filter with the following filter components: C1 = 5pF ,
C2 = 166pF , C3 = 0.7pF , R2 = 1.4kΩ, R3 = 12.8kΩ has
been adopted. The theoretical lock time computed from these
control voltage and so by the state of the system. After that,
values is somewhat few µs, which depend on the frequency
I use a regulated cascode source to charge the charge pump
step and specification tolerance. An important consideration in
element. With this solution we have a high output impdance
the adaptive scheme is to maintain a phase margin superior to
and a constant current value a the output of the current source
45deg, as shown in Fig.3, and an optimum-damping factor, ς
(independant of the output load) Fig.5.
around 0.7 [5] when the loop is switched from the wide-BW
to narrow-BW mode, so that the loop stability and settling
behavior are optimized in both modes.
Fig. 5. regulated cascode behavior
Bias current is then injected to the charge pump. The U P
and DOW N signals from the phase frequency detector control
the switches of the charge pump. Current is then integrated
through 3rd order loop filter to control a two stage ring
Fig. 3. Phase Margin for different bandwidth mode: ωc1 /2π loop bandwidth
for Narrow-BW mode and ωc /2π loop bandwidth for Wide-BW mode oscillator. Each stage is a differential delay cell that consists
of an input NMOS pair M 1 and M 2, a cross-coupled PMOS
As we have seen in II, by controling the Charge Pump pair M 3 and M 4 to sharpen the edge of the output signal,
current, we can control loop bandwidth. So to have this two and a frequency control PMOS pair M 5 and M 6 fig. 6.
modes bandwidth we use a modulated source current. This
adaptation technique is especially effective in the case of large
frequency steps or small data transition. First, PLL settles to
within a small residual frequency error in a very short time
in wide BW mode. Then, the additional time required for the
loop to settle to the final frequency value in the narrow- BW
mode is greatly reduced.
Fig.4 shows the simplified schematic of the adaptive current
steering charge pump. The charge pump current IUP and
IDOWN can be biased to either 80µA for the narrow-BW
mode or 160µA for the wide-BW mode, controlled by the
Fig. 6. Delay cell schematic and the differential VCO
control voltage of the VCO through the control transistor M 1
as shown in Fig.4. M 1 send a current controled by the VCO

4. IV. SIMULATION RESULTS
Behavior of the adaptive PLL is estimated and compared
to that its counterpart without adaptation. Fig. 7 shows the
result for both cases. Estimated lock time for the proposed
adaptive PLL is 0.9µs compared to the 3.2µs for the PLL
without adaptation.
Fig. 9. Settling time simulation for a PLL with adaptation and non-periodical
reference signal.
Fig. 7. Estimated settling time for PLL with adaptation and without
adaptation and PLL without adaptation.
Figure 8 shows the phase noise contribution from different
loop components based on the transistor level simulation.
the overall phase noise is estimated and also provided in
figure 8. It can be seen that the phase noise of the VCO Fig. 10. layout of the proposed adaptive PLL
is suppressed inside the loop bandwidth, whereas the phase
noise from the other loop component is attenuated outside the
V. CONCLUSION
loop bandwidth. The overall phase noise at 1M Hz frequency
offset is −130dBc/Hz and the dominant contributor is the This article demonstrates the feasibility of an adaptive band-
VCO. The simulated current consumption is 8mA with supply width PLL allowing achieving frequency synthesis, frequency
voltage of 1.8v. modulation and clock and data recovery with fast locking
and high level precision. Contrarily to standard techniques,
the proposed method offers a modulation bandwidth solution
with simple loop PLL. We are waiting for the test chip
measurements to compare with the simulation results
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As shown in figure 10, the die area is 600µm × 300µm in
0.15µm Cmos technology with on chip loop filter.