This document presents a simplified space vector pulse-width modulation (SVPWM) scheme for three-phase cascaded H-bridge inverters. It treats each unit as a three-level inverter and uses three-level SVPWM to modulate each unit individually. Duty cycles from sector 1 are mapped to obtain duty cycles for other sectors. This simplifies the process compared to conventional multilevel SVPWM. Simulation and experimental results validate the presented SVPWM scheme, which provides a higher effective switching frequency while maintaining the same DC-link voltage utilization as conventional SVPWM, with significantly reduced FPGA resource utilization.