Subject: Microprocessor and Application Week 2 Data Transfer Operation

1. MCS-51 Data Transfer
Instructions
MCS51 Instruction 12 April 2016

2. Developing
2 April 2016 MCS51 Instruction 2
Save / Load
Build
Assembly file
(.asm)
Hex file
Emulator
Circuit
Simulator
Microcontroller
Board
Assembly Editor

3. Assembly Language
• Low-level programming
• Specific to physical computer architecture
Assembly Language structure
• [Header]
• [Program Instructions]
• [END Instruction]
MCS51 Instruction 32 April 2016

4. Assembly Language Sample
ORG 00H
MOV A, #45H
ANL A, P1 ; Get status from sensors and process
MOV R0, P2 ; Get setting
Loop:
MOV P3, A ; Send Output to Display unit
DJNZ R0, Loop
END
MCS51 Instruction 42 April 2016

5. • Appendix 2: MCS-51 Instruction set
2 April 2016 MCS51 Instruction 5

6. Instruction set
• MCS51 is 8 bit microcontroller, there for 28 or
256 difference instructions possible for CPU.
• Types of instructions
– Data Transfer Instruction
– Logical Instruction
– Arithmetic Instruction
– Branch Instruction
– Bit Operation Instruction
MCS51 Instruction 62 April 2016

7. Machine Code
2 April 2016 MCS51 Instruction 7

8. Description of MCS51 instruction’s
parameter
• A
• Rn
• Ri
• Rx (Ry)
• Address
• #X
• #X16
• Rel
• Bit
• C
MCS51 Instruction 82 April 2016

9. Data Transfer Instructions
• These instructions move the content of one register to
another one. The register which content is moved
remains unchanged. If they have the suffix “X” (MOVX),
the data is exchanged with external memory.
• MOV
• MOVC
• MOVX
• PUSH
• POP
• XCH
MCS51 Instruction 92 April 2016

10. MOV A, Rn
• MOV A, R3
• MOV A, 03h
MCS51 Instruction 102 April 2016

11. MOV A, #X
• MOV A, #78H
• MOV A, #00101010B
MCS51 Instruction 112 April 2016

12. MOV @Ri, #X
• MOV @R1, #78H
• MOV @R0, #00101010B
MCS51 Instruction 122 April 2016

13. MOV DPTR, #XX
• MOV DPTR, #78E5H
• MOV DPTR, #1101010100101010B
MCS51 Instruction 132 April 2016
78 E5
DPH DPL
DPTR

14. MOV @Ri, A
E E
0001
0002
0003
0004
0005
…
0 4
Ri
Acc
Data Memory
Ri is R0 or R1 register
MCS51 Instruction 142 April 2016
3 5
7 E
6 8
E E
5 F

15. MOV A, @Ri
6 8
0001
0002
0003
0004
0005
…
0 3
Ri
Acc
Data Memory
Ri is R0 or R1 register
MCS51 Instruction 152 April 2016
3 5
7 E
6 8
E E
5 F

16. XCH A, @Ri
1 5
0001
0002
0003
0004
0005
…
0 5
Ri
Acc
Data Memory
Ri is R0 or R1 register
MCS51 Instruction 162 April 2016
3 5
7 E
6 8
E E
5 F

17. PUSH Rx
1 5
0006
0007
0008
0009
000A
000B
0 7
SP
Rx
Data Memory
Increase SP. then …
To address SP+1
MCS51 Instruction 172 April 2016
0 D
0 0
1 5
0 0
0 0
0 0

18. POP Rx
4 B
0006
0007
0008
0009
000A
000B
0 A
SP
Rx
Data Memory
Then decrease SP.
from address SP
MCS51 Instruction 182 April 2016
0 D
0 0
1 5
E F
4 B
0 0

19. XCH A, Rn
MCS51 Instruction 192 April 2016

20. XCHD A, @Ri
1 5
0001
0002
0003
0004
0005
0006
0 5
Ri
Acc
Data Memory
Ri is R0 or R1 register
MCS51 Instruction 202 April 2016
3 5
7 E
6 8
E E
3 F
E 2